IEEE Standard 1149.6:: Outline

Outline
IEEE Standard 1149.6:

Boundary-Scan Testing of • Scope and objectives of 1149.6
Advanced Digital Networks • AC coupling, differential signalling
J. M. Martins Ferreira • 1149.6 defect model
FEUP / DEEC - Rua Dr. Roberto Frias
• Testing AC-coupled / differential networks
4200-537 Porto - PORTUGAL
(placement of BS cells, new instructions)
Tel. 351 225 081 748 / Fax: 351 225 081 443
(jmf@fe.up.pt / http://www.fe.up.pt/~jmf) • 1149.6: test driver and test receiver
• Conclusion
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 1 © J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 2
Scope and objectives AC-coupling, differential

signalling
• Scope of 1149.6: Structural test of high- • Single-ended signalling with AC-coupling
speed digital networks Transmitter
C
Receiver
TX:
• Objectives TX
R
RX RX:
– Cope with differential and/or AC-coupled

interconnections, enabling high fault coverage • Differential signalling with AC-coupling and
with minimum impact on mission logic bias provision
– Reuse as much as possible IEEE 1149.1 tools Transmitter
Positive C
Receiver
(ensure compatibility with 1149.1 / 4)

R
+
011010 Vref 011010
-
R
Negative
1149.6 defect model 1149.6 defect model (cont.)
C C
Transmitter 1 2 1 Receiver Transmitter Receiver Transmitter 1 2 1 Receiver Transmitter Receiver
delay delay
1 1 +
1 1 1 1 +
1 1
R - R -
2 C 2 2 C 2
1 2 1 2
delay TX1 RX1 delay TX1 RX1
TX2 2 RX2 TX2 2 RX2
Testing AC-coupled / 1149.6 drivers and receivers

differential networks
• BS cell placement has an impact on circuit • An AC testing instruction selects Mode
performance and defect coverage the AC Mode, and a test signal Mission 0
1
Transmitter
Positive C
suited for AC-coupled U
AC Signal
0
1
networks is applied to the pin

R
+ Receiver
Vref AC Mode
-
R
Negative
C
• A test receiver at the input cell derives logic
• Modified BS cells must ensure: level information from the incoming AC /
– Signal transmission over AC-coupled nets DC test signal Mission Mode
– Logic level detection from AC test signals 0

1
Test
Receiver C U
AC Mode
1149.6 instructions for AC- EXTEST_PULSE
coupled differential networks
Pulse Width
• EXTEST_PULSE generates a transition TCK

... ...
even when the new test value at the driver TAP State
... ...
pin retains its previous value
TL Reset Update-XR Run-Test / Idle Select-DR Capture-DR
• EXTEST_TRAIN provides multiple AC Test Signal

...
additional transitions (to cope with transient Update Point Capture Point Mode
AC Pin Driver
... 0 Data
Data Inverted Data Data
conditions, when necessary)

1
AC Pin
Driver
0
Update FF 1
• Both cause the driver pins to change state UpdateDR

D
CLK
Q
AC Mode
at least twice in Run-Test / Idle Train / Pulse

Train /
Pulse
D Q
EXTEST_PULSE 0
RTI State AC Test Signal
CLK
EXTEST_TRAIN 1
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 9 © J. M. Martins Ferreira - University of Porto (FEUP
TCK
/ DEEC) 10
EXTEST_TRAIN General AC pin driver

Mode
Pulse Width Pulse Width
Mission 0
TCK
... ... 1
C U 0
TAP State Mode
1
... ...
AC Signal Mission
TL Reset Update-XR Run-Test / Idle Select-DR Capture-DR
0 Data
AC Mode 1
Shift Out
ShiftDR
...
0
AC Test Signal Capture FF Update FF 1
0
D Q D Q
1
Update Point Capture Point Mode
AC Pin Driver CLK CLK AC Mode
... 0 Data Shift In ClockDR UpdateDR

Data Inverted Data Data Inverted Data Data
1
AC Pin
Driver
0
Update FF 1 Train / Pulse Train /
Mode AC Mode Pulse
D Q
UpdateDR BYPASS 0 X X
CLK AC Mode
EXTEST 1 0 X
D Q
Train / Pulse RTI State EXTEST_PULSE 1 1 0
Train /
Pulse CLK
EXTEST_TRAIN 1 1 1
D Q
EXTEST_PULSE 0 TCK
RTI State AC Test Signal
CLK
EXTEST_TRAIN 1
© J. M. Martins Ferreira - University of Porto (FEUP
TCK
/ DEEC) 11 © J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 12
The test receiver Operation of the test receiver
• Extracts test data even in the presence of • When an AC testing Mission Mode
instruction is loaded,
0
an unknown offset Test

1
the test receiver detects Receiver C U
• The solution is to look for valid transitions AC Mode
transitions at the input pin

(with a minimum voltage swing ΔV and a and sends the logic level information to the
maximum transition time Δt) capture / shift stage of the BS cell
• Single-ended signal Mission Mode
• When the current instruction is EXTEST,
reception: 0
1 the test receiver sends the input logic level
to the capture / shift stage of the BS cell
Test
Receiver C U
AC Mode
The test receiver : transition The test receiver (AC Mode /

detection and offset removal DC Mode test receiver model)
• A delay element and an hysteretic • Test receiver model supporting AC Mode
comparator (AC testing instructions) and DC Mode
– Detect input signal transitions (by comparing a (EXTEST):
signal with a delayed version of itself)
+ -
+
Input
-
R AC mode Set
– Provide an output at standard logic levels
.
or a time-decaying variant: C DC mode
Init data D Q
(removing unknown offsets)

CLK
Init clock
.
Vbias
Clear
+
- +
In+:
+
-
R
In-: IEEE std 1149.6, p. 27: “two simple comparators, one to sense
C
Out: rising edges and the other to sense falling edges; two VHyst voltage
sources, to set the hysteresis voltage for the comparators; and a
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 15
D-type flip-flop memory element, to hold the reconstructed signal.”
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC) 16
Test receiver support for AC Test receiver support for (DC)
testing instructions EXTEST instruction
V V
+ - +A + - +A
+ +
A A
Vhyst - Vhyst -
Set Set
Vin R Vin
Init Data Init Data
.
D Q Vbias D Q
Hysteretic Hysteretic
C
Init CLK CLK comparator Init CLK CLK comparator
FF FF
.
V = V
-A +B Clear Clear
+ +
Vhyst B Vhyst B
- -
Vin
- + V
-B
Vin
V
- + V
-B
V
V
-B
V Vhyst
V
V = V
+A
+A
Vbias
V
-A +B
V - Vhyst Vhyst
Vhyst
V
Set
+B Vbias
V
The output of the hysteretic The delay network (RC) is
comparator FF will also be Clear replaced by a bias voltage, Set
as shown when the input since transition detection is Clear

Q (HC FF)
signal Vin decays over time no longer required
Q (HC FF)
BS cell with test receiver BS cell with test receiver

Mode (DC Mode) Mode
0 0
1 1
Capture FF Update FF 1149.6 std 6.2.2.1-d): Capture FF Update FF
1149.6 std 6.2: 0 0
Shift In D Q D Q
“Whenever a test receiver Shift In D Q D Q
“When an AC testing
1 1
CLK CLK
is operating in the level- CLK CLK
instruction is in effect, it is ShiftDR ShiftDR

detection mode on an AC
the purpose of the test
input pin, the test receiver
receiver to reconstruct the
output shall be cleared of
+ - + -
test waveform driven by the

+ +
Input Input
prior history on the falling

- -
upstream driver when

R AC mode Set Set
edge of TCK in the

.
.
either AC- or DC-coupling C DC mode D Q
DC mode D Q
Capture-DR TAP Controller

Hysteretic Hysteretic
comparator FF
is used. It does this by
CLK CLK comparator
FF
.
.
state.”
reacting to the edges and Vbias
+
Clear Vbias
+
Clear
not the levels of the input

- -
- + 1149.6 std 6.2.2.2-a): - +
waveform. When (DC) Capture-DR “the output of the test Capture-DR
EXTEST is in effect, the receiver is only relevant

TCK EXTEST TCK EXTEST
test receiver behaves as a during the window of time

level detector.” between the falling and A valid input (> Vbias+Vhyst or < Vbias – Vhyst)
EXTEST_TRAIN
rising edges of TCK in the

EXTEST_PULSE
Exit1-DR will force the HC FF into Set or Clear;

© J. M. Martins Ferreira - University of Porto (FEUP / DEEC) Exit2-DR
19
Capture-DR (…) state.”
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC) otherwise the Capt. FF state will be retained20
Test receiver operation BS cell with test receiver
(DC Mode) (AC Mode) Mode
1149.6 std 6.2.3.1-d): 1
• Valid input: set / clear the HC FF

Capture FF Update FF
“Whenever a test receiver Shift In 0
1
D Q D Q
is operating in the edge- CLK CLK
– Set: Vin–Vhyst > Vbias (i.e. Vin > Vbias+Vhyst) detection mode on an AC ShiftDR
input signal, the test

– Clear: Vin+Vhyst < Vbias (i.e. Vin < Vbias-Vhyst) receiver output shall be Input
+ -
+
cleared of prior history at a -
• Invalid input (within the test window): the

R AC mode Set
time between exiting the
.
C D Q
Shift-DR TAP controller Hysteretic
Capture FF will retain the current value

CLK comparator
state and before entering FF
.
Clear
Clear Capt. FF Set (…) Update-DR (…).” +
-
Vin - Vhyst state
+ - +
A
-
Set Set
Valid transitions will force
from to TCK
Capt. FF Capt. FF
the HC FF into Set or
.
Vbias D Q
/TCK CLK Clear Clear; if no valid transitions

occur, the Capture FF state
.
EXTEST_TRAIN
HC FF Clear
EXTEST_PULSE
will be retained
+
Vin + Vhyst B
-
Vbias - Vhyst Vbias Vbias + Vhyst Exit1-DR
Exit2-DR
Test receiver operation Conclusion

(AC Mode)
• Valid input: set / clear the HC FF • Industry-driven 1149.6 enables structural
• Invalid input (within the test window): the testing capability of AC-coupled single-
Capture FF will retain the current value ended or differential networks
Vin - Vhyst
TCK
• An underlying fault model facilitates high
defect coverage
+
A
-
Set
Vin R from to TAP State Shift-DR Exit1-DR Update-DR Run-Test/Idle Sel.-DR-Scan Capture-DR
Capt. FF Capt
.
• Compatibility with 1149.1 enables minimal

D Q
/TCK CLK Driver Signal Data N-1 Data N Inverted Data NData N
C
.
-
B
HC FF Clear
impact on 1149.1 tools
Vin + Vhyst Test receiver output
Initial State Data Inverted Data Data or Initial State
Edge-Detection Intialise Point Detect Edges (if any)

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IEEE Standard 1149.6:: Outline

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Outline

IEEE Standard 1149.6:

Scope and objectives AC-coupling, differential

– Cope with differential and/or AC-coupled

(ensure compatibility with 1149.1 / 4)

Testing AC-coupled / 1149.6 drivers and receivers

networks is applied to the pin

– Logic level detection from AC test signals 0

• EXTEST_PULSE generates a transition TCK

• EXTEST_TRAIN provides multiple AC Test Signal

conditions, when necessary)

• Both cause the driver pins to change state UpdateDR

at least twice in Run-Test / Idle Train / Pulse

EXTEST_TRAIN General AC pin driver

... 0 Data Shift In ClockDR UpdateDR

an unknown offset Test

the test receiver detects Receiver C U

• The solution is to look for valid transitions AC Mode

transitions at the input pin

The test receiver : transition The test receiver (AC Mode /

– Provide an output at standard logic levels

(removing unknown offsets)

as shown when the input since transition detection is Clear

BS cell with test receiver BS cell with test receiver

instruction is in effect, it is ShiftDR ShiftDR

test waveform driven by the

prior history on the falling

upstream driver when

edge of TCK in the

Capture-DR TAP Controller

not the levels of the input

- + 1149.6 std 6.2.2.2-a): - +

waveform. When (DC) Capture-DR “the output of the test Capture-DR

EXTEST is in effect, the receiver is only relevant

test receiver behaves as a during the window of time

rising edges of TCK in the

Exit1-DR will force the HC FF into Set or Clear;

1149.6 std 6.2.3.1-d): 1

• Valid input: set / clear the HC FF

is operating in the edge- CLK CLK

input signal, the test

cleared of prior history at a -

• Invalid input (within the test window): the

Shift-DR TAP controller Hysteretic

Capture FF will retain the current value

state and before entering FF

/TCK CLK Clear Clear; if no valid transitions

Test receiver operation Conclusion

• Compatibility with 1149.1 enables minimal

Initial State Data Inverted Data Data or Initial State

Edge-Detection Intialise Point Detect Edges (if any)

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