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CISC RISC
The two's-complement system has the advantage of not requiring that the
addition and subtraction circuitry examine the signs of the operands to
determine whether to add or subtract. This property makes the system both
simpler to implement and capable of easily handling higher precision
arithmetic. Also, zero has only a single representation, obviating the
subtleties associated with negative zero, which exists in ones'-complement
systems.
Memory mapped I/O is mapped into the same address space as program
memory and/or user memory, and is accessed in the same way. I/O
Computer Architecture Question Bank 2
mapped I/O (also known as port mapped I/O) uses a separate, dedicated
address space and is accessed via a dedicated set of microprocessor
instructions. If you're using a microprocessor or microcontroller that
doesn't support port mapped I/O, then you have to use memory mapped
I/O.
Microprocessors that support port mapped I/O include Intel x86 and
compatible processors, and also the Zilog Z80 and Intel 8080.
Microprocessors that DON'T support port mapped I/O (and hence require
the use of memory mapped I/O) include the Motorola 6800 and the MOS
Technology 6502.
The advantage of port mapped I/O is that it makes for neater code and
requires fewer external components to implement I/O. However, it adds to
the complexity and pin count of the microprocessor itself.
IDE and SCSI controllers can use any of three data transfer methods to
move data to and from system memory. The first method, Programmed
I/O (PIO), relies entirely on the host PC's CPU to conduct data back and
forth between the controller and memory.
The other two methods of data transfer, which are more sophisticated than
PIO, are known as third-party DMA and first-party DMA. Direct memory
access (DMA) uses special hardware, either on the host system's
motherboard or on a controller card, to facilitate the transfer of data to and
Computer Architecture Question Bank 4
from system memory without involving the CPU.
The push instruction pushes a value onto the stack. The value is put ON
TOP of the stack. The stack's size will increase by one.
The pop instruction takes the TOP VALUE from the stack and assigns it to
the specified variable. The stack's size will decrease by one. If there are no
values on the stack (e.g. the stack's size is equal to zero), then the error
flag will be set.
Digital computer systems consist of three distinct units. These units are as
follows:
Input unit
Output unit
Control lines
These allow the CPU to control which operations the devices attached
should perform, I.E. read or write.
Address lines
Data lines
A register is a very small temporary holding area (usually 64 bits) for data.
These registers act as buffers between the CPU and the memory.
The use of registered memory increases system reliability, but also slows
the system down a very slight bit as data must be moved through the
registers.
It takes same time to any address of the memory as the first address. It is
also called read/write memory. The storage of data and instructions inside
the primary storage is temporary.
The memories, which loose their content on failure of power supply, are
known as volatile memories. So now we can say that RAM is volatile
memory.
System software refers to the files and programs that make up your
computer's operating system. System files include libraries of functions,
system services, drivers for printers and other hardware, system
preferences, and other configuration files. The programs that are part of
the system software include assemblers, compilers, file management tools,
system utilities, and debuggers.
The system software is installed on your computer when you install your
operating system. You can update the software by running programs such
as "Windows Update" for Windows or "Software Update" for Mac OS X.
Unlike application programs, however, system software is not meant to be
run by the end user. For example, while you might use your Web browser
every day, you probably don't have much use for an assembler program
(unless, of course, you are a computer programmer).
Since system software runs at the most basic level of your computer, it is
called "low-level" software. It generates the user interface and allows the
operating system to interact with the hardware. Fortunately, you don't have
Bootloaders
Fetch: Read the next instruction from memory into the CPU.
Interrupt: If interrupts are enabled and an interrupt has occurred, save the
current process state and service the interrupt.
The memory address register (MAR) holds the address of the memory
location where the next instruction is to be executed. While the first
instruction is being executed, the address of the next memory location is
held by it. The Memory Address Register is half of a minimal interface
between a micro program and computer storage. The other half is a
memory data register.
Far more complex memory interfaces exist, but this is the least that can
work.
A stack is a list in which all insertions and deletions are made at one end,
called the top. The last element to be inserted into the stack will be the first
to be removed. Thus stacks are sometimes referred to as Last In First Out
(LIFO) lists.
It is given by T = (N*S)/R
'N' is the total number of steps required to complete program execution. 'N'
is the actual number of instruction executions, not necessarily equal to the
Computer Architecture Question Bank 12
total number of machine language instructions in the object program.
Some instructions are executed more than others (loops) and some are not
executed at all (conditions).
Displacement Addressing:
1) Relative addressing
2) Base register addressing
source Register)
4) Register indirect
Stack Addressing:
Stack is a linear array of locations referred to as last-in first out queue. The
stack is a reserved block of location, appended or deleted only at the top of
the stack. Stack pointer is a register which stores the address of top of
stack location. This mode of addressing is also known as implicit
addressing.
(b) the instant at which the first character of the response is received at a
terminal.
Memory caching is effective because most programs access the same data
or instructions over and over. By keeping as much of this information as
possible in SRAM, the computer avoids accessing the slower DRAM.
Most modern PCs also come with external cache memory, called Level 2
(L2) caches. These caches sit between the CPU and the DRAM. Like L1
caches, L2 caches are composed of SRAM but they are much larger.
Instructions that include a direct address require three bytes of storage: one
for the instruction code, and two for the 16-bit address.
MOV Move
An 'X' in the name of a data transfer instruction implies that it deals with a
register pair (16-bits);
Access time is the time required for a computer to process data from the
processor and then retrieve the required data from a storage device, such
as a hard drive. For hard drives, disk access time is determined by a sum
of the spin-up time, seek time, rotational delay and transfer time.
Seek time is one of the three delays associated with reading or writing
data on a computer's disk drive, and somewhat similar for CD or DVD
drives. The others are rotational delay and transfer time, and their sum is
access time. In order to read or write data in a particular place on the disk,
the read/write head of the disk needs to be physically moved to the correct
place. This process is known as seeking, and the time it takes for the head
to move to the right place is the seek time.
Addressing modes affect both the amount of time required for executing
an instruction and the amount of memory required for its storage. For
example, instructions that use implied or register addressing, execute very
quickly since they deal directly with the processor’s hardware or with data
already present in hardware registers. Most important, however is that the
entire instruction can be fetched with a single memory access. The number
of memory accesses required is the single greatest factor in determining
execution timing. More memory accesses therefore require more execution
time. A CALL instruction for example, requires five memory accesses:
three to access the entire instruction and two more to push the contents of
the program counter onto the stack.
The processor can access memory once during each processor cycle. Each
cycle comprises a variable number of states. (See below and the appendix
of “USING THE SDK-85 MICROPROCESSOR TRAINER”). The length
of a state depends on the clock frequency specified for your system, and
may range from 480 nanoseconds to 2 microseconds. Thus, the timing for
a four state instruction may range from 1.920 microseconds through 8
microseconds. (The 8085 have a maximum clock frequency of 5 MHz and
therefore a minimum state length of 200 nanoseconds.)
A hardware interrupt causes the processor to save its state of execution via
a context switch, and begin execution of an interrupt handler.
Q39 What Is The Difference Between Single Bus And Multiple Bus
Structure?
Single Bus structure and multiple bus structures are types of bus or
computing. A bus is basically a subsystem which transfers data between
the components of Computer components either within a computer or
between two computers. It connects peripheral devices at the same time.
Control lines: These allow the CPU to control which operations the
devices attached should perform, I.E. read or write.
Example :
Notice that the names of the immediate instructions indicate that they use
immediate data. Thus, the name of an add instruction is ADD; the name of
an add immediate instruction is ADI.
The LXI instruction (load register pair immediate) is even more unusual in
that its immediate data is a 16-bit value. This instruction is commonly
used to load addresses into a register pair. As mentioned previously, your
program must initialize the stack pointer; LXI is the instruction most
commonly used for this purpose. For example, the instruction LXI SP,
3OFFH loads the stack pointer with the hexadecimal value 30FF.
A logic gate performs a logical operation on one or more logic inputs and
produces a single logic output. The logic normally performed is Boolean
logic and is most commonly found in digital circuits. Logic gates are
primarily implemented electronically using diodes or transistors, but can
also be constructed using electromagnetic relays, fluidics, optics,
molecules, or even mechanical elements.
The output Q is true if input A AND input B are both true: Q = A AND B
An AND gate can have two or more inputs, its output is true if all inputs
are true.
0 0 0
0 1 0
1 0 0
1 1 1
This is an AND gate with the output inverted, as shown by the 'o' on the
output.
0 0 1
0 1 1
1 0 1
1 1 0
The output Q is true if input A OR input B is true (or both of them are
true): Q = A OR B
An OR gate can have two or more inputs; its output is true if at least one
input is true.
0 0 0
0 1 1
1 0 1
1 1 1
This is an OR gate with the output inverted, as shown by the 'o' on the
output.
The output Q is true if NOT inputs A OR B are true: Q = NOT (A OR B)
A NOR gate can have two or more inputs, its output is true if no inputs are
true.
0 0 1
0 1 0
1 0 0
1 1 0
The output Q is true if either input A is true OR input B is true, but not
when both of them are true:
Q = (A AND NOT B) OR (B AND NOT A)
This is like an OR gate but excluding both inputs being true.
The output is true if inputs A and B are DIFFERENT.
EX-OR gates can only have 2 inputs.
0 0 0
0 1 1
1 0 1
1 1 0
Input Output
1 0
0 1
The values inside the squares are copied from the output column of the
truth table, therefore there is one square in the map for every row in the
truth table. Around the edge of the Karnaugh map are the values of the two
input variable. A is along the top and B is down the left hand side. The
diagram below explains this:
The values around the edge of the map can be thought of as coordinates.
So as an example, the square on the top right hand corner of the map in the
above diagram has coordinates A=1 and B=0. This square corresponds to
the row in the truth table where A=1 and B=0 and F=1. Note that the value
in the F column represents a particular function to which the Karnaugh
map corresponds.
If you add a device that does not support Pnp, the manufacturer will
hopefully provide explicit directions on how to assign IRQ values for it. If
you don't know what IRQ value to specify, you'll probably save time by
calling the technical support phone number for the device manufacturer
and asking.
The J-K flip-flop is the most versatile of the basic flip-flops. It has the
input- following character of the clocked D flip-flop but has two inputs,
traditionally labeled J and K. If J and K are different then the output Q
takes the value of J at the next clock edge.
If J and K are both low then no change occurs. If J and K are both high at
the clock edge then the output will toggle from one state to the other. It
can perform the functions of the set/reset flip-flop and has the advantage
that there are no ambiguous states. It can also act as a T flip-flop to
accomplish toggling action if J and K are tied together. This toggle
application finds extensive use in binary counters.
Q64 What is D – Type Flip flop?
The D flip-flop tracks the input, making transitions with match those of
the input D. The D stands for "data"; this flip-flop stores the value that is
on the data line. It can be thought of as a basic memory cell. A D flip-flop
can be made from a set/reset flip-flop by tying the set to the reset through
an inverter. The result may be clocked.
One disadvantage of the S/R flip-flop is that the input S=R=0 gives
ambiguous results and must be avoided. The J-K flip-flop gets around that
problem.
The T or "toggle" flip-flop changes its output on each clock edge, giving
an output which is half the frequency of the signal to the T input.
There are two types of S-R flip-flops: Active High and Active Low. Like
all flip-flops, both types of S-R devices are pulsed with a clock.
Depending on the input values, the two complementary outputs (Q and Q')
change according to the flip-flop's logical function at the moment of the
clock input's active transition.
A ROM chip is also non volatile so data stored in it is not lost when power
is turned off.
– Shift
– Load
– Clear
– Increment
– …
LOGIC MICROOPERATIONS
-- Specify binary operations on the strings of bits in registers
-- Logic microoperations are bit-wise operations, i.e., they work on the
individual bits of data
-- useful for bit manipulations on binary data
Computer Architecture Question Bank 41
-- useful for making logical decisions based on the bit value
-- There are, in principle, 16 different logic functions that can be defined
over two binary input variables.
Computer processors were for a long period constructed out of small and
medium-scale ICs containing the equivalent of a few to a few hundred
transistors. The integration of the whole CPU onto a single VLSI chip
therefore greatly reduced the cost of processing capacity. From their
humble beginnings, continued increases in microprocessor capacity have
rendered other forms of computers almost completely obsolete (see history
of computing hardware), with one or more microprocessor as processing
element in everything from the smallest embedded systems and handheld
devices to the largest mainframes and supercomputers.
Since the early 1970s, the increase in capacity of microprocessors has been
known to generally follow Moore's Law, which suggests that the
complexity of an integrated circuit, with respect to minimum component
cost, doubles every two years. In the late 1990s, and in the high-
performance microprocessor segment, heat generation (TDP), due to
switching losses, static current leakage, and other factors, emerged as a
leading developmental constraint[
In both cases, the higher the value, the more powerful the CPU. For
example, a 32-bit microprocessor that runs at 50MHz is more powerful
than a 16-bit microprocessor that runs at 25MHz.
The ability to execute a stored set of instructions to carry out user defined
tasks.
The ability to be able to access external memory chips to both read and
write data from and to the memory.
• When memory is accessed, the contents of the MAR get sent to the
memory unit’s address lines
– The values in register R1 get sent over the bus to the data
input lines of the memory
DR Data register
M Equivalent to M[AR]
– Addition
– Subtraction
– Increment
– Transfer/Load
– etc. …
R3 R1 + R2’+ 1 subtraction
R1 R1 + 1 Increment
R1 R1 - 1 Decrement
Binary Adder
FA C3 FA C2 FA C1 FA C0
C4 S3 S2 S1 S0
Binary Adder-Subtractor
B3 A3 B2 A2 B1 A1 B0 A0
C3 C2 FA C1 C0
FA FA FA
C4 S3 S2 S1 S0
Binary Incrementer
A3 A2 A1 A0 1
x y x y x y x y
HA HA HA HA
C S C S C S C S
C4 S3 S2 S1 S0
– Selective-complement AAB
– Selective-clear A A • B’
– Clear AAB
– Insert A (A • B) + C
– Compare AAB
– Logical shift
– Circular shift
– Arithmetic shift
• What differentiates them is the information that goes into the serial
input
– Examples:
» R2 shr R2
» R3 shl R3
• In a circular shift the serial input is the bit that is shifted out of the
other end of the register.
– Examples:
» R2 cir R2
» R3 cil R3
MPC
Mapping ROM
Micro-
store Next Microinstruction selection
Rd
Condition codes and interrupts
Control ROM
to a host computer.
Bus architecture uses common data signaling paths for multiple devices,
rather than have separate connections between each set of devices that
need to communicate.
For example, a data bus can be used for data to and from dynamic RAM,
to and from mass storage, and to and from peripheral devices, rather than
having one set of wires from the CPU for memory, another set for I/O, and
so forth.
There is often a mechanism for devices to signal when they need to use the
bus, while it is in use, and what is the nature of the use
(data/instructions/controls/etc).
Q95 What do u mean by term bus,single bus architecture, future bus and
PCI?
The bus analyzer monitors the bus traffic and decodes and displays the
data. It is essentially a logic analyzer with some additional knowledge of
the underlying bus traffic characteristics.
Flow Chart
Computer Architecture Question Bank 67
Q99 What are control and status signal of 8085?
ALE: Address Latch Enable. This signal is a pulse that become 1 when the
AD0 – AD7 lines have an address on them. It becomes 0 after that. This
signal can be used to enable a latch to save the address bits from the AD
lines.
A stack is a last in, first out (LIFO) abstract data type and data structure.
A stack can have any abstract data type as an element, but is characterized
by only two fundamental operations, the push and the pop. The push
operation adds to the top of the list, hiding any items already on the stack,
or initializing the stack if it is empty. The pop operation removes an item
from the top of the list, and returns this value to the caller. A pop either
reveals previously concealed items, or results in an empty list. A stack is a
restricted data structure, because only a small number of operations are
performed on it. The nature of the pop and push operations also means that
stack elements have a natural order. Elements are removed from the stack
in the reverse order to the order of their addition: therefore, the lower
elements are typically those that have been in the list the longest.
The stack frame at the top of the stack is for the currently executing
routine. In the most common approach the stack frame includes space
for the local variables of the routine, the return address back to the
routine's caller, and the parameter values passed into the routine. The
stack is often
accessed via a register called the stack pointer, which also serves to
indicate the current top of the stack.