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Chapter 2: Op-Amp Basic Stages

2.1 Introduction

An integrated circuit IC is a circuit where an entire circuit is constructed on a single piece of

semiconductor material. One of the commonly used types of IC is the operational amplifier.
The schematic diagram of the 741-type OP-Amp and its symbol is shown below.

Bias Network Differential Amp Gain Stage Level Shifter Output Stage

Vee

Inverting Input -
Output
Non Inverting +
Input

Vcc

Operational Amplifier is a high gain dc differential amplifier capable of performing a wide

range of functions by using external feedback. It is the most flexible linear device. By
controlling the feedback network properties, we can manipulate the overall forward transfer
function of the device and its application.

The majority of commercially available operational amplifiers employ the structure shown
below.

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V1
Buffer & Level
Diff-Amp Additional Gain Output Deriver VO
V2 Shifter

The differential amplifier is used as the input stage to provide the inverting and the non
inverting inputs and the high input resistance as well as voltage gain. The low output
resistance of the op-amp is achieved by the emitter follower output stage. The level shifter
adjusts the dc voltages so that the output voltage signal is referenced to ground. The
adjustment of dc level is required because the gain stages are direct coupled. The input and
output stages are required to match the op-amp with the external world.

2.2 Differential Amplifiers

Previously in Applied electronics I, we have discussed single stage amplifiers of one input
and one output terminal with limited gain, input resistance and output resistance. Here,
another basic transistor circuit configuration called differential amplifier is introduced,
which can give us high gain and specified input and output resistance values. It is the input
stage for most operational amplifiers and is widely used amplifier building block in analogue
integrated circuit. Unlike the other amplifiers we have discussed so far, it has two input
terminals and one output terminal, where the output signal is the difference of the two input
signals as shown in the difference amplifier block diagram below.

V2
Difference
Amplifier VO
V1

Figure 2.1: Difference amplifier block diagram

Where the output voltage V O is given by:

𝑉𝑉𝑂𝑂 = 𝐴𝐴𝑑𝑑 (𝑉𝑉1 − 𝑉𝑉2 )

There are two different modes of operation of the differential pair:

1. The differential pair with a common-mode input signal CM:

𝑉𝑉1 + 𝑉𝑉2
𝑉𝑉𝑐𝑐𝑐𝑐 =
2
2. The differential pair with a differential (mode) input signal:

𝑉𝑉𝑑𝑑 = 𝑉𝑉1 − 𝑉𝑉2

Thus, the total output voltage is given by

𝑉𝑉1 + 𝑉𝑉2
𝑉𝑉𝑂𝑂 = 𝐴𝐴𝑑𝑑 (𝑉𝑉1 − 𝑉𝑉2 ) + 𝐴𝐴𝑐𝑐 � �
2
Where 𝐴𝐴𝑑𝑑 and 𝐴𝐴𝑐𝑐 respectively are the differential gain and the common mode gain.

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The above equations shows that if V 1 = V 2 , the differential mode input signal is zero and the
common mode input signal is V cm = V 1 = V 2 .

The differential amplifier can be implemented with BJTs and FETs. We focus on differential
amplifiers implemented using BJT transistors.

2.2.1. Response for differential inputs

Differential mode: This mode of operation exists when the differential amplifier has one
source connected to each input and the two sources are out of phase with each other and of
the same amplitude.

Common mode: This exists if the sources are equal in amplitude and in phase, the two
opposing forces will balance each other, so that they cancel.

Consider the following basic BJT differential pair configuration

VCC

RC1 RC2

VC1 - +
Vout VC2

iC1 iC2

Q1 Q2

VB1 iE1 VB2

iE2

VEE

Figure 2.2: Basic BJT differential pair configuration

Following the polarity shown in figure 2.2, the ac output voltage can be expressed as:

𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 = 𝑉𝑉𝐶𝐶2 − 𝑉𝑉𝐶𝐶1

The output voltage V out is called a differential output since it combines the two ac collector
voltages into one voltage.

Common mode response

First let us consider a circuit in which the two base terminals are connected together and a
common mode voltage V cm is applied as shown in figure 2.3 below.

The voltage at the common emitters is given by KVL in one of the transistor input circuit:

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𝑉𝑉𝐸𝐸 = 𝑉𝑉𝑐𝑐𝑐𝑐 − 𝑉𝑉𝐵𝐵𝐵𝐵 (𝑜𝑜𝑜𝑜) 2.1

If the transistors Q 1 and Q 2 are identical, the current I Q splits evenly between the two
transistors and is given by:

𝐼𝐼𝑄𝑄
𝑖𝑖𝐸𝐸1 = 𝑖𝑖𝐸𝐸2 = 2.2
2
If base currents are negligible then, 𝑖𝑖𝐶𝐶1 ≅ 𝑖𝑖𝐸𝐸1 𝑎𝑎𝑎𝑎𝑎𝑎 𝑖𝑖𝐶𝐶2 ≅ 𝑖𝑖𝐸𝐸2 ,

Therefore, the collector voltages are given by:

𝐼𝐼𝑄𝑄
𝑉𝑉𝐶𝐶1 = 𝑉𝑉𝐶𝐶𝐶𝐶 − 𝑅𝑅 = 𝑉𝑉𝐶𝐶2 2.3
2 𝐶𝐶
VCC

IQ IQ
RC1 RC2 2
2
IQ IQ
VC1 = VCC − RC1 VC 2 = VCC − RC 2
2 2

Q1 Q2
+
Vcm
- IQ IQ
2 VE
2

IQ

VEE

Figure 2.3: Basic diff-amp with applied common mode voltage

From this we conclude that, for an applied common mode voltage, 𝐼𝐼𝑄𝑄 splits equally between
Q 1 and Q 2 and the difference between V C1 and V C2 is zero.

By varying V cm in figure 2.3 above by a small amount and determining the circuit response,
will not result any change in the above equations. Thus, suggesting that both the collector
current and voltages of the transistor will remain unchanged. Hence, we say the circuit does
not respond to changes in the input common mode level; or the circuit “rejects” input CM
variations.

Differential response

Let us now increase the base voltage V B1, in figure 2.2, by a small voltage V d /2 and decrease
V B2 by the same amount. I.e. let
𝑣𝑣𝑑𝑑 𝑣𝑣𝑑𝑑
𝑉𝑉𝐵𝐵1 = �2 𝑎𝑎𝑎𝑎𝑎𝑎 𝑉𝑉𝐵𝐵2 = − �2 2.4

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This show the voltages at the bases of Q 1 and Q 2 are no longer equal. Since the emitters are
common, the base to emitter voltages of Q 1 and Q 2 are not the same. We have increased V B1
and decreased V B2 , giving us V BE1 >V BE2 , as a result i C1 increases by ΔI above its quiescent
value and i C2 decreases by ΔI below its quiescent value. This is shown in figure 2.4 below.

VCC

IQ
IQ
+ ∆I RC1 RC2
− ∆I
2 2

  IQ     IQ  
VC1 = VCC −  + ∆I  RC1  VC 2 = VCC −  − ∆I  RC 2 
  2     2  

Q1 Q2
+ +
vd VBE1 - V vd
- BE 2
2 IQ IQ 2
+ ∆I − ∆I
2 VE
2

IQ

VEE

Figure 2.4: Basic differential amplifier with applied differential mode

Hence, there exists a potential difference between the two collector terminals which is given as
follows:

𝐼𝐼𝑄𝑄 𝐼𝐼𝑄𝑄
𝑉𝑉𝐶𝐶2 − 𝑉𝑉𝐶𝐶1 = �𝑉𝑉𝐶𝐶𝐶𝐶 − � − ∆𝐼𝐼� 𝑅𝑅𝐶𝐶2 � − �𝑉𝑉𝐶𝐶𝐶𝐶 − � + ∆𝐼𝐼� 𝑅𝑅𝐶𝐶1 �
2 2

= ∆𝐼𝐼𝑅𝑅𝐶𝐶2 + ∆𝐼𝐼𝑅𝑅𝐶𝐶1 , 𝑏𝑏𝑏𝑏𝑏𝑏 𝑖𝑖𝑖𝑖 𝑅𝑅𝐶𝐶1 = 𝑅𝑅𝐶𝐶2 = 𝑅𝑅𝐶𝐶

∴ 𝑉𝑉𝐶𝐶2 − 𝑉𝑉𝐶𝐶1 = 2∆𝐼𝐼𝑅𝑅𝐶𝐶 2.5

This proves that a voltage difference is created between the two collector terminals (V C2 and
V C1 ) by applying a differential mode input voltages.

2.2.2. Small signal analysis

Consider the following small signal circuit configuration.

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RC1 RC2

+ +
Ri1 V1 gm1V1 gm2V2 V2 Ri2
VB1 - - VB2
E

Figure 2.5: Small signal model of bipolar pair

Take the requirement that the input signals do not affect the bias currents of transistors Q 1
and Q 2 significantly. I.e. both transistors must exhibit approximately equal trans-
conductance. And for small differential inputs the tail node maintains constant voltage (which
results in a state called “virtual ground”).

For differential operation V B1 and V B2 represent small changes in each input and they should
satisfy V B1 = - V B2 .
Note: The emitter current source I Q is replaced with an open circuit.

To analyse the small signal operation let us take KVL around the input network and KCL at
node E.

𝑉𝑉𝐵𝐵1 − 𝑉𝑉1 = 𝑉𝑉𝐸𝐸 = 𝑉𝑉𝐵𝐵2 − 𝑉𝑉2 2.11

𝑉𝑉1 𝑉𝑉2
+ 𝑔𝑔𝑚𝑚1 𝑉𝑉1 + 𝑔𝑔𝑚𝑚2 𝑉𝑉2 + =0 2.12
𝑅𝑅𝑖𝑖1 𝑅𝑅𝑖𝑖2

Let R i1 = R i2 and g m1 = g m2 , then equation 2.12 yields:

𝑉𝑉1 = −𝑉𝑉2

Since V B1 = - V B2 , equation 2.11 will become:

2𝑉𝑉𝐵𝐵1 = 2𝑉𝑉1

This would result in:

𝑉𝑉𝐸𝐸 = 𝑉𝑉𝐵𝐵1 − 𝑉𝑉1 = 0

Thus, for small signal analysis of the circuit the emitter voltage remains constant if the two
inputs vary differentially and by a small amount.
With the assumption taken to analyse the above circuit and the result obtained, node E can be
shorted to ac ground reducing the differential pair of figure 2.5 to two half circuits, with each
half resembling common emitter stage as shown in figure 2.6 below.

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RC1 RC2

+ +
Ri1 V1 gm1V1 gm2V2 V2 Ri2
VB1 - - VB2

Figure 2.6: Simplified small signal model

With this simplified model, we can write:

𝑣𝑣𝑜𝑜𝑜𝑜𝑜𝑜 1 = −𝑔𝑔𝑚𝑚1 𝑉𝑉1 𝑅𝑅𝐶𝐶1 2.13

Substituting for V 1 = V B1 , g m1 =g m2 =g m and R C1 = R C2 = R C ,

𝑣𝑣𝑜𝑜𝑜𝑜𝑜𝑜 1 = −𝑔𝑔𝑚𝑚 𝑉𝑉𝐵𝐵1 𝑅𝑅𝐶𝐶 2.14(𝑎𝑎)

𝑣𝑣𝑜𝑜𝑜𝑜𝑜𝑜 2 = −𝑔𝑔𝑚𝑚 𝑉𝑉𝐵𝐵2 𝑅𝑅𝐶𝐶 2.14(𝑏𝑏)

Then, the differential voltage gain of the differential pair is:

𝑣𝑣𝑜𝑜𝑜𝑜𝑜𝑜 1 − 𝑣𝑣𝑜𝑜𝑜𝑜𝑜𝑜 2 −𝑔𝑔𝑚𝑚 𝑉𝑉𝐵𝐵1 𝑅𝑅𝐶𝐶 − (−𝑔𝑔𝑚𝑚 𝑉𝑉𝐵𝐵2 𝑅𝑅𝐶𝐶 )

𝐴𝐴𝑑𝑑 = =
𝑉𝑉𝐵𝐵1 − 𝑉𝑉𝐵𝐵2 𝑉𝑉𝐵𝐵1 − 𝑉𝑉𝐵𝐵2

𝐴𝐴𝑑𝑑 = −𝑔𝑔𝑚𝑚 𝑅𝑅𝐶𝐶 2.15

Common mode gain (A C )

The small signal equivalent model for the common mode signal is:

- -

RC VO1 VO2 RC
+ +

+ +
Ri1 V1 gm1V1 gm2V2 V2 Ri2
Vcm - -

Figure 2.7: Small signal pair of common mode circuit

The common mode gain A c of transistor Q 1 in the above common mode circuit is given by:

𝑉𝑉𝑂𝑂1 −𝑔𝑔𝑚𝑚1 𝑉𝑉𝑐𝑐𝑐𝑐 𝑅𝑅𝐶𝐶1

𝐴𝐴𝑐𝑐 = = , ∵ 𝑉𝑉1 = 𝑉𝑉2 = 𝑉𝑉𝑐𝑐𝑐𝑐 2.16
𝑉𝑉𝑐𝑐𝑐𝑐 𝑉𝑉𝑐𝑐𝑐𝑐

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This results to:

𝐴𝐴𝑐𝑐 = −𝑔𝑔𝑚𝑚1 𝑅𝑅𝐶𝐶1 2.17

By symmetry of the two transistors the total gain of common mode pair is zero.

RC1

+
Ri1 V1 gm1V1
Vcm -

2RE

Figure 2.8: Small signal model for the common mode circuit when Re is added

But if an emitter resistor is connected to the emitter node E of the above figure 2.8, the one sided gain
A C is simply given by:

𝑉𝑉𝑂𝑂1 −𝑔𝑔𝑚𝑚1 𝑉𝑉𝑐𝑐𝑐𝑐 𝛽𝛽𝛽𝛽𝐶𝐶1

𝐴𝐴𝑐𝑐 = =
𝑉𝑉𝑐𝑐𝑐𝑐 𝑔𝑔𝑚𝑚1 𝑉𝑉𝑐𝑐𝑐𝑐 𝑅𝑅𝑖𝑖1 + 2(1 + 𝛽𝛽)𝑅𝑅𝐸𝐸 (𝑔𝑔𝑚𝑚1 𝑉𝑉𝑐𝑐𝑐𝑐 )

−𝛽𝛽𝛽𝛽𝐶𝐶1
= 2.18
2(1 + 𝛽𝛽)𝑅𝑅𝐸𝐸 + 𝑅𝑅𝑖𝑖1

For large values of β and dividing by R i1

−𝑔𝑔𝑚𝑚 𝑅𝑅𝐶𝐶1 𝑅𝑅𝐶𝐶1

𝐴𝐴𝑐𝑐 = ≅ − , 𝑓𝑓𝑓𝑓𝑓𝑓 2𝑔𝑔𝑚𝑚 𝑅𝑅𝐸𝐸 ≫ 1 2.19
2𝑔𝑔𝑚𝑚 𝑅𝑅𝐸𝐸 + 1 2𝑅𝑅𝐸𝐸

Because the same signal is applied for Q 1 and Q 2 both V o1 and V o2 are out of phase with V cm .

2.2.3. Common mode rejection ratio (CMRR)

It is defined as the ratio between the differential gain and the common mode gain, indicates
the ability of the amplifier to accurately cancel voltages that are common to both inputs.

𝐴𝐴𝑑𝑑
𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 =
𝐴𝐴𝑐𝑐

For an ideal diff-amp A c is zero and CMRR goes to infinite.

𝐴𝐴𝑑𝑑
𝐼𝐼𝐼𝐼 𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑, 𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 = 20 log � �
𝐴𝐴𝑐𝑐

For the differential amplifier shown in figure 2.2 the one sided differential and common
mode gains are given by:

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𝑔𝑔𝑚𝑚 𝑅𝑅𝐶𝐶
𝐴𝐴𝑑𝑑 = −
2
And
−𝛽𝛽𝛽𝛽𝐶𝐶1
𝐴𝐴𝑐𝑐 =
2(1 + 𝛽𝛽)𝑅𝑅𝐸𝐸 + 𝑅𝑅𝑖𝑖1

Using these equations the CMRR can be expressed as:

𝐴𝐴𝑑𝑑 1 2(1 + 𝛽𝛽)𝑅𝑅𝐸𝐸

𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 = � �= � + 1� 2.20
𝐴𝐴𝑐𝑐 2 𝑅𝑅𝑖𝑖1

The common mode gain decreases as 𝑅𝑅𝐸𝐸 increases. Therefore, as equation 2.20 shows CMRR
increases as 𝑅𝑅𝐸𝐸 increases.

Hence, the higher the differential gain with respect to the common mode gain, the better the
performance of the diff-amp in terms of the rejection of the common mode signals.

Example 1:

Determine the differential and common mode gains of the diff-amp for the figure 2.2, with
parameters 𝑉𝑉𝐶𝐶𝐶𝐶 = 10𝑉𝑉, 𝑉𝑉𝐸𝐸𝐸𝐸 = −10𝑉𝑉, 𝐼𝐼 = 0.8𝑚𝑚𝑚𝑚, 𝑎𝑎𝑎𝑎𝑎𝑎 𝑅𝑅𝐶𝐶 = 12𝐾𝐾Ω. The transistor
parameters are: 𝛽𝛽 = 100. Assume the output resistance looking into the constant current
source is 𝑅𝑅𝑂𝑂 = 25𝐾𝐾Ω, and again take the assumption that the source resistance of each
transistor is zero.

Solution:

From equation 2.15, the differential mode gain for the one sided output is

𝑔𝑔𝑚𝑚1 𝑅𝑅𝐶𝐶1 𝛽𝛽𝐼𝐼𝑏𝑏1 𝑉𝑉𝑇𝑇

𝐴𝐴𝑑𝑑 = − , 𝑏𝑏𝑏𝑏𝑏𝑏 𝑔𝑔𝑚𝑚1 = , 𝑎𝑎𝑎𝑎𝑎𝑎 𝑉𝑉1 = 𝐼𝐼𝑏𝑏1 𝑅𝑅𝑖𝑖1 , 𝑅𝑅𝑖𝑖1 =
2 𝑉𝑉1 𝐼𝐼𝑏𝑏1

Therefore,
𝛽𝛽𝛽𝛽𝑏𝑏1 𝑅𝑅𝐶𝐶1
𝐴𝐴𝑑𝑑 = − , 𝐵𝐵𝐵𝐵𝐵𝐵 𝐼𝐼𝑐𝑐1 = 𝛽𝛽𝛽𝛽𝑏𝑏1
2𝑉𝑉𝑇𝑇

𝐼𝐼𝑐𝑐1 𝑅𝑅𝐶𝐶1 𝐼𝐼
𝐴𝐴𝑑𝑑 = − , 𝐼𝐼𝑐𝑐1 =
2𝑉𝑉𝑇𝑇 2

𝐼𝐼𝑅𝑅𝐶𝐶1
𝐴𝐴𝑑𝑑 = −
4𝑉𝑉𝑇𝑇

Substituting the values of 𝑅𝑅𝐶𝐶1 and 𝐼𝐼 and taking 𝑉𝑉𝑇𝑇 = 26𝑚𝑚𝑚𝑚, we get

0.8 ∗ 12
𝐴𝐴𝑑𝑑 = − = −92.3
4 ∗ 0.026

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From equation 2.18, the common mode gain is

−𝛽𝛽𝛽𝛽𝐶𝐶1
𝐴𝐴𝑐𝑐 =
2(1 + 𝛽𝛽)𝑅𝑅𝐸𝐸 + 𝑅𝑅𝑖𝑖1

Rewriting the above equation and using 𝑅𝑅𝐸𝐸 = 𝑅𝑅𝑂𝑂

−𝛽𝛽𝛽𝛽𝛽𝛽𝐶𝐶1
𝐴𝐴𝑐𝑐 =
2(1 + 𝛽𝛽)𝑅𝑅𝑂𝑂 + 2𝛽𝛽𝛽𝛽𝑇𝑇

−100 ∗ 0.8𝑚𝑚𝑚𝑚 ∗ 12𝐾𝐾Ω

𝐴𝐴𝑐𝑐 = = −0.237
2(1 + 100)25𝐾𝐾Ω + 2 ∗ 100 ∗ 26mV

As it is seen in the above result, the common mode gain is significantly less than the
differential-mode gain, but it is not zero because our current source is not ideal.

And the CMRR is given by

𝐴𝐴𝑑𝑑 92.3
𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 = � �= = 389
𝐴𝐴𝑐𝑐 0.237

Expressing this in decibel,

𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝑑𝑑𝑑𝑑 = 20 log10 389 = 51.8𝑑𝑑𝑑𝑑

The CMRR of diff-amp can be improved by increasing the current source output resistance.

Input and output impedances

For the differential pair configuration and its equivalent model shown in figure 2.9 below, we
can write the input impedance as follows:
𝑉𝑉1 𝑉𝑉2
= 𝑖𝑖𝑥𝑥 = −
𝑅𝑅𝑖𝑖1 𝑅𝑅𝑖𝑖2

And also we have from KVL loop between V 1 , node E and V 2 :

𝑉𝑉𝑥𝑥 = 𝑉𝑉1 − 𝑉𝑉2 , 𝑏𝑏𝑏𝑏𝑏𝑏 𝑅𝑅𝑖𝑖1 = 𝑅𝑅𝑖𝑖2

𝑉𝑉𝑥𝑥 = 2𝑅𝑅𝑖𝑖1 𝑖𝑖𝑥𝑥 ,

𝑤𝑤ℎ𝑒𝑒𝑒𝑒𝑒𝑒 𝑉𝑉𝑥𝑥 𝑖𝑖𝑖𝑖 𝑡𝑡ℎ𝑒𝑒 𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠

From this it follows that

𝑉𝑉𝑥𝑥
= 2𝑅𝑅𝑖𝑖1
𝑖𝑖𝑥𝑥

This implies that as if the two base emitter junctions appear in series. And hence, the result is
called the differential input impedance of the circuit.

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VCC

RC RC

IX RC RC
Q Q
1 2
+ +
Ri1 V1 gm1V1 gm2V2 V2 Ri2
- -
VE
IX
E
VX IX
IQ
VX

Figure 2.9: Method for calculation of differential input impedance and its equivalent model.

The output impedance for the differential mode is 2R C . But if R C is derived from an active
load, the output resistance r o of the BJT cannot be ignored rather it must be included as given
below:

𝑅𝑅𝑂𝑂 = 2(𝑟𝑟𝑜𝑜 //𝑅𝑅𝐶𝐶 )

Example 2:

The differential amplifier of figure example 2, shown below uses transistors with B=100.
Evaluate the following:

a. The input differential resistance 𝑅𝑅𝑖𝑖𝑖𝑖

b. The overall differential gain 𝑣𝑣𝑜𝑜 ⁄𝑣𝑣𝑠𝑠 (neglect the effect of r o ).
c. The worst case Common mode gain if the two collector resistances are accurate to
within ±1%.
d. The CMRR, in dB

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VCC=15V

RC= 10K RC= 10K

- +
VO
5K 5K
Q1 Q2
+ -

VS/2 VS/2
RE= 150 RE= 150
- Rid +

REE= 200K I 1mA

Figure: Example 2

Solution:

a. Each transistor is biased at an emitter current of 0.5mA. Thus,

𝑉𝑉𝑇𝑇 25𝑚𝑚𝑚𝑚
𝑟𝑟𝑒𝑒1 = 𝑟𝑟𝑒𝑒2 = = = 50Ω
𝐼𝐼𝐸𝐸 0.5𝑚𝑚𝑚𝑚

The input differential resistance can now be found as:

𝑅𝑅𝑖𝑖𝑖𝑖 = 2(𝛽𝛽 + 1)(𝑟𝑟𝑒𝑒 + 𝑅𝑅𝐸𝐸 ) = 2(101)(50 + 150)

𝑅𝑅𝑖𝑖𝑖𝑖 = 40𝑘𝑘Ω

b. The voltage gain from the signal source to the bases of Q 1 and Q 2 is:

𝑣𝑣𝑖𝑖𝑖𝑖 𝑅𝑅𝑖𝑖𝑖𝑖 40
= = = 0.8
𝑣𝑣𝑠𝑠 𝑅𝑅𝑖𝑖𝑖𝑖 + 𝑅𝑅𝑠𝑠 40 + 5 + 5

The voltage gain from the bases to the output is

𝑣𝑣𝑜𝑜 𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 𝑖𝑖𝑖𝑖 𝑡𝑡ℎ𝑒𝑒 𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐

=
𝑣𝑣𝑖𝑖𝑖𝑖 𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 𝑖𝑖𝑖𝑖 𝑡𝑡ℎ𝑒𝑒 𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒

2𝑅𝑅𝑐𝑐 2 ∗ 10𝑘𝑘
= = = 50
2(𝑟𝑟𝑒𝑒 + 𝑅𝑅𝐸𝐸 ) 2(50 + 150)

The overall differential voltage gain can now be found as

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𝑣𝑣𝑜𝑜 𝑣𝑣𝑖𝑖𝑖𝑖 𝑣𝑣𝑜𝑜

𝐴𝐴𝑑𝑑 = = = 0.8 ∗ 50 = 40
𝑣𝑣𝑠𝑠 𝑣𝑣𝑠𝑠 𝑣𝑣𝑖𝑖𝑖𝑖

c. Assuming perfect symmetry, except mismatch in the collector resistances, the

common mode gain is given by:

𝑅𝑅𝑐𝑐 ∆𝑅𝑅𝑐𝑐
𝐴𝐴𝑐𝑐 =
2𝑅𝑅𝐸𝐸𝐸𝐸 𝑅𝑅𝑐𝑐

Where ∆𝑅𝑅𝑐𝑐 = 0.02𝑅𝑅𝑐𝑐 in the worst case. Then

10
𝐴𝐴𝑐𝑐 = ∗ 0.02 = 5𝑥𝑥10−4
2 ∗ 200𝑘𝑘
d.
𝐴𝐴𝑑𝑑 40
𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 = 20 log10 = 20 log10 = 98𝑑𝑑𝑑𝑑
𝐴𝐴𝑐𝑐 5𝑥𝑥10−4

Input Offset voltage of the differential pair

Consider the basic BJT differential pair with both input grounded, as shown in figure 2.10
below.
VCC VCC

RC1 RC2 RC1 RC2

- + - +
VO 0V
iC1 iC2 iC1 iC2

Q1 Q2 Q1 Q2
+

-VOS iE1 iE2

iE1 iE2

-
I
I

(a) (b)

Figure 2.10: (a) The BJT differential pair with both input grounded, (b) Application of the
input offset voltage V OS .

As we have seen until now, if the two sides of the differential pair were perfectly matched,
the current I would split evenly in both sides and V O would be zero. But practical circuit’s
exhibit mismatches that result in a dc output voltage V OS , even with both inputs grounded.
We call V O the output dc offset voltage.

To obtain the input offset voltage V OS we divide V O by the differential gain A d

𝑉𝑉
𝑉𝑉𝑂𝑂𝑂𝑂 = 𝑂𝑂�𝐴𝐴
𝑑𝑑

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If we apply a voltage - V OS between the input terminals of the differential amplifier, then the
output voltage will be reduced to zero as shown in figure 2.10(b).

The factors which contribute to the dc offset voltage of bipolar differential amplifier are
mismatches in load resistors (R C1 and R C2 ), from junction area, β and other mismatches in Q 1
and Q 2 .

2.3. Constant Current Sources

Frequently in practice, Re is replaced by a transistor circuit. They are widely used as emitter
sources for differential amplifiers and also to bias transistors. Now let’s consider the circuit
shown below.

VCC

IC1 RC IC2 RC

VO1 VO2
IB1 IB2
Q1 Q2
+ + +
+
VBE1 - VBE 2
RS1 - RS2
IE1 IE2
VB1 VB2
IO VS2
VS1 R1
Q3
- -
D

I3 R3 R2

-VEE

Figure 2.13: Differential amplifier with constant current stage in the emitter circuit

On figure 2.13 Q 3 acts as a constant current source.

Now applying KVL to the base of Q 3 :

𝑅𝑅2
𝐼𝐼3 𝑅𝑅3 + 𝑉𝑉𝐵𝐵𝐵𝐵3 = 𝑉𝑉𝐷𝐷 + (𝑉𝑉𝐸𝐸𝐸𝐸 − 𝑉𝑉𝐷𝐷 )
𝑅𝑅1 + 𝑅𝑅2

𝑉𝑉𝐷𝐷 is the diode voltage. Hence,

1 𝑉𝑉𝐸𝐸𝐸𝐸 𝑅𝑅2 𝑉𝑉𝐷𝐷 𝑅𝑅1

𝐼𝐼𝑂𝑂 ≈ 𝐼𝐼3 = � + − 𝑉𝑉𝐵𝐵𝐵𝐵3 �
𝑅𝑅3 𝑅𝑅1 + 𝑅𝑅2 𝑅𝑅1 + 𝑅𝑅2

If the circuit parameters are chosen so that

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𝑉𝑉𝐷𝐷 𝑅𝑅1 𝑉𝑉𝐸𝐸𝐸𝐸 𝑅𝑅2

= 𝑉𝑉𝐵𝐵𝐵𝐵3 𝑡𝑡ℎ𝑒𝑒𝑒𝑒 𝐼𝐼𝑂𝑂 =
𝑅𝑅1 + 𝑅𝑅2 𝑅𝑅3 ∗ (𝑅𝑅1 + 𝑅𝑅2 )

Since this current is independent of the signal voltages, then Q 3 acts to supply the diff-amp
consisting of Q 1 and Q 2 with the constant current I O .

2.4. Current Mirror

The principle of a current mirror is that a current fed in at the input of the current mirror
circuit will produce an identical value of current in the second.
Let’s consider the following current mirror circuit.

I
VO

IC 2I C β IO=IC

Q3 Q4
IC β + IC β
 1  1
I C 1 +  VBE I C 1 + 
 β -  β

Figure 2.14: BJT current mirror

If 𝛽𝛽 is sufficiently high, so that we can neglect the base currents, the reference current I is
passed through the diode connected transistor Q 3 and thus establishes a corresponding
voltage V BE , which in turn is applied between base and emitter of Q 4 . Hence, if Q 3 is
matched with Q 4 , the collector current of Q 4 will be equal to that of Q 3 ; i.e. 𝐼𝐼𝑂𝑂 = 𝐼𝐼

However, for finite transistor𝛽𝛽, if transistors Q 3 and Q 4 are matched and have the same V BE ,
their collector currents will be equal i.e 𝐼𝐼𝑂𝑂 = 𝐼𝐼𝐶𝐶

Then, a node equation at the collector of Q 3 yields:

2𝐼𝐼𝐶𝐶 2
𝐼𝐼 = 𝐼𝐼𝐶𝐶 + �𝛽𝛽 = 𝐼𝐼𝐶𝐶 �1 + �
𝛽𝛽

Since 𝐼𝐼𝑂𝑂 = 𝐼𝐼𝐶𝐶 , the ratio between I O and the reference current I is given by:

𝐼𝐼𝑂𝑂 𝐼𝐼𝐶𝐶 1
= =
𝐼𝐼 2 2
𝐼𝐼𝐶𝐶 �1 + � �1 + �
𝛽𝛽 𝛽𝛽

Now, consider the following circuit which employs a symmetrical differential pair Q 1 and Q 2
along with a current mirror load Q 3 and Q 4 .

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VCC

Q3 Q4
vd
gm
vd 2
gm vd
2 gm +
2 Vout
Q1 Q2
VB1 VB2
-

-VEE

Figure 2.15: Differential pair with active load

The current mirror active load is a way to accomplish high gain for a single stage differential
amplifier. The NPN transistors Q 1 and Q 2 shown in figure 2.15 above make up the
differential amplifier and Q 3 and Q 4 (PNP) make up the current mirror. The current mirror
acts as the collector load and provide a high effective collector load resistance, increasing the
gain.

Darlington Connection

If we connect two transistors together as shown below then it is called Darlington pair. It
behaves like a single transistor with an effective current gain approximately equal to the
product of the current gains of the two transistors. The base emitter on voltage of the pair is
twice the base emitter on voltage of a single transistor and the saturation voltage is greater
than that of a single transistor by an amount equal to the base emitter on voltage. If a small
signal Ii is input to the base, the collector current of transistor Q1 is 𝛽𝛽1 𝐼𝐼𝑖𝑖 and the emitter
current is(𝛽𝛽 + 1)𝐼𝐼𝑖𝑖 . The latter becomes the base current of transistor Q2 and hence the
collector current of Q2 is 𝛽𝛽2 (𝛽𝛽1 + 1)𝐼𝐼𝑖𝑖 . Thus the total collector current of the Darlington pair
is

𝛽𝛽2 (𝛽𝛽1 + 1)𝐼𝐼𝑖𝑖 + 𝛽𝛽1 𝐼𝐼𝑖𝑖 ≈ 𝛽𝛽1 𝛽𝛽2 𝐼𝐼𝑖𝑖

Therefore, this circuit can be very useful in high current stages where a large gain is required.

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B Q1

Q2

Figure 2.16: Darlington circuit

2.5. Level Shifter and Buffer Circuits

In integrated circuits the use of coupling capacitors is always avoided and to offset any direct
voltage level present between say, two amplifier stages, different methods are employed. One
of these methods is to use an emitter follower that can serve as a voltage shifter as shown in
the following figures.

VCC VCC VCC

Vi Vi Vi
+
R1 R1 VZ

-
VO VO VO
R2 IO R2

(a) (b) (c)

Figure 2.14: Level shifter circuits

If the output 𝑉𝑉𝑂𝑂 is taken at the emitter then the change in levels is𝑉𝑉𝑂𝑂 − 𝑉𝑉𝑖𝑖 = −𝑉𝑉𝐵𝐵𝐵𝐵 ≈ 0.7𝑉𝑉. If
this shift is not sufficient, the output may be taken at the junction of two resistors in the
emitter leg (a). The voltage shift is then increased by the drop across R 1 . The disadvantage
𝑅𝑅2
with this arrangement is that the signal voltage suffers attenuation� �. This difficulty is
𝑅𝑅1 +𝑅𝑅2
avoided by replacing R 2 by a current source I O (b). The level shift is 𝑉𝑉𝑂𝑂 − 𝑉𝑉𝑖𝑖 = −(𝑉𝑉𝐵𝐵𝐵𝐵 + 𝐼𝐼𝑂𝑂 𝑅𝑅1 )
and there is no ac attenuation for a very high resistance current source.

An avalanche diode can also be used to translate a voltage (c). Then the shift will be
𝑉𝑉𝑂𝑂 − 𝑉𝑉𝑖𝑖 = −(𝑉𝑉𝐵𝐵𝐵𝐵 + 𝑉𝑉𝑍𝑍 ). A number of forward biased p-n diodes may also be used in place
of the zener diode.

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2.6. Output Driver Circuits

An output voltage must be capable of supplying the load current and must have a low output
resistance. A common configuration for the output stage of an op amp is the emitter follower
with complementary transistors. If the input signal V i goes positive the n-p-n transistor Q 1
acts as a source to supply current to the load R L and the p-n-p transistor Q 2 is cutoff. On the
other hand, if V i becomes negative, Q 1 is cutoff and Q 2 acts as a sink to remove current from
the load, that is to decrease I L .

+VCC

Q1
n-p-n IL
Vi VO

Q2
p-n-p RL

-VCC

Figure 2.15: Complementary class B emitter follower output stage

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