Format No ACD50

Date 01/08/2016
Sri Venkateshwara College of Engineering
INTERNAL ASSESSMENT TEST QUESTION PAPER Rev No. 01
Page 1 of 1

USN: 1 V E
CBCS SCHEME 2017
IA Test- II
Term: April-2021 to August-2021
Programme: Electronics & Communication Engineering Semester& Section: 6/B
Course Title : VLSI Design Date: 29/06/2021
Course Code: 17EC63 Time: 9.15 AM to 10.45 AM
Duration: 90 Minutes Maximum Marks: 30
Instructions: Answer THREE full questions, choosing ONE full question from each part. Use A4
sheets only.
SL.NO Kx, COx Question Marks
PART – I (20 Marks)
K3,
a) CO363.323.3
Illustrate the general arrangement of a 4 bit data path of processor 10
1 Analyse the Manchester carry chain element with relevant diagram
b) K4, CO363.3 10
OR
Build the scaling factor for i) Channel resistance ii) Maximum operating
a) K3, CO363.3 10
frequency
2 Describe the following
b) K2, CO363.3 a. Different bus architectures 10
b. Carry skip adder with relevant diagram
PART – II (10 Marks)
3 a) K2, CO363.3 Explain Manchester carry chain element with relevant diagram 10

OR
Analyse implementation of carry look ahead adder along with relevant 5
a) K4, CO363.2
4 equations
Explain 4 x 4 Barrel shifter. Write the nMOS implementation and the stick 5
b) K3, CO363.2
diagram for it.
COx- course outcome (1to5) Kx- blooms knowledge Level (K1, K2, K3, K4, K5, K6)
K1 – Remember K2 – Understand K3 – Apply K4 – Analyze K5 – Evaluate K6 – Create

CO No. Knowledge Max

COURSE OUTCOMES
XYZ.I Level Marks
C363.2 Understand the stick diagram and Illustrate the layout diagrams with the
K2, K3 20
knowledge of physical design aspects.
C363.3 Understand the FPGA based system design and Analyze the CMOS subsystems and
architectural issues with the design constraints. K4 40

TOTAL 60

CXYZ.I : C – Course; X – YEAR; Y – SEMESTER; Z – Course Order; I- Order of CO

Scrutinizer Signature