AMERICAN INTERNATIONAL

UNIVERSITY-BANGLADESH
Faculty of Engineering

Lab Cover Sheet

Determination of Threshold Voltage, Output Resistance, and process technology parameters of a

Assign./Case Title:
MOSFET.

Assign./CaseNo: 6 Date of Submission:

Course Title: Analog Electronics Lab

Course Code: Click here to enter text. Section: E

Semester: Fall 2021-22 Degree Program: BSc [EEE]

Course Teacher: NUZAT NUARY ALAM

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Group Name/No.: 1

No Name ID ROLL Signature

1 Das,Subrota Sourov(submitted) 17-35445-3      

2 SAJEDUL ISLAM RIYAN 18-36165-1      

3 MUHAMMAD ABDULLAH-AN-NAYEEM JABER 16-32083-2      

4 MD. RASHEDUL ISLAM 17-33685-1      

5 MD. FARAH AL MAHMUD 17-33502-1      

6                  

Title:
Determination of Threshold Voltage, Output Resistance, and process technology parameters of a
MOSFET.

Abstract:

The Metal-Oxide-Semiconductor Field-Effect Transistor is the most common commercial

transistor today (MOSFET). Despite the fact that the MOSFET was invented before the bipolar
transistor, it wasn't until advanced fabrication techniques and the digital revolution that it became
the most widely used transistor today. Despite its lower trans conductance than the Bipolar
Junction Transistor (BJT), the MOSFET has made important contributions to analog circuit
design in recent years, owing to the demand for mixed signal circuits driven by the integration of
many functions on a single IC. The goal of this lab is to investigate the attributes of an
enhancement kind of MOSFET that has a substantial influence on the MOSFET's operation.
Students must determine the threshold voltage, output resistance, and process technology
parameters for both p-type and n-type MOSFETs in this experiment.

Introduction:

The metal-oxide semiconductor field-effect transistor (MOSFET) and the bipolar junction
transistor are the two main types of three-terminal semiconductor devices (BJT). Despite the fact
that each of the two transistor types has its own set of characteristics and applications, the
MOSFET is by far the most extensively utilized electronic device, particularly in the design of
integrated circuits (ICs), which are complete circuits manufactured on a single silicon chip.
MOSFETs, in comparison to BJTs, may be made very compact (requiring only a little area on
the silicon IC chip) and their production process is quite easy. Furthermore, their operation
necessitates relatively little energy. Moreover, circuit designers have devised innovative
techniques to integrate digital and analog functionalities almost entirely with MOSFETs (i.e.,
with very few or no resistors). All of these characteristics have enabled the implementation of
very sophisticated, very-large-scale-integrated (VLSI) digital circuits such as memory and
microprocessors using enormous numbers of MOSFETs on a single IC chip.

Theory and Methodology:

Threshold Voltage:
The value of VGS at which a sufficient number of mobile electrons accumulate in the channel region of a
enhancement type MOSFET to form a conducting channel is called the threshold voltage and is denoted
Vt . The value of Vt is controlled during device fabrication and typically lies in the range of 0.3 V to 1.0
V.

Figure 1: Drain current ID vs gate to source voltage VGS graph of an enhancement type NMOS showing
threshold voltage Vtn
In case of enhancement type transistors the channel is formed (induced) by the applied gate voltage and
the threshold voltage is defined in the following way:

Enhancement type NMOS: Vtn > 0

Enhancement type PMOS: Vtp < 0

In the case of a depletion type transistor the channel is already physically implementedby doping the
region so that already a drain current can flow for VGS = 0V.

Depletion Mode NMOS: Vtn < 0

Depletion Mode PMOS: Vtp > 0

A MOSFET can operate in any of the three regions: cut-off, triode and saturation.

Figure 2: (a) an n-channel enhancement type MOSFET with v GS and vDS applied (b) the iD – vDS
characteristics of a device with k’n(W/L) = 1 mA/V2 showing the three operating region

For NMOS:

[Triode region]

[Saturation region without considering channel length modulation]

[Saturation region considering channel length modulation]

For PMOS:

[Triode region]
 [Saturation region without considering channel length modulation]

[Saturation region considering channel length modulation]

MOSFET Parameters:

NMOS:

Vtn = Threshold voltage for a NMOS [V]

W = Width of the transistor [μm]
L = Channel-length [μm]
λn = Channel-length modulation factor [V-1]
K’n= μnCox = Transconductance coefficient [A/V2]
Cox = Gate capacitance per unit area [F/m 2]
tox = Oxide layer thickness [μm]
εox = Permittivity of the oxide (3.9)*8.85E-14 [F/cm]

PMOS:

Vtp = Threshold voltage for a NMOS [V]

W = Width of the transistor [μm]
L = Channel-length [μm]
λp = Channel-length modulation factor [V-1]
K’p= μpCox = Transconductance coefficient [A/V2]
Cox = Gate capacitance per unit area [F/m 2]
tox = Oxide layer thickness [μm]
εox = Permittivity of the oxide (3.9)*8.85E-14 [F/cm]

Channel-length modulation factor λ can be measured as: λ = 1/V A, where VA is called the early voltage
and it is a process technology parameter normally given in the datasheet.
 Figure 3: Calculation of λ from iD – vDS characteristics of an NMOS
Output Resistance:

Due to channel length modulation, the MOSFET has a finite output resistance in saturation region. The
output resistance of a MOSFET in saturation region is given by:

Where, ID is the drain current without considering channel length modulation and is given by:

Apparatus: Using Multisim as the simulation software.

(1) Multimeter
(2) NMOS
(3) PMOS
(4) Connecting wires
(5) Trainer Board
(6) 1kΩ resistor

Experimental Procedure:

1. Connected the circuits as shown in Fig. 1 and Fig. 2.

2. Placed an ammeter in Box 1. Slowly increased the voltage at V CC until we saw current start to
flow. This is the point where the transistor had transitioned from cutoff to saturation region.
Estimate Vtp.
3. Added a 1kΩ resistor in series with the ammeter. Use V CC = 5V. Measured V DS∧I D of the
transistor. Used the saturation current equation to determine K p = K’p(W/L).
4. Repeated step 1 and 2 for NMOS as in fig. 2 to find V tn and Kn.
5. Connect the circuit as shown in fig. 5(a) for PMOS and fig. 5(b) for NMOS.

(a) (b)

Figure 5: Circuit for drawing i D – vDS curve for (a) PMOS and (b) NMOS

6. Kept VGS fixed at 5 V. Now vary VDS from 0-16 volts and measured corresponding ID. Filled up
table 1.
7. Ploted the iD – vDS curve and find λ as shown in fig. 3 for both PMOS and NMOS.
8. Calculated output resistance using:
 Table 1: Data to plot iD – vDS curve

SL. VDS ID

1 0 0 0
2 2 4.30 0.22
3 4 6.47 0.07
4 6 8.66 0.05
5 8 10.92 0.04
6 10 12.15 0.03
7 12 14.32 0.03
8 14 16.52 0.02
9 16 18.70 0.02
Simulation and Measurement:
Discussion:

We summarize the experiment and analyze it with my group members as a whole. We build the circuit,
then apply a sufficient quantity of VGS to find the threshold voltage. There might be some error in the
experimental simulation. There was also some other problem which was faced by us while doing this
experiment which was solved with the help of our course teacher. So exact value cannot be calculated.
Because of channel length modulation, the MOSFET has a limited resistance in the saturation zone.

Question/Answer:

1. Explain Channel length modulation and its effect on MOSFET operation.

Ans:

The resistance of the channel is inversely proportional to its width-to-length ratio; reducing the
length leads to decreased resistance and hence higher current flow. Thus, channel-length
modulation means that the saturation-region drain current will increase slightly as the drain-to-
source voltage increases.

Channel length modulation is an effect in field effect transistors, a shortening of the length of the
inverted channel region with increase in drain bias for large drain biases. The result of Channel
length modulation is an increase in current with drain bias and a reduction of output resistance.
 2. Discuss MOSFET resistance in triode and saturation regions.

Ans:

In the saturation or linear region, the transistor will be biased so that the maximum amount of
gate voltage is applied to the device which results in the channel resistance RDS (on being as
small as possible with maximum drain current flowing through the MOSFET switch.

References:

1. Adel S. Sedra, and Kenneth C. Smith, “Microelectronic Circuits,”

2. Integrated Electronics: Analog and Digital Circuits and Systems by Jacob Millman,
Christos
3. J. Keown, ORCAD PSpice and Circuit Analysis, Prentice Hall Press (2001).