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Asymmetrical IGBT design for three-level NPC1 converter in a bi- directional

power conversion system

Conference Paper · November 2020

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 PCIM Asia 2020, 16 – 18 November 2020, Shanghai, China

Asymmetrical IGBT design for three-level NPC1 converter in a bi-

directional power conversion system
Heng Wang, Jia Zhao, Yong Yang
Infineon Integrated Circuit (Beijing) Co., Ltd., Beijing, China, heng.wang@infineon.com

Abstract

The neutral-point-clamped topology is becoming
popular in field applications, such as medium
voltage drives, UPS, solar inverter etc. However,
the power loss distribution in such a topology is
concentrated only on some chips. This paper
introduces a novel IGBT module design, which has
an optimized silicon chip area for achieving the
best cost-performance balance in a bi-directional
converter. The proposed IGBT module adopts a
new low-cost package of the latest generation
IGBT chips. A demonstration prototype has been
designed to evaluate the module’s performance.
Laboratory test evaluations include the stray
inductance of four commutation loops, IGBT/diode
switching behavior, and thermal performance.
Based on the measured results, a simulation
model has been built to obtain accurate losses and
junction temperature. The simulated junction
temperature value is used to assess the utilization
of the chip area.
1. Basics of NPC1 topology
The three-level inverter was originally developed
for applications with high DC bus voltage, which
exceeds the blocking capability of the device.
Nowadays, three-level inverters are often used in
applications requiring high efficiency, such as solar
inverters and UPS. Compared with a two-level
inverter, the three-level inverter shows many
benefits [1]:
a) Reduction of losses and improvement of
system efficiency
b) Higher equivalent switching frequency and
smaller output filters
c) Reduced distortion of output voltage or output
current
d) Improved EMC performance
e) Use of low-voltage device to replace high-
voltage device (reduces system cost)
Neutral-point-clamped topology consists of two
diodes and four IGBTs, as Fig. 1 shows. The
central point of the D5/D6 operates as a reference
or neutral point. The typical power loss distribution
is strongly related to its operation mode. For
example in a pure inverter mode, T1/T4 have the
most switching losses and conduction losses.
T2/T3 only have conduction losses, D5/D6 have
switching losses and few conduction losses, and
D1/D2/D3/D4 have no losses, as no current
passes through it. The power loss distribution of
other operating modes is shown in Fig. 1.
The loss calculation of NPC1 is based on a full
current, 400 A configuration, which means the
T1/T2/T3/T4 are using 950 V/400 A IGBT chips

Fig. 1. Typical distribution of power losses in inverter mode, reactive mode, and rectifier mode.

ISBN 978-3-8007-5387-1 46 © VDE VERLAG GMBH · Berlin · Offenbach

 PCIM Asia 2020, 16 – 18 November 2020, Shanghai, China
and D1/D2/D3/D4/D5/D6 are using 950 V/400 A
freewheeling diode chips. The maximum IGBT
loss occurs in inverter mode, while the maximum
diode loss is in rectifier mode, both of which are
outer switches. For the other switches, their power
loss distribution is strongly affected by chip
characteristics and working conditions. A
benchmark is done with the maximum loss as
100%; thus the proportion of the power loss is
calculated [2]~[3].
2. The minimum chip area for NPC1
topology
Based on former loss calculations, the power
proportion between each chip can be obtained. As
there is an approximate linear connection from a
power loss to the chip area, the draft minimum chip
area can be calculated according to a power loss
proportion of each switch, as shown in Fig. 2.
a) Inverter mode b) Reactive mode c) Rectifier mode
Fig. 2. The minimum required chip area for
each operation mode
On the other hand, the available chips have only a
few current ratings for the module design. For
example, the latest 950 V/S7 IGBT uses only 100
A and 200 A chips, and the corresponding
freewheeling diode 100 A chips. The new
proposed module has to take into account the
nearest current values. Another adjustable factor
is thermal resistance (Rth), which is defined by the
chip area and layout position. The Rth can
influence the junction temperature, which is the
most important indicator of the safe operating of
chips. Finally, a novel IGBT for NPC1 is proposed
with 400 A IGBTs for T1/T4, 400 A diodes for
D1/D4, 300 A IGBT chips for T2/T3, and 300 A
diode chips for D2/D3/D5/D6 to balance the three
above-mentioned application requirements. The
target is to make more chips operate near the
maximum allowed temperature, depending on the
different conditions [4]~[5].
ISBN 978-3-8007-5387-1
2. The prototype design
2.1. The proposed IGBT module design
The new IGBT module chooses a new low-cost
package, which is referred to as Easy3B. It is the
ideal platform for extending the current rating
without changing significantly the mechanical
outline. Easy3B has a flexible pin-grid system like
other EASY family members, which enables a
customized pinout.
It also selects the latest 950 V, fast-switching IGBT
chips covering a wide range of DC-link voltages
from 500 V to 1300 V, suitable for 380 V, 480 V,
and 690 V AC grid-connected equipment6].
Fig. 3(a) is a vertical view of the Easy 3B module.
Its footprint is 110 mm x 62 mm with two separated
direct bonded copper (DBC) units supporting
solder or press-fit pins. This package allows the
(a) Easy 3B Module vertical view
(b) Power module pinout sketch map
Fig3. New IGBT module design for
NPC1 solution
broadest power module portfolio at 12 mm height
without baseplate. Fig. 3(b) is a module pinout
sketch map. The top and bottom chips are
positioned symmetrically, and the DC+/DC-
/neutral terminal is located only on one side of the
module, so the inverter DC-link design is much
easier. The output terminal is placed at the other
side of the module opposite the DC terminals,
which is connected to the inverter output busbar.
47 © VDE VERLAG GMBH · Berlin · Offenbach
 PCIM Asia 2020, 16 – 18 November 2020, Shanghai, China
2.2. The NPC1 power stack design
A prototype was designed to verify the switching of
the module and the thermal performance of the
new IGBT module under air-cooling conditions. In
the DC link, screwed and soldered film capacitors
are both used. The soldered capacitor is placed
very near the module to absorb ripple current, and
thus reduce VCE peak voltage during switching
turn-on and turn-off. Therefore, suitable ripple
current values for the film capacitors need to be
considered. The screwed capacitor is used to
stabilize the DC-voltage level during the module
switch. Power resistors packaged by SMD, which
are located on the PCB, are connected to DC+ and
DC- terminals to discharge the energy after the
system has stopped.
In the gate-driver stage, a galvanic driver IC is
selected to meet the system isolation
requirements. A desaturation function is used to
monitor the module’s short-circuit errors. And an
active clamping circuit and special clamping circuit
are added between the module collector and gate
terminal to reduce the VCE peak voltage level
during switching turn-off. The negative
temperature coefficient (NTC) resistor is
connected to the control circuit in the galvanic
isolation circuit to monitor the module’s DCB
temperature.
Fig. 4. Schematic and PCB design of the
prototype of NPC1 power stack
3. Experimental verification
3.1 Stray inductance
There are four commutation loops in an NPC1
topology. The stray inductance is not the same in
each loop due to the different chip positions. The
ISBN 978-3-8007-5387-1
stray inductance can be calculated by the double
pulse test. Fig. 5 shows the double pulse test
setup, in which an air-coil inductance acts as a
simulated load. The collector current is tested by a
Rogowski coil, and the collector voltage is tested
by a high-voltage differential probe. Fig. 5 shows a
typical switching waveform during turn-on. The
collector-emitter (CE) voltage drop ΔV, and current
slope di/dt can be measured by oscilloscope, then
the stray inductance (Ls) can be calculated
according to formula (1):
Ls=ΔV/ (di/dt) (1)
Based on the method illustrated above, the stray
inductance can be calculated for four commutation
loops in the NPC1 topology, named Ls1, Ls2, Ls3,
and Ls4 respectively, as shown in Fig. 6.
During an IGBT turn-off transient, the di/dt will
induce a voltage across the stray inductance. The
induced voltage overlap on the bus voltage will
cause a voltage spike at the collector of the IGBT.
If the voltage is too high, the IGBT may be
destroyed. The large stray inductance will result in
higher voltage overshoot. Hence, the turn-off
transient must be carefully evaluated to ensure
safe operation [7]~[8].
Fig. 5. Double pulse test setup and principle
measurement for stray inductance
Fig. 6. Measured stray inductance on each
commutation loop
48 © VDE VERLAG GMBH · Berlin · Offenbach
 PCIM Asia 2020, 16 – 18 November 2020, Shanghai, China
3.2 Switching
The switching waveforms of the short loop and the
long loop are shown in Fig. 7. There is an obvious
difference in the VCE spike of the IGBT between the
short loop and the long loop. The maximum VCE of
IGBT T1 is 824 V, while the VCE of T4 in the long
loop is up to 939 V, which is 115 V higher than the
short loop IGBT T1.
824V
a) Short loop
939V
b) Long loop
Fig. 7. The switching waveforms of
1200V/300A in different communication loop
As illustrated in Fig.7, the voltage overshoot across
IGBT in the long loop exceeds 900 V at nominal
current. Therefore, it is necessary to suppress the
collector-emitter voltage spike in case an
overvoltage surge or short circuit occurs. One way
of protecting the IGBT from high-voltage spikes is
via active clamping. Voltage spikes can be
reduced by adopting an active clamping circuit,
however, turn-off losses will increase. After
measuring switching losses at different currents, it
was found that such increments occur only in the
higher current area, and that the losses in the low
current area rarely change.
3.3 Thermal performance
ISBN 978-3-8007-5387-1
Normally, junction temperature is calculated by
power loss and thermal resistance:
Tj=Ploss × (Rthjc+Rthch+Rthha) +Ta (1)
Ploss: power loss of the chip
Rthjc: thermal resistance from junction to case
Rthch: thermal resistance from case to heat sink
Rthha: thermal resistance of a heat sink
Ta: ambient temperature
The Rthjc and Rthch values can be read from the
datasheet provided by the manufacturers, and
Rthha can be measured by a thermocouple or
infrared radiometer. Since Rthjh will differ
depending on the heatsink design, we should not
simply add Rthjh and Rthha. The best solution is to
measure the Rthja directly in the actual design.
First, the chips are calibrated by a small current
(here using 20 mA) to see the relationship between
junction temperature and voltage drop, which is
exactly linear with a negative temperature
coefficient. The curve of both IGBT and diode are
shown in Fig. 9.
The thermal test setup includes a DC source for
heating, a fast auxiliary switch, and a cooling
system. First, the DC source heats the power
module to thermal equilibrium with a stable Tj, then
the fast switch cuts off the current rapidly. The data
logger records the voltage drop with high sampling
rate in microseconds along with an auxiliary 20 mA
Fig. 8. Experimental setup and measurements
for transient thermal resistance calculation
from junction to ambient (Zthja)
49 © VDE VERLAG GMBH · Berlin · Offenbach
 PCIM Asia 2020, 16 – 18 November 2020, Shanghai, China
constant current source. Finally, the Tj can be
calculated from the linear coefficient, which is
measured previously.
The measured Tj can be used to calculate the
transient thermal resistance (Zth), as shown in Fig.
9. In this way, a more accurate thermal resistance
from junction to ambient can be obtained, which
will help to build a more accurate simulation model
[9]~[10].
4 Simulation
From the introduced measurements, an accurate
new device model can be built in PLECS for
simulation. The simulation is based on field-
application demands from a power conversion
system for energy storage systems. It is a 125 kW
converter working at 1200 VDC maximum voltage
and connected to a grid with line voltage 480 V
AC/50 Hz. The IGBT is required to switch with 16
kHz under forced air cooling; the maximum
ambient temperature is 40 ℃.
4.1 Power losses and junction temperature
Fig. 10. Distribution of power losses of the proposed IGBT module
Fig. 11. Junction temperature among chips of the proposed IGBT module
ISBN 978-3-8007-5387-1
The simulation analyzes three operation modes:
inverter mode, reactive mode, and rectifier mode
to check the proposed IGBT performance.
In the simulation result, illustrated in Fig.10 and
Fig.11, the maximum junction temperatures are at
the same level at around 140℃ compared to the
switches in different operation modes. Another
indicator is to check the second and third hottest
temperatures to see whether the remaining
switches are fully used or not. Thanks to the
tailored, asymmetrical chip area, the Tj of T1/T4
and T2/T3 is approximately 127 ℃ in inverter
mode; the Tj of T2/T3 is 139.5℃ in reactive mode,
and the Tj of D1/D4 is 134℃, and of D2/D3/D5/D6
the Tj is around 120℃ in rectifier mode. Thus, the
new proposed module improves the junction
temperature distribution.
5 Conclusion
A novel IGBT module featured on a tailored chip
area was designed and verified for NPC1 in bi-
directional power conversion systems, which
meets several different application requirements,
and saves costs owing to the reduced silicon area.
The stray inductance of four commutation loops
50 © VDE VERLAG GMBH · Berlin · Offenbach
 PCIM Asia 2020, 16 – 18 November 2020, Shanghai, China
are given and compared in terms of switching.
Based on double pulse test data, an accurate
simulation model was established. The simulation
results show more similar junction temperatures
among the switches in the proposed module under
different conditions. The asymmetrical design has
proved to be beneficial for NPC1 topology in a bi-
directional power system.
References
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ISBN 978-3-8007-5387-1
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51 © VDE VERLAG GMBH · Berlin · Offenbach