Dell Vostro 1320 - Compal La-4232p Kal80 - Rev 1.0sec

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A B C D E

DELL Vostro 1320


COMPAL LA-4232P - KAL80
1 1

Half Penny Bridge 13.3


2 Compal Confidential 2

Schematic Document
Cantiga + ICH9
2009 / 06 / 01 Rev:1.0(A00)
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 1 of 48
A B C D E hexainf@hotmail.com
A B C D E

DELL Vostro 1320 Half Penny Bridge 13.3


COMPAL LA-4232P
ZZZ1

Thermal Sensor Penryn -4MB (Socket P)


PCB
1
ADT7421ARMZ uFCPGA-478 CPU 1

CRT +CPU_CORE CK505 SM IC -72


+3VS P.4
+CRT_VCC P.16 +VCCP Clock Generator
P.4,5,6
+1.5VS CS9LPRS387BKLFT
+1.05VS_CK505
LVDS Panel Interface Fan conn
+LCDVDD +5VS P.4 H_A#(3..35) +3VS_CK505 P.15
+3VS FSB
B+ P.16 H_D#(0..63) 800/1066 MHz 1.05V

nVidia DDR2 667/800MHz 1.8V DDR2-SO-DIMM X2


NB9M-GS
Intel Cantiga MCH BANK 0, 1, 2, 3
+1.8V +0.9VS P.13,14

+3VS_DAC_CRT 1329pin BGA


+1.8VS +3VS_DAC_BG Dual Channel
+VGA_CORE +1.05VS_DPLLA
VRAM x 2 +1.1V_GFX_PCIE
+1.05VS_DPLLB
+VCCP USB conn x 4
+1.8VS +3VS +1.8V_TXLVDS P.7,8,9,10,11,12 +5VALW
P.35 P.31,32,33,34 P.29
2 2

DMI X4 C-Link FingerPrinter


+3VS P.29

Felica Conn
USB2.0 +5VS P.29
Intel ICH9-M
Azalia
+RTCVCC 676pin BGA BT Conn
+1.5VS +3VS P.29
SATA 0
+VCCP
PCI-E BUS SATA 1
+3VALW
P.17,18,19,20 Camera
+5VS +3VS P.29

10/100/1000 LAN Mini-Card-1 CardBus Controller Express Card Express Card


REALTEK (WLAN) O2MICRO OZ888 +1.5VS +3VS +1.5VS P.26
+1.8VS_CB
+1.5VS +3VS P.26
RTL8111DL +3VS
P.23 +3VS_PHY
P.30
3
+LAN_IO P.21 Mini-Card-1 3

+1.5VS +3VS P.23

TPM
1394 Media Card LPC
+3VS_CR SLB 9635
+3VS P.28
RJ45/11 CONN LPC BUS Digital Mic
P.24
LPC
Mini-Card-2 Audio CODEC
(WLAN) 92HD81 Audio Jack
+3VS
+1.5VS +5VS P.24 P.24
+3VS
P.23 ENE KB926
+3VALW
+EC_AVCC P.27
SATA HDD Connector
+5VS P.22
Touch Pad CONN. Int.KBD BIOS(System/EC)
Power On/Off CKT. +5VS +3VALW
P.28 P.28 P.27
P.28 CDROM Conn.
4
+5VS P.22 4

DC/DC Interface CKT.


+5VS P.36

Security Classification Compal Secret Data Compal Electronics, Inc.


2007/1/15 2008/1/15 Title
Power Circuit DC/DC RTC CKT. Issued Date Deciphered Date
SCHEMATIC, M/B LA-4232P
+RTCVCC P.39 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P.36~P.45 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 2 of 48
A B C D E
A

O MEANS ON X MEANS OFF Symbol Note :


Voltage Rails
: means Digital Ground

+5VS
+3VS : means Analog Ground
+1.5VS
power @ : means just reserve , no build
plane +0.9V
+VCCP
CONN@: connect
VGA@: discrete component
+5VALW +1.8V +CPU_CORE
UMA@: uma component
+B
TPM@: TPM compoent
+3VALW +VGA_CORE
+1.8VS
State +1.1VS
+0.9VGA

PCI EXPRESS DESTINATION SATA DESTINATION

Lane 1 NA Lane 0 HDD


S0
O O O O Lane 2 GLAN RTL8111DL Lane 1 ODD
S1
O O O O Lane 3 MINI CARD-2 WLAN Lane 4 NA
S3
O O O X Lane 4 EXPRESS CARD Lane 5 NA
S5 S4/AC
O O X X Lane 5 CARD READER OZ888
S5 S4/ Battery only
O X X X Lane 6 NA
S5 S4/AC & Battery
1
don't exist X X X X SMBUS Control Table
1

THERMAL
SERIAL SENSOR
SOURCE INVERTER BATT EEPROM (CPU) SODIMM CLK CHIP MINI CARD LCD

USB PORT# DESTINATION


SMB_EC_CK1
SMB_EC_DA1
KB926 X V V X X X X X
0 JUSBP1
SMB_EC_CK2
SMB_EC_DA2
KB926 X X X V X X X X
1 CAMERA
V V
SMB_CK_CLK1

2 JUSBP3(SINGLE)
SMB_CK_DAT1 ICH9 X X X X X X
V
LCD_CLK
3 Felica LCD_DAT Cantiga
X X X X X X X
4 Blue Tooth
ICH9-M
5 Finger Printer
I2C / SMBUS ADDRESSING
6 JMINI2-WLAN
DEVICE HEX ADDRESS
7 Express card DDR SO-DIMM 0 A0 10100000
DDR SO-DIMM 1 A4 10100100
8 JUSBP3(DUEL TOP) CLOCK GENERATOR (EXT.) D2 11010010

9 JUSBP3(DUEL BOTTOM)

10 NA

11 NA
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Date: Saturday, June 06, 2009 Sheet 3 of hexainf@hotmail.com
48
5 4 3 2 1

+VCCP

XDP_TDI R5 1 2 54.9_0402_1%

XDP_TMS R4 1 2 54.9_0402_1%
D D

XDP_TRST# R11 1 2 54.9_0402_1%

XDP_TCK R35 1 2 54.9_0402_1%

CONN@ This shall place near CPU


7 H_A#[3..16]
JCPU1A
H_A#3 J4 H1 H_ADS#
A[3]# ADS# H_ADS# 7

ADDR GROUP_0
H_A#4 L5 E2 H_BNR#
A[4]# BNR# H_BNR# 7
H_A#5 L4 G5 H_BPRI#
A[5]# BPRI# H_BPRI# 7
H_A#6 K5
H_A#7 A[6]# H_DEFER#
M3 A[7]# DEFER# H5 H_DEFER# 7
H_A#8 N2 F21 H_DRDY#
A[8]# DRDY# H_DRDY# 7
H_A#9 J1 E1 H_DBSY#
A[9]# DBSY# H_DBSY# 7
H_A#10 N3
H_A#11 A[10]# H_BR0#
P5 A[11]# BR0# F1 H_BR0# 7
H_A#12 P2 A[12]#

CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR# H_INIT#
P4 A[14]# INIT# B3 H_INIT# 18
H_A#15 P1
H_A#16 A[15]# H_LOCK#
R1 A[16]# LOCK# H4 H_LOCK# 7
H_ADSTB#0 M1
7 H_ADSTB#0 ADSTB[0]#
C1 H_RESET#
RESET# H_RESET# 7
H_REQ#0 K3 F3 H_RS#0
7 H_REQ#0 REQ[0]# RS[0]# H_RS#0 7
H_REQ#1 H2 F4 H_RS#1
7 H_REQ#1 REQ[1]# RS[1]# H_RS#1 7
H_REQ#2 K2 G3 H_RS#2
7 H_REQ#2 REQ[2]# RS[2]# H_RS#2 7
H_REQ#3 J3 G2 H_TRDY#
7 H_REQ#3 REQ[3]# TRDY# H_TRDY# 7
H_REQ#4 L1
7 H_REQ#4 REQ[4]#
G6 H_HIT#
7 H_A#[17..35] HIT# H_HIT# 7
H_A#17 Y2 E4 H_HITM#
C A[17]# HITM# H_HITM# 7 C
H_A#18 U5
H_A#19 A[18]#
R3 A[19]# BPM[0]# AD4
ADDR GROUP_1

H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]# +3VS
U4 AD1
H_A#22 Y5
A[21]#
A[22]#
BPM[2]#
BPM[3]# AC4 Thermal Sensor EMC1402-1-ACZL-TR
XDP/ITP SIGNALS

H_A#23 U1 AC2
H_A#24 A[23]# PRDY#
R4 A[24]# PREQ# AC1

0.1U_0402_16V
H_A#25 T5 AC5 XDP_TCK 1
H_A#26 A[25]# TCK XDP_TDI
T3 A[26]# TDI AA6
H_A#27 W2 AB3 XDP_TDO C13
A[27]# TDO T84
H_A#28 W5 AB5 XDP_TMS
H_A#29 A[28]# TMS XDP_TRST# 2
Y4 A[29]# TRST# AB6
H_A#30 U2 C20 XDP_DBRESET# U2
A[30]# DBR# XDP_DBRESET# 19
H_A#31 V4 1 8 EC_SMB_CK2 EC_SMB_CK2 16,27,31
H_A#32 A[31]# VDD SCLK
W3 A[32]#
H_A#33 AA4 THERMAL H_THERMDA 2 7 EC_SMB_DA2
A[33]# D+ SDATA EC_SMB_DA2 16,27,31
H_A#34 AB2 H_PROCHOT# R146 2 1 68_0402_1% +VCCP C5
H_A#35 A[34]# H_THERMDC
AA3 A[35]# PROCHOT# D21 1 2 3 D- ALERT# 6
H_ADSTB#1 V1 A24 H_THERMDA_R R57 1 2 100_0402_5% H_THERMDA 2200P_0402_50V7K
7 H_ADSTB#1 ADSTB[1]# THERMDA
B25 H_THERMDC_R R53 1 2 100_0402_5% H_THERMDC L_THERM# 4 5
H_A20M# THERMDC THERM# GND
18 H_A20M# A6 A20M#
ICH

H_FERR# A5 C7 H_THERMTRIP# R16


18 H_FERR# FERR# THERMTRIP# H_THERMTRIP# 7,18
H_IGNNE# C4 +3VS 1 2 EMC1402-2-ACZL-TR MSOP 8P
18 H_IGNNE# IGNNE#
H_THERMDA, H_THERMDC routing together, 10K_0402_5%
18 H_STPCLK#
H_STPCLK# D5 STPCLK#
Address:100_11000
18 H_INTR
H_INTR C6 H CLK Trace width / Spacing = 10 / 10 mil
H_NMI LINT0 CLK_CPU_BCLK
18 H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK 15
H_SMI# A3 A21 CLK_CPU_BCLK#
18 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 15
C76
M4
N5
RSVD[01] FAN Control circuit 10U_1206_16V4Z~N
2 1
RSVD[02] +5VS
T2 RSVD[03]
B C88 B
V3 RSVD[04]
RESERVED

B2 1000P_0402_50V7K~N 1 2
RSVD[05] C77 10U_1206_16V4Z~N
D2 RSVD[06] 2 1
D22 RSVD[07]
D3 U3
RSVD[08]
F6 RSVD[09] 1 VEN GND 8
2 VIN GND 7
FAN1_POWER 3 6
EN_DFAN1 VO GND
27 EN_DFAN1 4 VSET GND 5

Penryn +3VS RT9027BPS SO 8P

1
JFAN1
R61
40mil
1 1
+VCCP 10K_0402_5% 2 2
3 3

2
27 FAN_SPEED1 4 GND
1

FAN_SPEED1
2 5 GND
R17
56_0402_5% C94 ACES_85205-03001
0.01U_0402_16V7K conn@
1
2 2

FAN1
B

2
E

H_PROCHOT# 3 1 OCP# D4
OCP# 19
C

@ Q2 PJSOT24C_SOT23-3
MMBT3904_SOT23 @

1
+VCCP
A A
2

R18
56_0402_5%
1

H_IERR# Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 4 of 48
5 4 3 2 1
5 4 3 2 1

+CPU_CORE +CPU_CORE
7 H_D#[0..15] CONN@ CONN@
H_D#[32..47] 7
JCPU1B JCPU1C
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 D[1]# D[33]# AB24 A9 VCC[002] VCC[069] AB7
H_D#2 E26 V24 H_D#34 A10 AC7
D[2]# D[34]# VCC[003] VCC[070]

DATA GRP 0
H_D#3 G22 V26 H_D#35 A12 AC9

DATA GRP 2
D H_D#4 D[3]# D[35]# H_D#36 VCC[004] VCC[071] D
F23 D[4]# D[36]# V23 A13 VCC[005] VCC[072] AC12
H_D#5 G25 T22 H_D#37 A15 AC13
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
E25 D[6]# D[38]# U25 A17 VCC[007] VCC[074] AC15
H_D#7 E23 U23 H_D#39 A18 AC17
H_D#8 D[7]# D[39]# H_D#40 VCC[008] VCC[075]
K24 D[8]# D[40]# Y25 A20 VCC[009] VCC[076] AC18
H_D#9 G24 W22 H_D#41 B7 AD7
H_D#10 D[9]# D[41]# H_D#42 VCC[010] VCC[077]
J24 D[10]# D[42]# Y23 B9 VCC[011] VCC[078] AD9
H_D#11 J23 W24 H_D#43 B10 AD10
H_D#12 D[11]# D[43]# H_D#44 VCC[012] VCC[079]
H22 D[12]# D[44]# W25 B12 VCC[013] VCC[080] AD12
H_D#13 F26 AA23 H_D#45 B14 AD14
H_D#14 D[13]# D[45]# H_D#46 VCC[014] VCC[081]
K22 D[14]# D[46]# AA24 B15 VCC[015] VCC[082] AD15
H_D#15 H23 AB25 H_D#47 B17 AD17
H_DSTBN#0 D[15]# D[47]# H_DSTBN#2 VCC[016] VCC[083]
7 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 7 B18 VCC[017] VCC[084] AD18
H_DSTBP#0 H26 AA26 H_DSTBP#2 B20 AE9
7 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 7 VCC[018] VCC[085]
H_DINV#0 H25 U22 H_DINV#2 C9 AE10
7 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 7 VCC[019] VCC[086]
7 H_D#[16..31] H_D#[48..63] 7 C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
H_D#16 N22 AE24 H_D#48 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 D[17]# D[49]# AD24 C15 VCC[023] VCC[090] AE17
H_D#18 P26 AA21 H_D#50 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 D[19]# D[51]# AB22 C18 VCC[025] VCC[092] AE20
H_D#20 L23 AB21 H_D#52 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D10 AF10

DATA GRP 3
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
L22 D[22]# D[54]# AD20 D12 VCC[028] VCC[095] AF12
H_D#23 M23 AE22 H_D#55 D14 AF14
H_D#24 D[23]# D[55]# H_D#56 VCC[029] VCC[096]
P25 D[24]# D[56]# AF23 D15 VCC[030] VCC[097] AF15
H_D#25 P23 AC25 H_D#57 D17 AF17
H_D#26 D[25]# D[57]# H_D#58 VCC[031] VCC[098]
P22 D[26]# D[58]# AE21 D18 VCC[032] VCC[099] AF18
H_D#27 T24 AD21 H_D#59 E7 AF20 +VCCP
H_D#28 D[27]# D[59]# H_D#60 VCC[033] VCC[100]
R24 D[28]# D[60]# AC22 E9 VCC[034]
H_D#29 L25 AD23 H_D#61 E10 G21
H_D#30 D[29]# D[61]# H_D#62 VCC[035] VCCP[01]
T25 D[30]# D[62]# AF22 E12 VCC[036] VCCP[02] V6
C H_D#31 H_D#63 C
N25 D[31]# D[63]# AC23 E13 VCC[037] VCCP[03] J6
H_DSTBN#1 L26 AE25 H_DSTBN#3 E15 K6 1
7 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 7 VCC[038] VCCP[04]

220U_D2_4VY_R15M
H_DSTBP#1 M26 AF24 H_DSTBP#3 E17 M6
7 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 7 VCC[039] VCCP[05] +
H_DINV#1 N24 AC20 H_DINV#3 E18 J21
7 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 7 VCC[040] VCCP[06]

C10
E20 VCC[041] VCCP[07] K21
+V_CPU_GTLREF AD26 R26 COMP0 F7 M21
TEST1 GTLREF COMP[0] COMP1 VCC[042] VCCP[08] 2
T50 C23 TEST1 MISC COMP[1] U26 F9 VCC[043] VCCP[09] N21
TEST2 D25 AA1 COMP2 F10 N6 0814 Change to 220uF
T23 TEST2 COMP[2] VCC[044] VCCP[10]
TEST3 C24 Y1 COMP3 F12 R21
T2 TEST3 COMP[3] VCC[045] VCCP[11]
TEST4 AF26 F14 R6 0819 Change to C_D2E
T3 TEST4 VCC[046] VCCP[12]
TEST5 AF1 E5 H_DPRSTP# R23 R24 R25 R26 F15 T21
T4 TEST5 DPRSTP# H_DPRSTP# 7,18,44 VCC[047] VCCP[13]

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%
TEST6 A26 B5 H_DPSLP# F17 T6
T5 TEST6 DPSLP# H_DPSLP# 18 VCC[048] VCCP[14]

1
TEST7 C3 D24 H_DPWR# F18 V21
T6 TEST7 DPWR# H_DPWR# 7 VCC[049] VCCP[15]
CPU_BSEL0 B22 D6 H_PWRGOOD F20 W21
15 CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD 18 VCC[050] VCCP[16]
CPU_BSEL1 B23 D7 H_CPUSLP# AA7
15 CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# 7 VCC[051]
CPU_BSEL2 C21 AE6 H_PSI# AA9 B26
15 CPU_BSEL2 BSEL[2] PSI# H_PSI# 44 VCC[052] VCCA[01] +1.5VS
AA10 C26

2
VCC[053] VCCA[02]

10U_0805_6.3V6M

0.01U_0402_16V7K
Penryn AA12 VCC[054]
AA13 VCC[055] VID[0] AD6 CPU_VID0 44
AA15 VCC[056] VID[1] AF5 CPU_VID1 44 1 1
AA17 VCC[057] VID[2] AE5 CPU_VID2 44
AA18 AF4 C12 C11
VCC[058] VID[3] CPU_VID3 44
layout note: Rout H_DPRSTP# from ICH9 to IMVP6 then to GMCH & CPU AA20 VCC[059] VID[4] AE3 CPU_VID4 44 2 2
Resistor placed within AB9 VCC[060] VID[5] AF3 CPU_VID5 44
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs 0.5" of CPU pin.Trace AC10 VCC[061] VID[6] AE2 CPU_VID6 44
AB10 VCC[062]
should be at least 25 AB12 VCC[063]
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 mils away from any other AB14 VCC[064] VCCSENSE AF7 VCCSENSE VCCSENSE 44
AB15 VCC[065] Near pin B26
toggling signal. AB17 VCC[066] No stuff 27.4 pull down near IMVP for testing
AB18 AE7 VSSSENSE
COMP[0,2] trace width is VCC[067] VSSSENSE VSSSENSE 44
166 0 1 1
B 21 mils. COMP[1,3] trace Penryn B

width is 5 For 8 layer condition


.

200 0 0
Length match within 25 mils.
1
The trace width/space/other is
20/7/25.
266 0 0 0
+VCCP
1

R27
1K_0402_1% +CPU_CORE
2

+V_CPU_GTLREF
R28 1 2 100_0402_1% VCCSENSE
1

R29 R30 1 2 100_0402_1% VSSSENSE


2K_0402_1%
2

Close to CPU pin AD26


Close to CPU pin
within 500mils.
within 500mils.
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 5 of 48
5 4 3 2 1 hexainf@hotmail.com
5 4 3 2 1

High Frequence Decoupling


10uF 0805 X5R -> 85 degree.

+CPU_CORE Place these caps inside


the CPU socket.
Place these caps inside 1 1 1 1 1 1 1 1 1 1 ( Left side on Top ).
the CPU socket cavity. C216 C205 C529 C232 C258 C505 C504 C257 C261 C214
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
( Left side on Top ). 2 2 2 2 2 2 2 2 2 2

D D
CONN@
JCPU1D
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21
A11
A14
VSS[003] VSS[084] P24
R2
+CPU_CORE Place these caps inside
VSS[004] VSS[085]
A16 VSS[005] VSS[086] R5 the CPU socket.
A19 VSS[006] VSS[087] R22 Place these caps inside
A23 VSS[007] VSS[088] R25 1 1 1 1 1 1 1 1 1 1 ( Right side on Top ).
AF2 VSS[008] VSS[089] T1 the CPU socket cavity. C190 C210 C254 C208 C203 C200 C206 C204 C215 C226
B6 VSS[009] VSS[090] T4
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
B8 VSS[010] VSS[091] T23 ( Right side on Top side). 2 2 2 2 2 2 2 2 2 2
B11 VSS[011] VSS[092] T26
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24
B24 VSS[016] VSS[097] V2
C5 VSS[017] VSS[098] V5
+CPU_CORE
C8 VSS[018] VSS[099] V22
C11 VSS[019] VSS[100] V25
C14 VSS[020] VSS[101] W1
C16
C19
VSS[021] VSS[102] W4
W23
Place these caps inside 1 1 1 1 1 1
VSS[022] VSS[103]
C2 VSS[023] VSS[104] W26 the CPU socket cavity. C501
10U_0805_6.3V6M
C508
10U_0805_6.3V6M
C514
10U_0805_6.3V6M
C519
10U_0805_6.3V6M
C522
10U_0805_6.3V6M
C533
10U_0805_6.3V6M
C22 VSS[024] VSS[105] Y3
2 2 2 2 2 2
C25 VSS[025] VSS[106] Y6 ( Left side on Bottom ).
D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24
D8 VSS[028] VSS[109] AA2
D11 VSS[029] VSS[110] AA5
C C
D13 VSS[030] VSS[111] AA8
D16 VSS[031] VSS[112] AA11
D19 VSS[032] VSS[113] AA14
+CPU_CORE
D23 VSS[033] VSS[114] AA16
D26 VSS[034] VSS[115] AA19
E3 VSS[035] VSS[116] AA22
E6
E8
VSS[036] VSS[117] AA25
AB1
Place these caps inside 1 1 1 1 1 1
VSS[037] VSS[118]
E11 VSS[038] VSS[119] AB4 the CPU socket cavity. C502
10U_0805_6.3V6M
C510
10U_0805_6.3V6M
C515
10U_0805_6.3V6M
C520
10U_0805_6.3V6M
C526
10U_0805_6.3V6M
C532
10U_0805_6.3V6M
E14 VSS[039] VSS[120] AB8
2 2 2 2 2 2
E16 VSS[040] VSS[121] AB11 ( Right side on Bottom ).
E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
E24 VSS[043] VSS[124] AB19
F5 VSS[044] VSS[125] AB23
F8 VSS[045] VSS[126] AB26
F11 VSS[046] VSS[127] AC3
F13 VSS[047] VSS[128] AC6
F16 VSS[048] VSS[129] AC8
+CPU_CORE
F19 VSS[049] VSS[130] AC11
F2 VSS[050] VSS[131] AC14
F22 VSS[051] VSS[132] AC16
F25 AC19
VSS[052] VSS[133]
ESR <= 1.5m ohm
330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9
G4
G1
VSS[053] VSS[134] AC21
AC24
Place these caps inside 1 1 1 1
Place these caps inside
VSS[054] VSS[135]
G23 VSS[055] VSS[136] AD2 the CPU socket. the CPU socket.
C202

C207

C259

C255

G26 AD5 + + + +
H3
H6
VSS[056]
VSS[057]
VSS[137]
VSS[138] AD8
AD11
( Left side on Top ). ( Right side on Top side). Capacitor > 880 uF
VSS[058] VSS[139] 2 2 2 2
H21 VSS[059] VSS[140] AD13
H24 VSS[060] VSS[141] AD16
J2 VSS[061] VSS[142] AD19
B B
J5 VSS[062] VSS[143] AD22
J22 VSS[063] VSS[144] AD25
J25 VSS[064] VSS[145] AE1
K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16
L6 VSS[070] VSS[151] AE19
L21 VSS[071] VSS[152] AE23
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
M5 VSS[074] VSS[155] AF6
M22 VSS[075] VSS[156] AF8
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] A25
VSS[163] AF25
+VCCP
Penryn
.

1 1 1 1 1 1
C213 C209 C212 C185 C183 C184

0.1U_0402_16V 0.1U_0402_16V 0.1U_0402_16V 0.1U_0402_16V 0.1U_0402_16V 0.1U_0402_16V


2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 6 of 48
5 4 3 2 1
5 4 3 2 1

H_A#[3..35] 4 U4B
5 H_D#[0..63] U4A
A14 H_A#3 M36
H_A#_3 T7 RSVD1
H_D#0 H_A#4 M_CLK_DDR0

DDR CLK/ CONTROL/COMPENSATION


F2 H_D#_0 H_A#_4 C15 T11 N36 RSVD2 SA_CK_0 AP24 M_CLK_DDR0 13

0.01U_0402_16V7K
H_D#1 H_A#5 M_CLK_DDR1

2.2U_0603_6.3V4Z
G8 H_D#_1 H_A#_5 F16 T12 R33 RSVD3 SA_CK_1 AT21 M_CLK_DDR1 13
H_D#2 F8 H13 H_A#6 T33 AV24 M_CLK_DDR2 M_CLK_DDR2 14
H_D#_2 H_A#_6 +1.8V T13 RSVD4 SB_CK_0
H_D#3 E6 C18 H_A#7 AH9 AU20 M_CLK_DDR3 M_CLK_DDR3 14
H_D#_3 H_A#_7 T14 RSVD5 SB_CK_1
H_D#4 G2 M16 H_A#8 AH10
H_D#_4 H_A#_8 T15 RSVD6
H_D#5 H6 J13 H_A#9 1 1 AH12 AR24 M_CLK_DDR#0
H_D#_5 H_A#_9 T16 RSVD7 SA_CK#_0 M_CLK_DDR#0 13

1
C398

C400
H_D#6 H2 P16 H_A#10 AH13 AR21 M_CLK_DDR#1
H_D#_6 H_A#_10 T17 RSVD8 SA_CK#_1 M_CLK_DDR#1 13
H_D#7 F6 R16 H_A#11 R331 K12 AU24 M_CLK_DDR#2
H_D#_7 H_A#_11 T18 RSVD9 SB_CK#_0 M_CLK_DDR#2 14
H_D#8 D4 N17 H_A#12 1K_0402_1% AL34 AV20 M_CLK_DDR#3
H_D#_8 H_A#_12 2 2 T19 RSVD10 SB_CK#_1 M_CLK_DDR#3 14
H_D#9 H3 M13 H_A#13 AK34
H_D#_9 H_A#_13 T20 RSVD11
H_D#10 M9 E17 H_A#14 AN35 BC28 DDR_CKE0_DIMMA
T21 DDR_CKE0_DIMMA 13

2
H_D#11 H_D#_10 H_A#_14 H_A#15 +SMRCOMP_VOH RSVD12 SA_CKE_0 DDR_CKE1_DIMMA
M11 H_D#_11 H_A#_15 P17 T22 AM35 RSVD13 SA_CKE_1 AY28 DDR_CKE1_DIMMA 13
D H_D#12 H_A#16 DDR_CKE2_DIMMB D
J1 H_D#_12 H_A#_16 F17 T24 T24 RSVD14 SB_CKE_0 AY36 DDR_CKE2_DIMMB 14

1
H_D#13 J2 G20 H_A#17 BB36 DDR_CKE3_DIMMB
H_D#_13 H_A#_17 SB_CKE_1 DDR_CKE3_DIMMB 14

RSVD
H_D#14 N12 B19 H_A#18 R332 B31
H_D#_14 H_A#_18 T25 RSVD15
H_D#15 J6 J16 H_A#19 3.01K_0402_1% B2 BA17 DDR_CS0_DIMMA#
H_D#_15 H_A#_19 T26 RSVD16 SA_CS#_0 DDR_CS0_DIMMA# 13
H_D#16 P2 E20 H_A#20 M1 AY16 DDR_CS1_DIMMA#
H_D#_16 H_A#_20 T27 RSVD17 SA_CS#_1 DDR_CS1_DIMMA# 13
H_D#17 L2 H16 H_A#21 AV16 DDR_CS2_DIMMB#
DDR_CS2_DIMMB# 14

2
H_D#18 H_D#_17 H_A#_21 H_A#22 +SMRCOMP_VOL SB_CS#_0 DDR_CS3_DIMMB#
R2 H_D#_18 H_A#_22 J20 SB_CS#_1 AR13 DDR_CS3_DIMMB# 14
H_D#19 N9 L17 H_A#23 AY21
H_D#_19 H_A#_23 T28 RSVD20

1
0.01U_0402_16V7K
H_D#20 H_A#24 M_ODT0

2.2U_0603_6.3V4Z
L6 H_D#_20 H_A#_24 A17 SA_ODT_0 BD17 M_ODT0 13
H_D#21 M5 B17 H_A#25 1 1 R333 AY17 M_ODT1 M_ODT1 13
H_D#22 H_D#_21 H_A#_25 H_A#26 1K_0402_1% SA_ODT_1 M_ODT2 +1.8V
J3 H_D#_22 H_A#_26 L16 SB_ODT_0 BF15 M_ODT2 14

C403

C404
H_D#23 N2 C21 H_A#27 BG23 AY13 M_ODT3 M_ODT3 14
H_D#_23 H_A#_27 T41 RSVD22 SB_ODT_1
H_D#24 R1 J17 H_A#28 BF23
T44

2
H_D#25 H_D#_24 H_A#_28 H_A#29 2 2 RSVD23 SMRCOMP R328
N5 H_D#_25 H_A#_29 H20 T73 BH18 RSVD24 SM_RCOMP BG22 1 2 80.6_0402_1%
H_D#26 N6 B18 H_A#30 BF18 BH21 SMRCOMP# R329 1 2 80.6_0402_1%
H_D#_26 H_A#_30 T74 RSVD25 SM_RCOMP#
H_D#27 P13 K17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32 +SMRCOMP_VOH
N8 H_D#_28 H_A#_32 B20 SM_RCOMP_VOH BF28
H_D#29 L7 F21 H_A#33 BH28 +SMRCOMP_VOL
H_D#30 H_D#_29 H_A#_33 H_A#34 SM_RCOMP_VOL
N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35 AV42 +V_DDR_MCH_REF
H_D#32 H_D#_31 H_A#_35 +3VS SM_VREF
Y3 H_D#_32 SM_PWROK AR36
H_D#33 AD14 H12 H_ADS# R82 BF17 SM_REXT R40 1 2 499_0402_1%
H_D#_33 H_ADS# H_ADS# 4 SM_REXT
H_D#34 Y6 B16 H_ADSTB#0 PM_EXTTS#0 1 2 BC36 TP_SM_DRAMRST# T29 PAD
H_D#_34 H_ADSTB#_0 H_ADSTB#0 4 SM_DRAMRST#
H_D#35 Y10 G17 H_ADSTB#1
H_D#_35 H_ADSTB#_1 H_ADSTB#1 4
H_D#36 Y12 A9 H_BNR# 10K_0402_5% B38 CLK_MCH_DREFCLK
H_D#_36 H_BNR# H_BNR# 4 DPLL_REF_CLK CLK_MCH_DREFCLK 15
H_D#37 Y14 F11 H_BPRI# A38 CLK_MCH_DREFCLK#
H_D#_37 H_BPRI# H_BPRI# 4 DPLL_REF_CLK# CLK_MCH_DREFCLK# 15
H_D#38 Y7 G12 H_BR0# R83 E41 MCH_SSCDREFCLK
HOST
H_D#_38 H_BREQ# H_BR0# 4 DPLL_REF_SSCLK MCH_SSCDREFCLK 15
H_D#39 W2 E9 H_DEFER# PM_EXTTS#1 1 2 F41 MCH_SSCDREFCLK#
H_D#_39 H_DEFER# H_DEFER# 4 DPLL_REF_SSCLK# MCH_SSCDREFCLK# 15
H_D#40 AA8 B10 H_DBSY#
H_D#_40 H_DBSY# H_DBSY# 4
H_D#41 CLK_MCH_BCLK 10K_0402_5% CLK_MCH_3GPLL

CLK
Y9 H_D#_41 HPLL_CLK AH7 CLK_MCH_BCLK 15 PEG_CLK F43 CLK_MCH_3GPLL 15
H_D#42 AA13 AH6 CLK_MCH_BCLK# E43 CLK_MCH_3GPLL#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 15 PEG_CLK# CLK_MCH_3GPLL# 15
H_D#43 AA9 J11 H_DPWR#
C H_D#_43 H_DPWR# H_DPWR# 5 C
H_D#44 AA11 F9 H_DRDY#
H_D#_44 H_DRDY# H_DRDY# 4
H_D#45 AD11 H9 H_HIT#
H_D#_45 H_HIT# H_HIT# 4
H_D#46 AD10 E12 H_HITM# AE41 DMI_MRX_ITX_N0
H_D#_46 H_HITM# H_HITM# 4 DMI_RXN_0 DMI_MRX_ITX_N0 19
H_D#47 AD13 H11 H_LOCK# AE37 DMI_MRX_ITX_N1
H_D#_47 H_LOCK# H_LOCK# 4 DMI_RXN_1 DMI_MRX_ITX_N1 19
H_D#48 AE12 C9 H_TRDY# AE47 DMI_MRX_ITX_N2
H_D#_48 H_TRDY# H_TRDY# 4 DMI_RXN_2 DMI_MRX_ITX_N2 19
H_D#49 AE9 AH39 DMI_MRX_ITX_N3
H_D#_49 DMI_RXN_3 DMI_MRX_ITX_N3 19
H_D#50 AA2
H_D#51 H_D#_50 DMI_MRX_ITX_P0
AD8 H_D#_51 DMI_RXP_0 AE40 DMI_MRX_ITX_P0 19
H_D#52 AA3 MCH_CLKSEL0 T25 AE38 DMI_MRX_ITX_P1
H_D#_52 15 MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_MRX_ITX_P1 19
H_D#53 AD3 J8 H_DINV#0 MCH_CLKSEL1 R25 AE48 DMI_MRX_ITX_P2
H_D#_53 H_DINV#_0 H_DINV#0 5 15 MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_MRX_ITX_P2 19
H_D#54 AD7 L3 H_DINV#1 MCH_CLKSEL2 P25 AH40 DMI_MRX_ITX_P3
H_D#_54 H_DINV#_1 H_DINV#1 5 15 MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_MRX_ITX_P3 19
H_D#55 AE14 Y13 H_DINV#2 PAD T8 P20
H_D#_55 H_DINV#_2 H_DINV#2 5 CFG_3
H_D#56 AF3 Y1 H_DINV#3 PAD T9 P24 AE35 DMI_MTX_IRX_N0
H_D#_56 H_DINV#_3 H_DINV#3 5 CFG_4 DMI_TXN_0 DMI_MTX_IRX_N0 19
H_D#57 AC1 CFG5 C25 AE43 DMI_MTX_IRX_N1
H_D#_57 9 CFG5 CFG_5 DMI_TXN_1 DMI_MTX_IRX_N1 19
H_D#58 AE3 L10 H_DSTBN#0 CFG6 N24 AE46 DMI_MTX_IRX_N2
H_D#_58 H_DSTBN#_0 H_DSTBN#0 5 9 CFG6 CFG_6 DMI_TXN_2 DMI_MTX_IRX_N2 19
H_D#59 AC3 M7 H_DSTBN#1 CFG7 M24 AH42 DMI_MTX_IRX_N3
H_D#_59 H_DSTBN#_1 H_DSTBN#1 5 9 CFG7 CFG_7 DMI_TXN_3 DMI_MTX_IRX_N3 19
H_D#60 AE11 AA5 H_DSTBN#2 PAD T37 E21
H_D#_60 H_DSTBN#_2 H_DSTBN#2 5 CFG_8

DMI
CFG
H_D#61 AE8 AE6 H_DSTBN#3 CFG9 C23 AD35 DMI_MTX_IRX_P0
H_D#_61 H_DSTBN#_3 H_DSTBN#3 5 9 CFG9 CFG_9 DMI_TXP_0 DMI_MTX_IRX_P0 19
H_D#62 AG2 PAD T65 C24 AE44 DMI_MTX_IRX_P1
H_D#_62 CFG_10 DMI_TXP_1 DMI_MTX_IRX_P1 19
H_D#63 AD6 L9 H_DSTBP#0 PAD T40 N21 AF46 DMI_MTX_IRX_P2
H_D#_63 H_DSTBP#_0 H_DSTBP#0 5 CFG_11 DMI_TXP_2 DMI_MTX_IRX_P2 19
M8 H_DSTBP#1 PAD T67 CFG12 P21 AH43 DMI_MTX_IRX_P3
H_DSTBP#_1 H_DSTBP#1 5 CFG_12 DMI_TXP_3 DMI_MTX_IRX_P3 19
AA6 H_DSTBP#2 PAD T47 CFG13 T21
H_DSTBP#_2 H_DSTBP#2 5 CFG_13
H_SWNG C5 AE5 H_DSTBP#3 PAD T10 R20
H_SWING H_DSTBP#_3 H_DSTBP#3 5 CFG_14
H_RCOMP E3 PAD T66 M20
H_RCOMP H_REQ#0 CFG16 CFG_15
H_REQ#_0 B15 H_REQ#0 4 9 CFG16 L21 CFG_16
K13 H_REQ#1 PAD T68 H21
H_REQ#_1 H_REQ#1 4 CFG_17
H_REQ#2

GRAPHICS VID
H_REQ#_2 F13 H_REQ#2 4 PAD T39 P29 CFG_18
B13 H_REQ#3 CFG19 R28
H_REQ#_3 H_REQ#3 4 9 CFG19 CFG_19
4 H_RESET# H_RESET# C12 B14 H_REQ#4 CFG20 T28 B33
H_CPURST# H_REQ#_4 H_REQ#4 4 9 CFG20 CFG_20 GFX_VID_0 T30
5 H_CPUSLP# H_CPUSLP# E11 B32
H_CPUSLP# GFX_VID_1 T31
B6 H_RS#0 H_RS#0 4 G33
H_RS#_0 GFX_VID_2 T32
F12 H_RS#1 H_RS#1 4 F33
B H_RS#_1 GFX_VID_3 T33 B
C8 H_RS#2 H_RS#2 4 19 PM_BMBUSY# PM_BMBUSY# R29 E33
H_RS#_2 PM_SYNC# GFX_VID_4 T34
+H_VREF A11 H_DPRSTP# B7
H_AVREF 5,18,44 H_DPRSTP# PM_DPRSTP#
B11 PM_EXTTS#0 N33
H_DVREF 13 PM_EXTTS#0 PM_EXT_TS#_0
PM_EXTTS#1 P32
14 PM_EXTTS#1 PM_EXT_TS#_1

PM
CANTIGA_1p0 PM_PWROK_R AT40 C34
PWROK GFX_VR_EN T35 +VCCP
PLT_RST# 1 2 PLT_RST#_NB AT11
17,27,30,31 PLT_RST# RSTIN#
4,18 H_THERMTRIP# R523 100_0402_5% THERMTRIP# T20
DPRSLPVR THERMTRIP#
19,44 DPRSLPVR R32 DPRSLPVR

1
AH37 CL_CLK0 R100
CL_CLK CL_CLK0 19
1 2 PM_PWROK_R AH36 CL_DATA0 1K_0402_1%
19,27 ICH_PWROK CL_DATA CL_DATA0 19
R408 0_0402_5% BG48 AN36 M_PWROK
NC_1 CL_PWROK M_PWROK 19
1 2 BF48 AJ35 CL_RST#
19,27,44 VGATE CL_RST# 19

2
NC_2 CL_RST#

ME
@R407
@ R407 0_0402_5% BD48 AH34 +CL_VREF
NC_3 CL_VREF
Layout Note: BC48 NC_4

1
BH47 1
H_RCOMP / H_VREF / H_SWNG BG47
NC_5 C181 R99
NC_6
trace width and spacing is 10/20 +1.8V
BE47 NC_7 DDPC_CTRLCLK N28 T36
0.1U_0402_16V 511_0402_1%
Layout Note: BH46 NC_8 DDPC_CTRLDATA M28 T48 2
V_DDR_MCH_REF BF46 G36 T63

2
+VCCP NC_9 SDVO_CTRLCLK

NC
BG45 E36 T64
trace width and NC_10 SDVO_CTRLDATA
1

+VCCP BH44 K36 CLKREQ#_7


NC_11 CLKREQ# CLKREQ#_7 15
spacing is 20/20. R42 BH43 NC_12 ICH_SYNC# H36 MCH_ICH_SYNC#
MCH_ICH_SYNC# 19
221_0603_1%
1K_0402_1%

1K_0402_1% BH6

MISC
NC_13
1

BH5 NC_14
R45 R322 BG4 B12 TSATN# 2 1 +VCCP
2

+V_DDR_MCH_REF NC_15 TSATN# R521 56_0402_5%


13,14 +V_DDR_MCH_REF BH3 NC_16
BF3 NC_17
1
0.1U_0402_16V

BH2
2

+H_VREF H_RCOMP H_SWNG R43 NC_18


1 BG2 NC_19 HDA_BCLK B28 T99
C121 1K_0402_1% BE2 B30
NC_20 HDA_RST# T100
24.9_0402_1%

0.1U_0402_16V

BG1 NC_21 HDA_SDI B29 T101


1

1
100_0402_1%
0.1U_0402_16V

A A
1 1 BF1 C29 T102
2

2 NC_22 HDA_SDO
2K_0402_1%

HDA
R46 C391 R324 R323 C386 BD1 A28
NC_23 HDA_SYNC T103
BC1 NC_24
@ F1
2 2 NC_25
A47
2

NC_26
CANTIGA_1p0
Security Classification Compal Secret Data Compal Electronics, Inc.
within 100 mils from NB Near B3 pin Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 7 of 48
5 4 3 2 1 hexainf@hotmail.com
5 4 3 2 1

D D

13 DDR_A_D[0..63] 14 DDR_B_D[0..63]
U4D U4E
DDR_A_D0 AJ38 BD21 DDR_A_BS#0 DDR_B_D0 AK47 BC16 DDR_B_BS#0
SA_DQ_0 SA_BS_0 DDR_A_BS#0 13 SB_DQ_0 SB_BS_0 DDR_B_BS#0 14
DDR_A_D1 AJ41 BG18 DDR_A_BS#1 DDR_B_D1 AH46 BB17 DDR_B_BS#1
SA_DQ_1 SA_BS_1 DDR_A_BS#1 13 SB_DQ_1 SB_BS_1 DDR_B_BS#1 14
DDR_A_D2 AN38 AT25 DDR_A_BS#2 DDR_B_D2 AP47 BB33 DDR_B_BS#2
SA_DQ_2 SA_BS_2 DDR_A_BS#2 13 SB_DQ_2 SB_BS_2 DDR_B_BS#2 14
DDR_A_D3 AM38 DDR_B_D3 AP46
DDR_A_D4 SA_DQ_3 DDR_A_RAS# DDR_B_D4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDR_A_RAS# 13 AJ46 SB_DQ_4
DDR_A_D5 AJ40 BD20 DDR_A_CAS# DDR_B_D5 AJ48 AU17 DDR_B_RAS#
SA_DQ_5 SA_CAS# DDR_A_CAS# 13 SB_DQ_5 SB_RAS# DDR_B_RAS# 14
DDR_A_D6 AM44 AY20 DDR_A_WE# DDR_A_WE# 13 DDR_B_D6 AM48 BG16 DDR_B_CAS#
SA_DQ_6 SA_WE# SB_DQ_6 SB_CAS# DDR_B_CAS# 14
DDR_A_D7 AM42 DDR_B_D7 AP48 BF14 DDR_B_WE# DDR_B_WE# 14
DDR_A_D8 SA_DQ_7 DDR_B_D8 SB_DQ_7 SB_WE#
AN43 SA_DQ_8 AU47 SB_DQ_8
DDR_A_D9 AN44 DDR_B_D9 AU46
SA_DQ_9 DDR_A_DM[0..7] 13 SB_DQ_9
DDR_A_D10 AU40 DDR_B_D10 BA48
DDR_A_D11 SA_DQ_10 DDR_A_DM0 DDR_B_D11 SB_DQ_10
AT38 SA_DQ_11 SA_DM_0 AM37 AY48 SB_DQ_11 DDR_B_DM[0..7] 14
DDR_A_D12 AN41 AT41 DDR_A_DM1 DDR_B_D12 AT47 AM47 DDR_B_DM0
DDR_A_D13 SA_DQ_12 SA_DM_1 DDR_A_DM2 DDR_B_D13 SB_DQ_12 SB_DM_0 DDR_B_DM1
AN39 SA_DQ_13 SA_DM_2 AY41 AR47 SB_DQ_13 SB_DM_1 AY47
DDR_A_D14 AU44 AU39 DDR_A_DM3 DDR_B_D14 BA47 BD40 DDR_B_DM2
DDR_A_D15 SA_DQ_14 SA_DM_3 DDR_A_DM4 DDR_B_D15 SB_DQ_14 SB_DM_2 DDR_B_DM3
AU42 SA_DQ_15 SA_DM_4 BB12 BC47 SB_DQ_15 SB_DM_3 BF35
DDR_A_D16 AV39 AY6 DDR_A_DM5 DDR_B_D16 BC46 BG11 DDR_B_DM4
DDR_A_D17 SA_DQ_16 SA_DM_5 DDR_A_DM6 DDR_B_D17 SB_DQ_16 SB_DM_4 DDR_B_DM5
AY44 SA_DQ_17 SA_DM_6 AT7 BC44 SB_DQ_17 SB_DM_5 BA3

A
DDR_A_D18 BA40 AJ5 DDR_A_DM7 DDR_B_D18 BG43 AP1 DDR_B_DM6

B
DDR_A_D19 SA_DQ_18 SA_DM_7 DDR_B_D19 SB_DQ_18 SB_DM_6 DDR_B_DM7
BD43 SA_DQ_19 DDR_A_DQS[0..7] 13 BF43 SB_DQ_19 SB_DM_7 AK2
DDR_A_D20 AV41 AJ44 DDR_A_DQS0 DDR_B_D20 BE45
SA_DQ_20 SA_DQS_0 SB_DQ_20 DDR_B_DQS[0..7] 14
DDR_A_D21 AY43 AT44 DDR_A_DQS1 DDR_B_D21 BC41 AL47 DDR_B_DQS0
DDR_A_D22 SA_DQ_21 SA_DQS_1 DDR_A_DQS2 DDR_B_D22 SB_DQ_21 SB_DQS_0 DDR_B_DQS1
BB41 SA_DQ_22 SA_DQS_2 BA43 BF40 SB_DQ_22 SB_DQS_1 AV48
DDR_A_D23 BC40 MEMORY BC37 DDR_A_DQS3 DDR_B_D23 BF41 DDR_B_DQS2

MEMORY
SA_DQ_23 SA_DQS_3 SB_DQ_23 SB_DQS_2 BG41
DDR_A_D24 AY37 AW12 DDR_A_DQS4 DDR_B_D24 BG38 BG37 DDR_B_DQS3
DDR_A_D25 SA_DQ_24 SA_DQS_4 DDR_A_DQS5 DDR_B_D25 SB_DQ_24 SB_DQS_3 DDR_B_DQS4
BD38 SA_DQ_25 SA_DQS_5 BC8 BF38 SB_DQ_25 SB_DQS_4 BH9
DDR_A_D26 AV37 AU8 DDR_A_DQS6 DDR_B_D26 BH35 BB2 DDR_B_DQS5
DDR_A_D27 SA_DQ_26 SA_DQS_6 DDR_A_DQS7 DDR_B_D27 SB_DQ_26 SB_DQS_5 DDR_B_DQS6
AT36 SA_DQ_27 SA_DQS_7 AM7 DDR_A_DQS#[0..7] 13 BG35 SB_DQ_27 SB_DQS_6 AU1
DDR_A_D28 AY38 AJ43 DDR_A_DQS#0 DDR_B_D28 BH40 AN6 DDR_B_DQS7
C SA_DQ_28 SA_DQS#_0 SB_DQ_28 SB_DQS_7 DDR_B_DQS#[0..7] 14 C
DDR_A_D29 BB38 AT43 DDR_A_DQS#1 DDR_B_D29 BG39 AL46 DDR_B_DQS#0
DDR_A_D30 SA_DQ_29 SA_DQS#_1 DDR_A_DQS#2 DDR_B_D30 SB_DQ_29 SB_DQS#_0 DDR_B_DQS#1
AV36 SA_DQ_30 SA_DQS#_2 BA44 BG34 SB_DQ_30 SB_DQS#_1 AV47
DDR_A_D31 AW36 BD37 DDR_A_DQS#3 DDR_B_D31 BH34 BH41 DDR_B_DQS#2
DDR_A_D32 SA_DQ_31 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D32 SB_DQ_31 SB_DQS#_2 DDR_B_DQS#3
BD13 SA_DQ_32 SA_DQS#_4 AY12 BH14 SB_DQ_32 SB_DQS#_3 BH37
DDR_A_D33 AU11 BD8 DDR_A_DQS#5 DDR_B_D33 BG12 BG9 DDR_B_DQS#4
DDR_A_D34 SA_DQ_33 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D34 SB_DQ_33 SB_DQS#_4 DDR_B_DQS#5
BC11 SA_DQ_34 SA_DQS#_6 AU9 BH11 SB_DQ_34 SB_DQS#_5 BC2
DDR_A_D35 BA12 AM8 DDR_A_DQS#7 DDR_B_D35 BG8 AT2 DDR_B_DQS#6
SYSTEM

SA_DQ_35 SA_DQS#_7 DDR_A_MA[0..14] 13 SB_DQ_35 SB_DQS#_6


DDR_A_D36 DDR_B_D36 DDR_B_DQS#7

SYSTEM
AU13 SA_DQ_36 BH12 SB_DQ_36 SB_DQS#_7 AN5
DDR_A_D37 AV13 BA21 DDR_A_MA0 DDR_B_D37 BF11 DDR_B_MA[0..14] 14
DDR_A_D38 SA_DQ_37 SA_MA_0 DDR_A_MA1 DDR_B_D38 SB_DQ_37 DDR_B_MA0
BD12 SA_DQ_38 SA_MA_1 BC24 BF8 SB_DQ_38 SB_MA_0 AV17
DDR_A_D39 BC12 BG24 DDR_A_MA2 DDR_B_D39 BG7 BA25 DDR_B_MA1
DDR_A_D40 SA_DQ_39 SA_MA_2 DDR_A_MA3 DDR_B_D40 SB_DQ_39 SB_MA_1 DDR_B_MA2
BB9 SA_DQ_40 SA_MA_3 BH24 BC5 SB_DQ_40 SB_MA_2 BC25
DDR_A_D41 BA9 BG25 DDR_A_MA4 DDR_B_D41 BC6 AU25 DDR_B_MA3
DDR_A_D42 SA_DQ_41 SA_MA_4 DDR_A_MA5 DDR_B_D42 SB_DQ_41 SB_MA_3 DDR_B_MA4
AU10 SA_DQ_42 SA_MA_5 BA24 AY3 SB_DQ_42 SB_MA_4 AW25
DDR_A_D43 AV9 BD24 DDR_A_MA6 DDR_B_D43 AY1 BB28 DDR_B_MA5
DDR_A_D44 SA_DQ_43 SA_MA_6 DDR_A_MA7 DDR_B_D44 SB_DQ_43 SB_MA_5 DDR_B_MA6
BA11 SA_DQ_44 SA_MA_7 BG27 BF6 SB_DQ_44 SB_MA_6 AU28
DDR_A_D45 BD9 BF25 DDR_A_MA8 DDR_B_D45 BF5 AW28 DDR_B_MA7
DDR_A_D46 SA_DQ_45 SA_MA_8 DDR_A_MA9 DDR_B_D46 SB_DQ_45 SB_MA_7 DDR_B_MA8
AY8 SA_DQ_46 SA_MA_9 AW24 BA1 SB_DQ_46 SB_MA_8 AT33
DDR_A_D47 BA6 BC21 DDR_A_MA10 DDR_B_D47 BD3 BD33 DDR_B_MA9
DDR_A_D48 SA_DQ_47 SA_MA_10 DDR_A_MA11 DDR_B_D48 SB_DQ_47 SB_MA_9 DDR_B_MA10
DDR

AV5 SA_DQ_48 SA_MA_11 BG26 AV2 SB_DQ_48 SB_MA_10 BB16


DDR_A_D49 DDR_A_MA12 DDR_B_D49 DDR_B_MA11

DDR
AV7 SA_DQ_49 SA_MA_12 BH26 AU3 SB_DQ_49 SB_MA_11 AW33
DDR_A_D50 AT9 BH17 DDR_A_MA13 DDR_B_D50 AR3 AY33 DDR_B_MA12
DDR_A_D51 SA_DQ_50 SA_MA_13 DDR_A_MA14 DDR_B_D51 SB_DQ_50 SB_MA_12 DDR_B_MA13
AN8 SA_DQ_51 SA_MA_14 AY25 AN2 SB_DQ_51 SB_MA_13 BH15
DDR_A_D52 AU5 DDR_B_D52 AY2 AU33 DDR_B_MA14
DDR_A_D53 SA_DQ_52 DDR_B_D53 SB_DQ_52 SB_MA_14
AU6 SA_DQ_53 AV1 SB_DQ_53
DDR_A_D54 AT5 DDR_B_D54 AP3
DDR_A_D55 SA_DQ_54 DDR_B_D55 SB_DQ_54
AN10 SA_DQ_55 AR1 SB_DQ_55
DDR_A_D56 AM11 DDR_B_D56 AL1
DDR_A_D57 SA_DQ_56 DDR_B_D57 SB_DQ_56
AM5 SA_DQ_57 AL2 SB_DQ_57
DDR_A_D58 AJ9 DDR_B_D58 AJ1
DDR_A_D59 SA_DQ_58 DDR_B_D59 SB_DQ_58
AJ8 SA_DQ_59 AH1 SB_DQ_59
DDR_A_D60 AN12 DDR_B_D60 AM2
B DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60 B
AM13 SA_DQ_61 AM3 SB_DQ_61
DDR_A_D62 AJ11 DDR_B_D62 AH3
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AJ12 SA_DQ_63 AJ3 SB_DQ_63
CANTIGA_1p0 CANTIGA_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 8 of 48
5 4 3 2 1
5 4 3 2 1

U4C
R56 within 500 mils from
pin T37,T36 PEGCOMP trace width Strap Pin Table
R95 +VCC_PEG and spacing is 20/25 mils.
L32 L_BKLT_CTRL 000 = FSB 1066MHz
16 GMCH_ENBKL GMCH_ENBKL G32 T37 1 2 CFG[2:0] FSB Freq select
R81 1 L_BKLT_EN PEG_COMPI 010 = FSB 800MHz
+3VS 2 10K_0402_5% UMA@ CTRL_CLK M32 L_CTRL_CLK PEG_COMPO T36 49.9_0402_1%

R80
1 2 10K_0402_5% UMA@ CTRL_DATA M33
011 = FSB 667MHz
GMCH_EDID_CLK_LCD L_CTRL_DATA PEG_NRX_GTX_N0
16 GMCH_EDID_CLK_LCD K33 L_DDC_CLK PEG_RX#_0 H44 Others = Reserved
GMCH_EDID_DAT_LCD J33 J46 PEG_NRX_GTX_N1
16 GMCH_EDID_DAT_LCD L_DDC_DATA PEG_RX#_1
L44 PEG_NRX_GTX_N2
PEG_RX#_2 PEG_NRX_GTX_N3
PEG_RX#_3 L40 CFG[4:3] Reserved
16 GMCH_LVDDEN GMCH_LVDDEN M29 N41 PEG_NRX_GTX_N4
L_VDD_EN PEG_RX#_4 PEG_NRX_GTX_N5 PEG_NRX_GTX_N[0..15]
1 2 C44 LVDS_IBG PEG_RX#_5 P48 PEG_NRX_GTX_N[0..15] 31 0 = DMI x 2
R94 2.4K_0402_1%~D B43 N44 PEG_NRX_GTX_N6 CFG5 (DMI select)
LVDS_VBG PEG_RX#_6 1 = DMI x 4
E37
E38
LVDS_VREFH PEG_RX#_7 T43
U43
PEG_NRX_GTX_N7
PEG_NRX_GTX_N8 *
0 = The iTPM Host Interface is enable
D LVDS_VREFL PEG_RX#_8
* D

LVDS
16 GMCH_LVDSAC- GMCH_LVDSAC- C41 Y43 PEG_NRX_GTX_N9 CFG6
GMCH_LVDSAC+ LVDSA_CLK# PEG_RX#_9 PEG_NRX_GTX_N10
16 GMCH_LVDSAC+ C40 LVDSA_CLK PEG_RX#_10 Y48 1 = The iTPM Host Interface is disable
B37 Y36 PEG_NRX_GTX_N11
LVDSB_CLK# PEG_RX#_11 PEG_NRX_GTX_N12
A37 LVDSB_CLK PEG_RX#_12 AA43 0 =(TLS)chiper suite with no confidentiality
AD37 PEG_NRX_GTX_N13 CFG7 (Intel Management
GMCH_LVDSA0- PEG_RX#_13 PEG_NRX_GTX_N14
H47 AC47 1 =(TLS)chiper suite with confidentiality
16 GMCH_LVDSA0-
16 GMCH_LVDSA1-
16 GMCH_LVDSA2-
GMCH_LVDSA1-
GMCH_LVDSA2-
E46
G40
LVDSA_DATA#_0
LVDSA_DATA#_1
PEG_RX#_14
PEG_RX#_15 AD39 PEG_NRX_GTX_N15 Engine Crypto strap) *
GMCH_LVDSA3- LVDSA_DATA#_2 PEG_NRX_GTX_P0
T38 A40 H43

GRAPHICS
LVDSA_DATA#_3 PEG_RX_0 PEG_NRX_GTX_P1
PEG_RX_1 J44 CFG8 Reserved
16 GMCH_LVDSA0+ GMCH_LVDSA0+ H48 L43 PEG_NRX_GTX_P2
GMCH_LVDSA1+ LVDSA_DATA_0 PEG_RX_2 PEG_NRX_GTX_P3 PEG_NRX_GTX_P[0..15]
16 GMCH_LVDSA1+ D45 LVDSA_DATA_1 PEG_RX_3 L41 PEG_NRX_GTX_P[0..15] 31
16 GMCH_LVDSA2+ GMCH_LVDSA2+ F40 N40 PEG_NRX_GTX_P4 CFG9 0 = Reverse Lane,15->0, 14->1
GMCH_LVDSA3+ LVDSA_DATA_2 PEG_RX_4 PEG_NRX_GTX_P5
T46 B40 LVDSA_DATA_3 PEG_RX_5 P47
N43 PEG_NRX_GTX_P6 (PCIE Graphics Lane Reversal) 1 = Normal Operation,Lane Number in order
PEG_RX_6 PEG_NRX_GTX_P7
A41 T42
H38
G37
LVDSB_DATA#_0
LVDSB_DATA#_1
PEG_RX_7
PEG_RX_8 U42
Y42
PEG_NRX_GTX_P8
PEG_NRX_GTX_P9 0 = Enable
*
LVDSB_DATA#_2 PEG_RX_9 PEG_NRX_GTX_P10
J37 LVDSB_DATA#_3 PEG_RX_10 W47 CFG10 (PCIE Lookback enable)
Y37 PEG_NRX_GTX_P11 1 = Disable
B42
G38
LVDSB_DATA_0
PEG_RX_11
PEG_RX_12 AA42
AD36
PEG_NRX_GTX_P12
PEG_NRX_GTX_P13 CFG11 Reserved
*
for test point need LVDSB_DATA_1 PEG_RX_13 PEG_NRX_GTX_P14
F37 LVDSB_DATA_2 PEG_RX_14 AC48 PEG_NTX_GRX_N[0..15] 31

PCI-EXPRESS
K37 AD40 PEG_NRX_GTX_P15 CFG[13:12] (XOR/ALLZ) 00 = Reserved
T45 LVDSB_DATA_3 PEG_RX_15
01 = XOR Mode Enabled
J41 PEG_TXN0 C568 1 2 VGA@ 0.1U_0402_16V PEG_NTX_GRX_N0 10 = All Z Mode Enabled
PEG_TX#_0 PEG_TXN1 C537 VGA@ 0.1U_0402_16V PEG_NTX_GRX_N1
M46 1 2 11 = Normal Operation(Default)
1
75_0402_1%
1
2
2 R65
F25
H25
TVA_DAC
PEG_TX#_1
PEG_TX#_2 M47
M40
PEG_TXN2
PEG_TXN3
C538
C539
1
1
2
2
VGA@ 0.1U_0402_16V
VGA@ 0.1U_0402_16V
PEG_NTX_GRX_N2
PEG_NTX_GRX_N3 CFG[15:14] Reserved
*
75_0402_1% TVB_DAC PEG_TX#_3
1 2 R67 K25 TVC_DAC PEG_TX#_4 M42 PEG_TXN4 C540 1 2 VGA@ 0.1U_0402_16V PEG_NTX_GRX_N4

TV
75_0402_1% R68 R48 PEG_TXN5 C541 1 2 VGA@ 0.1U_0402_16V PEG_NTX_GRX_N5
UMA@ PEG_TX#_5 PEG_TXN6 C542 VGA@ 0.1U_0402_16V PEG_NTX_GRX_N6
UMA@
H24 TV_RTN PEG_TX#_6 N38 1 2 CFG16 (FSB Dynamic ODT) 0 = Disabled
T40 PEG_TXN7 C543 1 2 VGA@ 0.1U_0402_16V PEG_NTX_GRX_N7
UMA@ PEG_TX#_7 PEG_TXN8 C544 VGA@ 0.1U_0402_16V PEG_NTX_GRX_N8
U37 1 2 1 = Enabled
C31
PEG_TX#_8
PEG_TX#_9 U40
Y40
PEG_TXN9
PEG_TXN10
C545
C546
1
1
2
2
VGA@ 0.1U_0402_16V
VGA@ 0.1U_0402_16V
PEG_NTX_GRX_N9
PEG_NTX_GRX_N10
*
TV_DCONSEL_0 PEG_TX#_10 PEG_TXN11 C547 VGA@ 0.1U_0402_16V PEG_NTX_GRX_N11
C E32 TV_DCONSEL_1 PEG_TX#_11 AA46 1 2 CFG[18:17] Reserved C
AA37 PEG_TXN12 C548 1 2 VGA@ 0.1U_0402_16V PEG_NTX_GRX_N12
CRT_B PEG_TX#_12 PEG_TXN13 C549 VGA@ 0.1U_0402_16V PEG_NTX_GRX_N13
16 CRT_B PEG_TX#_13 AA40 1 2
CRT_G AD43 PEG_TXN14 C550 1 2 VGA@ 0.1U_0402_16V PEG_NTX_GRX_N14 CFG19 (DMI Lane Reversal) 0 = Normal Operation
16
16
CRT_G
CRT_R CRT_R PEG_TX#_14
PEG_TX#_15 AC46 PEG_TXN15 C551 1 2 VGA@ 0.1U_0402_16V PEG_NTX_GRX_N15
PEG_NTX_GRX_P[0..15] 31

(Lane number in Order)


*
2

2
150_0402_1%

150_0402_1%

150_0402_1%

E28 J42 PEG_TXP0 C552 1 2 VGA@ 0.1U_0402_16V PEG_NTX_GRX_P0


CRT_BLUE PEG_TX_0 PEG_TXP1 C553 VGA@ 0.1U_0402_16V PEG_NTX_GRX_P1
PEG_TX_1 L46 1 2 1 = Reverse Lane
UMA@

UMA@

UMA@
R74

R76

R75

G28 M48 PEG_TXP2 C554 1 2 VGA@ 0.1U_0402_16V PEG_NTX_GRX_P2


CRT_GREEN PEG_TX_2 PEG_TXP3 C555 VGA@ 0.1U_0402_16V PEG_NTX_GRX_P3
M39 1 2
J28
PEG_TX_3
M43 PEG_TXP4 C556 1 2 VGA@ 0.1U_0402_16V PEG_NTX_GRX_P4 CFG20 (PCIE/SDVO concurrent) 0 = Only PCIE or SDVO is operational. *
1

CRT_RED PEG_TX_4
G29 CRT_IRTN
VGA PEG_TX_5
PEG_TX_6
R47
N37
PEG_TXP5
PEG_TXP6
C557
C558
1
1
2
2
VGA@ 0.1U_0402_16V
VGA@ 0.1U_0402_16V
PEG_NTX_GRX_P5
PEG_NTX_GRX_P6 1 = PCIE/SDVO are operating simu.
T39 PEG_TXP7 C559 1 2 VGA@ 0.1U_0402_16V PEG_NTX_GRX_P7
3VDDCCL PEG_TX_7 PEG_TXP8 C560 VGA@ 0.1U_0402_16V PEG_NTX_GRX_P8
16 3VDDCCL H32 CRT_DDC_CLK PEG_TX_8 U36 1 2
3VDDCDA J32 U39 PEG_TXP9 C561 1 2 VGA@ 0.1U_0402_16V PEG_NTX_GRX_P9
16 3VDDCDA CRT_DDC_DATA PEG_TX_9
16 CRT_HSYNC CRT_HSYNC J29 Y39 PEG_TXP10 C562 1 2 VGA@ 0.1U_0402_16V PEG_NTX_GRX_P10 @ R66 1 2 2.21K_0402_1%~D
CRT_HSYNC PEG_TX_10 7 CFG5
E29 Y46 PEG_TXP11 C563 1 2 VGA@ 0.1U_0402_16V PEG_NTX_GRX_P11
CRT_VSYNC CRT_TVO_IREF PEG_TX_11 PEG_TXP12 C564 VGA@ 0.1U_0402_16V PEG_NTX_GRX_P12 @ R58
16 CRT_VSYNC L29 CRT_VSYNC PEG_TX_12 AA36 1 2 7 CFG6 1 2 2.21K_0402_1%~D
AA39 PEG_TXP13 C565 1 2 VGA@ 0.1U_0402_16V PEG_NTX_GRX_P13
PEG_TX_13 PEG_TXP14 C566 VGA@ 0.1U_0402_16V PEG_NTX_GRX_P14 @ R59
PEG_TX_14 AD42 1 2 7 CFG7 1 2 2.21K_0402_1%~D
2

AD46 PEG_TXP15 C567 1 2 VGA@ 0.1U_0402_16V PEG_NTX_GRX_P15


PEG_TX_15 @ R55
0_0402_5% 7 CFG9 1 2 2.21K_0402_1%~D
2

0_0402_5%
R676 R675 R334 CANTIGA_1p0 @ R70 1 2 2.21K_0402_1%~D
7 CFG16
VGA@ VGA@ 1K_0402_1%
1

+3VS UMA@ UMA@ CFG[5:16] have internal pullup


1

R483 2.2K_0402_5%
1 2 GMCH_EDID_CLK_LCD
UMA@
R484 2.2K_0402_5%
1 2 GMCH_EDID_DAT_LCD +3VS

@ R72 1 2 4.02K_0402_1%~D
7 CFG19
R65 R67 R334 @ R73 1 2 4.02K_0402_1%~D
7 CFG20
B B
R74 R75
CFG[19:20] have internal pulldown

0_0402_5% 0_0402_5% 0_0402_5%


VGA@ VGA@ VGA@
0_0402_5% 0_0402_5%
VGA@ VGA@

R68

R76

0_0402_5%
VGA@
0_0402_5%
VGA@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 9 of 48 hexainf@hotmail.com
5 4 3 2 1
5 4 3 2 1

+3VS_DAC_CRT +3VS
L11 UMA@ +1.05VS_DPLLA
1 2
+VCCP +VCCP
100U_D2_6.3VM_R45~D

BLM18PG181SN1D_0603 UMA@
L13 +VCCP

0.01U_0402_16V7K

0.1U_0402_16V
C407 UMA@
1 2 +V1.05VS_AXF

C411 UMA@
1 1 1 COIL 2.2U +-20% IHLP-2525CZ-ER-2R2-M-01 8A U4H 1 2 R101
L15 @ 852mA 1 2
C219

0.1U_0402_16V

10U_0805_10V

10U_0805_10V

1U_0603_10V4Z
+ U13 10UH_LB2012T100MR_20%_0805~D 0_0805_5%
VTT_1 1

4.7U_0805_10V4Z

220U_D2_4VY_R15M

C173

C182
73mA T13 1 1 1
2 2 VTT_2

220U_D2_4VY_R15M
B27 U12 +
2 VCCA_CRT_DAC_1 VTT_3 1 1 1

C384

C191

C113

C69
A26 T12 +
+3VS_DAC_CRT VCCA_CRT_DAC_2 VTT_4

C370
UMA@ U11
2.68mA VTT_5 2 2 2
VTT_6 T11
2 2 UMA@ 2 2
A25 U10

CRT
+3VS_DAC_BG VCCA_DAC_BG VTT_7
B25 VSSA_DAC_BG VTT_8 T10
D U9 UMA@ UMA@ D
+3VS_DAC_BG +3VS_DAC_CRT VTT_9
VTT_10 T9
VTT_11 U8
R836 1 2 0_0402_5%~D +1.05VS_DPLLA 64.8mA F47 T8
VCCA_DPLLA VTT_12

0.47U_0603_10V7K

4.7U_0805_10V4Z

2.2U_0805_16V4Z
UMA@ U7

VTT
VTT_13 +1.8V_SM_CK
0.01U_0402_16V7K

0.1U_0402_16V

+1.05VS_DPLLB 64.8mA L48 T7 1 1 1 +1.8V


VCCA_DPLLB VTT_14 +1.05VS_DPLLB +VCCP
C405 UMA@

C408 UMA@

1 1 U6 R102
VTT_15 L14

C383

C373

C56
24mA AD1 T6 UMA@ 1 2

PLL
+1.05VS_HPLL VCCA_HPLL VTT_16
U5 1 2 0_0805_5%
VTT_17 2 2 2

0.1U_0402_16V

1_0402_5%~D C96
+1.05VS_MPLL 139.2mA AE1 T5
2 2 VCCA_MPLL VTT_18

C174

C178

10U_0805_10V
V3 10UH_LB2012T100MR_20%_0805~D
VTT_19

R137
VTT_20 U3 1 1
+1.8V_TXLVDS 13.2mA J48 V2
VCCA_LVDS VTT_21
1 U2

A LVDS
VTT_22

0.1U_0402_16V
C413 UMA@ J47 T2 UMA@ UMA@
VSSA_LVDS VTT_23 2 2

10U_0805_10V
VTT_24 V1
1000P_0402_50V7K U1 1 1
2 VTT_25

C102
414uA
+1.5VS_PEG_BG AD48 VCCA_PEG_BG
2 2

A PEG
+1.5VS +1.05VS_HPLL +VCCP
50mA
1 +1.05VS_PEGPLL AA48 L29
C175 VCCA_PEG_PLL
1 2
MBK2012121YZF_0805

4.7U_0805_10V4Z
0.1U_0402_16V 720mA AR20
2 VCCA_SM_1

0.1U_0402_16V
AP20 VCCA_SM_2 1 1

C388

C387
AN20
AR17
AP17
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
POWER 2 2
+VCCP AN17
+1.05VS_A_SM VCCA_SM_6
100U_D2E_6.3VM_R15M~D

AT16 VCCA_SM_7
R50 AR16

A SM
VCCA_SM_8
C
1 2 AP16 VCCA_SM_9 C
22U_0805_6.3V6M~D

0_0805_5% 1
C82

1 1 1
+ C83 C72
C68

4.7U_0805_10V4Z
2 2 2 2 +1.05VS_MPLL +VCCP +1.5VS_TVDAC +1.5VS
1U_0603_10V4Z 26mA AP28 321.35mA L9 R64
VCCA_SM_CK_1
AN28 VCCA_SM_CK_2 VCC_AXF_1 B22 +V1.05VS_AXF 1 2 1 2

0.022U_0402_16V7K

UMA@

0.1U_0402_16V
0_0805_5% UMA@

UMA@ C115
AP25 B21

AXF
R71 +1.05VS_A_SM_CK VCCA_SM_CK_3 VCC_AXF_2 LQH32CNR15M33L_1210~D
AN25 VCCA_SM_CK_4 VCC_AXF_3 A21
1 2 AN24 VCCA_SM_CK_5 1 1

2
0.1U_0402_16V

0_0603_5% AM28 124mA


VCCA_SM_CK_NCTF_1
22U_0805_6.3V6M~D

0_0603_5%

C114
AM26
A CK
VCCA_SM_CK_NCTF_2
C104

R97
1 1 AM25 VCCA_SM_CK_NCTF_3 2 2
C123

+3VS_DAC_CRT AL25 VCCA_SM_CK_NCTF_4 VCC_SM_CK_1 BF21 +1.8V_SM_CK


AM24 BH20

SM CK

1
VCCA_SM_CK_NCTF_5 VCC_SM_CK_2
AL24 VCCA_SM_CK_NCTF_6 VCC_SM_CK_3 BG20
2 2
AM23 VCCA_SM_CK_NCTF_7 VCC_SM_CK_4 BF20 1 1
AL23 C63
TVA 24.15mA VCCA_SM_CK_NCTF_8 118.8mA C62
TVB 39.48mA 0.1U_0402_16V 22U_0805_6.3V6M~D +VCCP
2 2 +VCC_PEG
TVX 24.15mA VCC_TX_LVDS K47 +1.8V_TXLVDS
B24 PJP13
VCCA_TV_DAC_1 +3VS @ JUMP_43X79
+3VS_DAC_CRT A24 VCCA_TV_DAC_2 VCC_HV_1 C35

22U_0805_6.3V6M~D
TV

B35 105.3mA 1 1
VCC_HV_2 2 2
A35
HV

VCC_HV_3

4.7U_0805_10V4Z
1

0.1U_0402_16V
HDMI disable connected to GND 50mA A32 2 1
VCC_HDA
0.01U_0402_16V7K

0.1U_0402_16V

C389
HDA

V48 1732mA +
VCC_PEG_1 +VCC_PEG 1
+1.05VS_PEGPLL
C401 UMA@

C402 UMA@

C410

C95

220U_D2_4VY_R15M
1 1 U48 +VCCP
VCC_PEG_2 L12

C117
V47
PEG

VCC_PEG_3 2 1 2
VCC_PEG_4 U47 1 2
2
D TV/CRT

+1.5VS_TVDAC 58.67mA M25 U46


2 2 VCCD_TVDAC VCC_PEG_5 BLM21PG221SN1D_0805~D
B +1.5VS_QDAC 48.363mA L28 B
VCCD_QDAC
VCC_DMI_1 AH48 456mA +1.05VS_DMI

R138
+1.05VS_HPLL 157.2mA AF1 AF48
VCCD_HPLL VCC_DMI_2
AH47
DMI

50mA VCC_DMI_3
+1.05VS_PEGPLL AA47 VCCD_PEG_PLL VCC_DMI_4 AG47 +1.05VS_DMI
1_0402_5%~D +VCC_PEG
R112
C233 0.1U_0402_16V

2 60.31mA M38 20mils 1 2


VCCD_LVDS_1

0.1U_0402_16V

10U_0805_10V
LVDS

+1.8V_LVDS L37 A8 0_0603_5%


VCCD_LVDS_2 VTTLF1

0.1U_0402_16V
VTTLF2 L1 1 1

C176

C179
VTTLF

VTTLF3 AB2
1
1
0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

C116
2 2
1 1 1
C382

C385

C65

CANTIGA_1p0
2

2 2 2

C401 C405 C413 C174 U4 +1.8V_LVDS +1.8V_TXLVDS

+1.5VS_QDAC +1.5VS R110 UMA@ R350


L5 1 2 +1.8V 1 2 +1.8V

10U_0805_10V

1000P_0402_50V7K
0_0603_5% 0_0603_5%

10U_0805_10V
1 2 1 UMA@ 1 UMA@
1U_0402_6.3V6K~D

C187

C186

1U_0603_10V4Z

C414
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% CRESTLINE_1p0 UMA@ 1 1
0.1U_0402_16V

C418
VGA@ VGA@ VGA@ VGA@ VGA@
BLM18PG181SN1_0603~D
C98

1 1 2 2
2 UMA@ 2
C97

UMA@
A A
C407 C173 C115 C186
2 2

0_0402_5% 0_0402_5% 0_0402_5% 0_0603_5%


VGA@ VGA@ VGA@ VGA@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 10 of 48
5 4 3 2 1
5 4 3 2 1

+VCCP

U4G
Extnal Graphic: 1210.34mA 3000mA
integrated Graphic: 1930.4mA AP33 W28
VCC_SM_1 VCC_AXG_NCTF_1
AN33 VCC_SM_2 VCC_AXG_NCTF_2 V28

330U_D2_2.5VY_R15M

330U_D2_2.5VY_R15M
+1.8V BH32 VCC_SM_3 VCC_AXG_NCTF_3 W26
U4F BG32 VCC_SM_4 VCC_AXG_NCTF_4 V26 1 1 Layout Note:
+VCCP

22U_0805_6.3V6M~D

C165

22U_0805_6.3V6M~D

C147

0.1U_0402_10V7K~D

@ C86
BF32 VCC_SM_5 VCC_AXG_NCTF_5 W25

C57
1 BD32 VCC_SM_6 VCC_AXG_NCTF_6 V25 + + Place close to GMCH
1 1 2 BC32 VCC_SM_7 VCC_AXG_NCTF_7 W24
D
AG34 C148 + BB32 V24 D
VCC_1 VCC_SM_8 VCC_AXG_NCTF_8 2 2

C164
AC34 VCC_2 BA32 VCC_SM_9 VCC_AXG_NCTF_9 W23
AB34 330U_D2_2.5VY_R9M~D AY32 V23
VCC_3 2 2 2 1 VCC_SM_10 VCC_AXG_NCTF_10
AA34 VCC_4 AW32 VCC_SM_11 VCC_AXG_NCTF_11 AM21
Y34 VCC_5 AV32 VCC_SM_12 VCC_AXG_NCTF_12 AL21
V34 VCC_6 AU32 VCC_SM_13 VCC_AXG_NCTF_13 AK21
U34 VCC_7 AT32 VCC_SM_14 VCC_AXG_NCTF_14 W21
AM33 0317 change value AR32 V21
VCC_8 VCC_SM_15 VCC_AXG_NCTF_15

POWER
AK33 VCC_9 AP32 VCC_SM_16 VCC_AXG_NCTF_16 U21
AJ33 VCC_10 AN32 VCC_SM_17 VCC_AXG_NCTF_17 AM20
22U_0805_6.3V6M~D

0.22U_0402_10V

0.22U_0402_10V

0.1U_0402_16V
AG33 VCC_11 BH31 VCC_SM_18 VCC_AXG_NCTF_18 AK20
1 AF33 VCC_12 BG31 VCC_SM_19 VCC_AXG_NCTF_19 W20
220U_D2_4VY_R15M

1 1 1 1 BF31 VCC_SM_20 VCC_AXG_NCTF_20 U20


C118

C143

C119

+ C120
AE33 VCC_13 BG30 VCC_SM_21 VCC_AXG_NCTF_21 AM19
C374

VCC CORE
AC33 VCC_14 BH29 VCC_SM_22 VCC_AXG_NCTF_22 AL19
AA33 VCC_15 BG29 VCC_SM_23 VCC_AXG_NCTF_23 AK19
2 2 2 2 2
Y33 VCC_16 BF29 VCC_SM_24 VCC_AXG_NCTF_24 AJ19
W33 VCC_17 BD29 VCC_SM_25 VCC_AXG_NCTF_25 AH19

VCC SM
V33 VCC_18 BC29 VCC_SM_26 VCC_AXG_NCTF_26 AG19
U33 VCC_19 BB29 VCC_SM_27 VCC_AXG_NCTF_27 AF19
AH28 VCC_20 BA29 VCC_SM_28 VCC_AXG_NCTF_28 AE19
AF28 VCC_21 AY29 VCC_SM_29 VCC_AXG_NCTF_29 AB19
AC28 VCC_22 AW29 VCC_SM_30 VCC_AXG_NCTF_30 AA19
AA28 VCC_23 AV29 VCC_SM_31 VCC_AXG_NCTF_31 Y19
AJ26 VCC_24 AU29 VCC_SM_32 VCC_AXG_NCTF_32 W19
AG26 VCC_25 AT29 VCC_SM_33 VCC_AXG_NCTF_33 V19
AE26 VCC_26 AR29 VCC_SM_34 VCC_AXG_NCTF_34 U19
AC26 VCC_27 AP29 VCC_SM_35 VCC_AXG_NCTF_35 AM17
AH25 VCC_28 VCC_AXG_NCTF_36 AK17
AG25 VCC_29 BA36 VCC_SM_36/NC VCC_AXG_NCTF_37 AH17
AF25 VCC_30 BB24 VCC_SM_37/NC VCC_AXG_NCTF_38 AG17
AG24 VCC_31 BD16 VCC_SM_38/NC VCC_AXG_NCTF_39 AF17
C
AJ23 +VCCP BB21 AE17 C
VCC_32 +VCCP VCC_SM_39/NC VCC_AXG_NCTF_40
AH23 VCC_33 POWER AW16 VCC_SM_40/NC VCC_AXG_NCTF_41 AC17
AF23 VCC_34 AW13 VCC_SM_41/NC VCC_AXG_NCTF_42 AB17
VCC_NCTF_1 AM32 AT13 VCC_SM_42/NC VCC_AXG_NCTF_43 Y17
T32 VCC_35 VCC_NCTF_2 AL32 VCC_AXG_NCTF_44 W17
AK32 6326.84mA V17

VCC GFX NCTF


VCC_NCTF_3 VCC_AXG_NCTF_45
VCC_NCTF_4 AJ32 VCC_AXG_NCTF_46 AM16
VCC_NCTF_5 AH32 Y26 VCC_AXG_1 VCC_AXG_NCTF_47 AL16
VCC_NCTF_6 AG32 AE25 VCC_AXG_2 VCC_AXG_NCTF_48 AK16

0.47U_0402_16V4Z~D

1U_0603_10V4Z~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

10U_0805_10V

22U_0805_6.3VAM~D
VCC_NCTF_7 AE32 AB25 VCC_AXG_3 VCC_AXG_NCTF_49 AJ16
VCC_NCTF_8 AC32 AA25 VCC_AXG_4 VCC_AXG_NCTF_50 AH16
VCC_NCTF_9 AA32 1 1 1 1 1 1 AE24 VCC_AXG_5 VCC_AXG_NCTF_51 AG16
VCC_NCTF_10 Y32 AC24 VCC_AXG_6 VCC_AXG_NCTF_52 AF16

C99

C78

C66

C100

C79

C80
VCC_NCTF_11 W32 AA24 VCC_AXG_7 VCC_AXG_NCTF_53 AE16
VCC_NCTF_12 U32 Y24 VCC_AXG_8 VCC_AXG_NCTF_54 AC16
2 2 2 2 2 2
VCC_NCTF_13 AM30 AE23 VCC_AXG_9 VCC_AXG_NCTF_55 AB16
VCC_NCTF_14 AL30 AC23 VCC_AXG_10 VCC_AXG_NCTF_56 AA16
VCC_NCTF_15 AK30 AB23 VCC_AXG_11 VCC_AXG_NCTF_57 Y16
VCC_NCTF_16 AH30 AA23 VCC_AXG_12 VCC_AXG_NCTF_58 W16
VCC_NCTF_17 AG30 AJ21 VCC_AXG_13 VCC_AXG_NCTF_59 V16
VCC_NCTF_18 AF30 AG21 VCC_AXG_14 VCC_AXG_NCTF_60 U16
VCC_NCTF_19 AE30 AE21 VCC_AXG_15
VCC_NCTF_20 AC30 Layout Note: Inside GMCH AC21 VCC_AXG_16
VCC_NCTF_21 AB30 cavity for VCC_AXG. AA21 VCC_AXG_17
VCC_NCTF_22 AA30 Y21 VCC_AXG_18
VCC_NCTF_23 Y30 AH20 VCC_AXG_19
VCC_NCTF_24 W30 AF20 VCC_AXG_20
VCC NCTF

VCC_NCTF_25 V30 AE20 VCC_AXG_21


VCC_NCTF_26 U30 AC20 VCC_AXG_22
VCC_NCTF_27 AL29 AB20 VCC_AXG_23
VCC_NCTF_28 AK29 AA20 VCC_AXG_24
VCC_NCTF_29 AJ29 T17 VCC_AXG_25
B B
VCC_NCTF_30 AH29 T16 VCC_AXG_26
VCC_NCTF_31 AG29 AM15 VCC_AXG_27
VCC_NCTF_32 AE29 AL15 VCC_AXG_28
VCC_NCTF_33 AC29 AE15 VCC_AXG_29
VCC_NCTF_34 AA29 AJ15 VCC_AXG_30
VCC_NCTF_35 Y29 AH15 VCC_AXG_31
VCC_NCTF_36 W29 AG15 VCC_AXG_32
VCC_NCTF_37 V29 AF15 VCC_AXG_33
VCC_NCTF_38 AL28 AB15 VCC_AXG_34
VCC_NCTF_39 AK28 AA15 VCC_AXG_35

VCC GFX
VCC_NCTF_40 AL26 Y15 VCC_AXG_36
VCC_NCTF_41 AK26 V15 VCC_AXG_37
VCC_NCTF_42 AK25 U15 VCC_AXG_38
VCC_NCTF_43 AK24 AN14 VCC_AXG_39
VCC_NCTF_44 AK23 AM14 VCC_AXG_40
U14 VCC_AXG_41 VCC_SM_LF1 AV44 VCCSM_LF1

VCC SM LF
T14 VCC_AXG_42 VCC_SM_LF2 BA37 VCCSM_LF2
VCC_SM_LF3 AM40 VCCSM_LF3
VCC_SM_LF4 AV21 VCCSM_LF4
VCC_SM_LF5 AY5 VCCSM_LF5
VCC_SM_LF6 AM10 VCCSM_LF6
CANTIGA_1p0
VCC_SM_LF7 BB13 VCCSM_LF7

C70

C71

C67

C81

C146

C145

C163
1 1 1 1 1 1 1

PAD T42 AJ14 VCC_AXG_SENSE

0.1U_0402_16V

0.1U_0402_16V
PAD T43 AH14 VSS_AXG_SENSE 2 2 2 2 2 2 2

0.22U_0603_10V7K

0.22U_0603_10V7K

0.47U_0402_6.3V6K

1U_0603_10V4Z

1U_0603_10V4Z
A A

CANTIGA_1p0

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 11 of 48
5 4 3 2 1 hexainf@hotmail.com
5 4 3 2 1

U4J
U4I BG21 AH8
VSS_199 VSS_297
L12 VSS_200 VSS_298 Y8
AU48 VSS_1 VSS_100 AM36 AW21 VSS_201 VSS_299 L8
AR48 VSS_2 VSS_101 AE36 AU21 VSS_202 VSS_300 E8
AL48 VSS_3 VSS_102 P36 AP21 VSS_203 VSS_301 B8
BB47 VSS_4 VSS_103 L36 AN21 VSS_204 VSS_302 AY7
AW47 VSS_5 VSS_104 J36 AH21 VSS_205 VSS_303 AU7
AN47 VSS_6 VSS_105 F36 AF21 VSS_206 VSS_304 AN7
AJ47 VSS_7 VSS_106 B36 AB21 VSS_207 VSS_305 AJ7
AF47 VSS_8 VSS_107 AH35 R21 VSS_208 VSS_306 AE7
D D
AD47 VSS_9 VSS_108 AA35 M21 VSS_209 VSS_307 AA7
AB47 VSS_10 VSS_109 Y35 J21 VSS_210 VSS_308 N7
Y47 VSS_11 VSS_110 U35 G21 VSS_211 VSS_309 J7
T47 VSS_12 VSS_111 T35 BC20 VSS_212 VSS_310 BG6
N47 VSS_13 VSS_112 BF34 BA20 VSS_213 VSS_311 BD6
L47 VSS_14 VSS_113 AM34 AW20 VSS_214 VSS_312 AV6
G47 VSS_15 VSS_114 AJ34 AT20 VSS_215 VSS_313 AT6
BD46 VSS_16 VSS_115 AF34 AJ20 VSS_216 VSS_314 AM6
BA46 VSS_17 VSS_116 AE34 AG20 VSS_217 VSS_315 M6
AY46 VSS_18 VSS_117 W34 Y20 VSS_218 VSS_316 C6
AV46 VSS_19 VSS_118 B34 N20 VSS_219 VSS_317 BA5
AR46 VSS_20 VSS_119 A34 K20 VSS_220 VSS_318 AH5
AM46 VSS_21 VSS_120 BG33 F20 VSS_221 VSS_319 AD5
V46 VSS_22 VSS_121 BC33 C20 VSS_222 VSS_320 Y5
R46 VSS_23 VSS_122 BA33 A20 VSS_223 VSS_321 L5
P46 VSS_24 VSS_123 AV33 BG19 VSS_224 VSS_322 J5
H46 VSS_25 VSS_124 AR33 A18 VSS_225 VSS_323 H5
F46 VSS_26 VSS_125 AL33 BG17 VSS_226 VSS_324 F5
BF44 VSS_27 VSS_126 AH33 BC17 VSS_227 VSS_325 BE4
AH44 VSS_28 VSS_127 AB33 AW17 VSS_228
AD44 P33 AT17 BC3
AA44
Y44
VSS_29
VSS_30
VSS_31
VSS_128
VSS_129
VSS_130
L33
H33
R17
M17
VSS_229
VSS_230
VSS_231
VSS VSS_327
VSS_328
VSS_329
AV3
AL3
U44 VSS_32 VSS_131 N32 H17 VSS_232 VSS_330 R3
T44 K32 C17 P3
M44
F44
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
F32
C32 BA16
VSS_233

VSS_235
VSS_331
VSS_332
VSS_333
F3
BA2
BC43 VSS_36 VSS_135 A31 VSS_334 AW2
AV43 VSS_37 VSS_136 AN29 AU16 VSS_237 VSS_335 AU2
AU43 VSS_38 VSS_137 T29 AN16 VSS_238 VSS_336 AR2
AM43 VSS_39 VSS_138 N29 N16 VSS_239 VSS_337 AP2
J43 VSS_40 VSS_139 K29 K16 VSS_240 VSS_338 AJ2
C C
C43 VSS_41 VSS_140 H29 G16 VSS_241 VSS_339 AH2
BG42 VSS_42 VSS_141 F29 E16 VSS_242 VSS_340 AF2
AY42 VSS_43 VSS_142 A29 BG15 VSS_243 VSS_341 AE2
AT42 VSS_44 VSS_143 BG28 AC15 VSS_244 VSS_342 AD2
AN42 VSS_45 VSS_144 BD28 W15 VSS_245 VSS_343 AC2
AJ42 VSS_46 VSS_145 BA28 A15 VSS_246 VSS_344 Y2
AE42 VSS_47 VSS_146 AV28 BG14 VSS_247 VSS_345 M2
N42 VSS_48 VSS_147 AT28 AA14 VSS_248 VSS_346 K2
L42 VSS_49 VSS_148 AR28 C14 VSS_249 VSS_347 AM1
BD41 VSS_50 VSS_149 AJ28 BG13 VSS_250 VSS_348 AA1
AU41 VSS_51 VSS_150 AG28 BC13 VSS_251 VSS_349 P1
AM41 VSS_52 VSS_151 AE28 BA13 VSS_252 VSS_350 H1
AH41 VSS_53 VSS_152 AB28
AD41 VSS_54 VSS_153 Y28 VSS_351 U24
AA41 VSS_55 VSS_154 P28 AN13 VSS_255 VSS_352 U28
Y41 VSS_56 VSS_155 K28 AJ13 VSS_256 VSS_353 U25
U41 VSS_57 VSS_156 H28 AE13 VSS_257 VSS_354 U29
T41 VSS_58 VSS_157 F28 N13 VSS_258
M41 VSS_59 VSS_158 C28 L13 VSS_259
G41 VSS_60 VSS_159 BF26 G13 VSS_260 VSS_NCTF_1 AF32
B41 VSS_61 VSS_160 AH26 E13 VSS_261 VSS_NCTF_2 AB32
BG40 VSS_62 VSS_161 AF26 BF12 VSS_262 VSS_NCTF_3 V32
BB40 VSS_63 VSS_162 AB26 AV12 VSS_263 VSS_NCTF_4 AJ30
AV40 VSS_64 VSS_163 AA26 AT12 VSS_264 VSS_NCTF_5 AM29
AN40 VSS_65 VSS_164 C26 AM12 VSS_265 VSS_NCTF_6 AF29
H40 B26 AA12 AB29

VSS NCTF
VSS_66 VSS_165 VSS_266 VSS_NCTF_7
E40 VSS_67 VSS_166 BH25 J12 VSS_267 VSS_NCTF_8 U26
AT39 VSS_68 VSS_167 BD25 A12 VSS_268 VSS_NCTF_9 U23
AM39 VSS_69 VSS_168 BB25 BD11 VSS_269 VSS_NCTF_10 AL20
AJ39 VSS_70 VSS_169 AV25 BB11 VSS_270 VSS_NCTF_11 V20
AE39 VSS_71 VSS_170 AR25 AY11 VSS_271 VSS_NCTF_12 AC19
N39 VSS_72 VSS_171 AJ25 AN11 VSS_272 VSS_NCTF_13 AL17
B B
L39 VSS_73 VSS_172 AC25 AH11 VSS_273 VSS_NCTF_14 AJ17
B39 VSS_74 VSS_173 Y25 VSS_NCTF_15 AA17
BH38 VSS_75 VSS_174 N25 Y11 VSS_275 VSS_NCTF_16 U17
BC38 VSS_76 VSS_175 L25 N11 VSS_276
BA38 VSS_77 VSS_176 J25 G11 VSS_277
AU38 G25 C11 BH48

VSS SCB
VSS_78 VSS_177 VSS_278 VSS_SCB_1
AH38 VSS_79 VSS_178 E25 BG10 VSS_279 VSS_SCB_2 BH1
AD38 VSS_80 VSS_179 BF24 AV10 VSS_280 VSS_SCB_3 A48
AA38 VSS_81 VSS_180 AD12 AT10 VSS_281 VSS_SCB_4 C1
Y38 VSS_82 VSS_181 AY24 AJ10 VSS_282 VSS_SCB_5 A3
U38 VSS_83 VSS_182 AT24 AE10 VSS_283
T38 VSS_84 VSS_183 AJ24 AA10 VSS_284 NC_26 E1
J38 VSS_85 VSS_184 AH24 M10 VSS_285 NC_27 D2
F38 VSS_86 VSS_185 AF24 BF9 VSS_286 NC_28 C3
C38 VSS_87 VSS_186 AB24 BC9 VSS_287 NC_29 B4
BF37 VSS_88 VSS_187 R24 AN9 VSS_288 NC_30 A5
BB37 VSS_89 VSS_188 L24 AM9 VSS_289 NC_31 A6
AW37 VSS_90 VSS_189 K24 AD9 VSS_290 NC_32 A43
AT37 VSS_91 VSS_190 J24 G9 VSS_291 NC_33 A44
AN37 G24 B9 B45

NC
VSS_92 VSS_191 VSS_292 NC_34
AJ37 VSS_93 VSS_192 F24 BH8 VSS_293 NC_35 C46
H37 VSS_94 VSS_193 E24 BB8 VSS_294 NC_36 D47
C37 VSS_95 VSS_194 BH23 AV8 VSS_295 NC_37 B47
BG36 VSS_96 VSS_195 AG23 AT8 VSS_296 NC_38 A46
BD36 VSS_97 VSS_196 Y23 NC_39 F48
AK15 VSS_98 VSS_197 B23 NC_40 E48
AU36 VSS_99 VSS_198 A23 NC_41 C48
VSS_199 AJ6 NC_42 B48

CANTIGA_1p0 CANTIGA_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 12 of 48
5 4 3 2 1
5 4 3 2 1

Close to VREF pins of SO-DIMM


+1.8V
+V_DDR_MCH_REF 7,14
JDIM2
8 DDR_A_DQS#[0..7]

2.2U_0805_16V4Z

0.1U_0402_16V
1 VREF VSS 2
8 DDR_A_D[0..63] 3 4 DDR_A_D5 1 1
VSS DQ4

C201

C220
DDR_A_D4 5 6 DDR_A_D0
DDR_A_D1 DQ0 DQ5
8 DDR_A_DM[0..7] 7 DQ1 VSS 8
9 10 DDR_A_DM0
DDR_A_DQS#0 VSS DM0 2 2
8 DDR_A_DQS[0..7] 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D6
DQS0 DQ6 DDR_A_D7
8 DDR_A_MA[0..13] 15 VSS DQ7 16
DDR_A_D2 17 18
DDR_A_D3 DQ2 VSS DDR_A_D13
19 DQ3 DQ12 20
D DDR_A_D12 D
21 VSS DQ13 22
DDR_A_D8 23 24
DDR_A_D9 DQ8 VSS DDR_A_DM1
Layout Note: 25 DQ9 DM1 26
27 VSS VSS 28
Place near JDIM1 DDR_A_DQS#1 29 30 M_CLK_DDR0
M_CLK_DDR0 7
DDR_A_DQS1 DQS1# CK0 M_CLK_DDR#0
31 DQS1 CK0# 32 M_CLK_DDR#0 7
33 VSS VSS 34
DDR_A_D14 35 36 DDR_A_D11
DDR_A_D15 DQ10 DQ14 DDR_A_D10
37 DQ11 DQ15 38
39 VSS VSS 40

+1.8V 41 42
DDR_A_D16 VSS VSS DDR_A_D20
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D21
DQ17 DQ21
47 VSS VSS 48
2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

330U 2.5V Y D2
1 DDR_A_DQS#2 49 50
DQS2# NC PM_EXTTS#0 7
1 1 1 1 1 1 1 1 1 DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
C105

C124

C149

C166

C169

C154

C131

C130

C108

C84
+ 53 54
DDR_A_D18 VSS VSS DDR_A_D23
55 DQ18 DQ22 56
@ DDR_A_D19 57 58 DDR_A_D22
2 2 2 2 2 2 2 2 2 2 DQ19 DQ23
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28
DDR_A_D24 DQ24 DQ28 DDR_A_D25
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76
Layout Note: DDR_CKE0_DIMMA
77 VSS VSS 78
DDR_CKE1_DIMMA
7 DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA 7
C Place one cap close to every 2 pullup 81 82 C
VDD VDD
resistors terminated to +0.9V 83 NC NC/A15 84
DDR_A_BS#2 85 86 DDR_A_MA14
8 DDR_A_BS#2 BA2 NC/A14 DDR_A_MA14 8
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
91 A9 A7 92
DDR_A_MA8 93 94 DDR_A_MA6
A8 A6
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 8
DDR_A_BS#0 107 108 DDR_A_RAS#
+0.9VS 8 DDR_A_BS#0 BA0 RAS# DDR_A_RAS# 8
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
8 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 7
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
8 DDR_A_CAS# CAS# ODT0 M_ODT0 7
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
7 DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

7 M_ODT1 M_ODT1 119 120


NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_D37 123 124 DDR_A_D32
DDR_A_D36 DQ32 DQ36 DDR_A_D33
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
C106

C125

C126

C127

C150

C151

C167

C107

C128

C129

C152

C153

C168

133 134 DDR_A_D39


DDR_A_D35 VSS DQ38 DDR_A_D38
135 DQ34 DQ39 136
DDR_A_D34 137 138
DQ35 VSS DDR_A_D45
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D47
DDR_A_D44 DQ40 DQ45
143 DQ41 VSS 144
B DDR_A_DQS#5 B
145 VSS DQS5# 146
DDR_A_DM5 147 148 DDR_A_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_A_D41 151 152 DDR_A_D43
DDR_A_D46 DQ42 DQ46 DDR_A_D42
Layout Note: 153 DQ43 DQ47 154
Place these resistor 155 VSS VSS 156
DDR_A_D49 157 158 DDR_A_D52
closely JP41,all DDR_A_D48 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
trace length Max=1.5" 161 VSS VSS 162
163 164 M_CLK_DDR1
NC,TEST CK1 M_CLK_DDR1 7
165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 7
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
+0.9VS 171 172
DDR_A_D54 VSS VSS DDR_A_D51
173 DQ50 DQ54 174
DDR_A_D50 175 176 DDR_A_D55
DQ51 DQ55
177 VSS VSS 178
DDR_A_D61 179 180 DDR_A_D57
RP14 RP22 56_0404_4P2R_5% DDR_A_D60 DQ56 DQ60 DDR_A_D56
181 DQ57 DQ61 182
DDR_A_MA5 1 4 4 1 DDR_A_MA12 183 184
DDR_A_MA8 VSS VSS
2 3 3 2 DDR_CKE0_DIMMA DDR_A_DM7 185 DM7 DQS7# 186 DDR_A_DQS#7
187 188 DDR_A_DQS7
RP13 56_0404_4P2R_5% RP17 56_0404_4P2R_5% DDR_A_D59 VSS DQS7
189 DQ58 VSS 190
DDR_A_MA1 1 4 4 1 DDR_A_MA7 DDR_A_D58 191 192 DDR_A_D62
DDR_A_MA3 DQ59 DQ62
2 3 3 2 DDR_A_MA6 193 VSS DQ63 194 DDR_A_D63
ICH_SM_DA 195 196
14,15,19 ICH_SM_DA SDA VSS
RP7 56_0404_4P2R_5% RP15 56_0404_4P2R_5% ICH_SM_CLK 197 198
14,15,19 ICH_SM_CLK SCL SA0
DDR_A_RAS# 1 4 4 1 DDR_A_MA9 199 200
+3VS VDDSPD SA1
DDR_CS0_DIMMA# 2 3 3 2 DDR_A_BS#2 1

1
10K_0402_5%

10K_0402_5%
1 1
RP6 56_0404_4P2R_5% RP16 56_0404_4P2R_5% C58 C59 FOX_ASOA426-M2RN-7F
R31

R32
DDR_A_BS#0 1 4 4 1 DDR_A_MA4
A DDR_A_MA10 2 3 3 2 DDR_A_MA2 0.1U_0402_16V
2 2
2.2U_0603_6.3V6K SO-DIMM A A

REVERSE
2

2
RP5 56_0404_4P2R_5% RP8 56_0404_4P2R_5%
DDR_A_CAS# 1 4 4 1 DDR_A_MA0
DDR_A_WE# 2 3 3 2 DDR_A_BS#1
Bottom side
RP1 56_0404_4P2R_5% RP2 56_0404_4P2R_5%
DDR_CS1_DIMMA# 2 3 4 1 M_ODT0
M_ODT1 1 4 3 2 DDR_A_MA13
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title
56_0404_4P2R_5% RP23 56_0404_4P2R_5%
DDR_CKE1_DIMMA 1 2 4 1 DDR_A_MA14 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
R96 56_0402_5% 3 2 DDR_A_MA11 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 13 of 48
5 4 3 2 1 hexainf@hotmail.com
5 4 3 2 1

Close to VREF pins of SO-DIMM


+1.8V

8 DDR_B_DQS#[0..7] +V_DDR_MCH_REF 7,13

8 DDR_B_D[0..63] JDIM1

2.2U_0805_16V4Z

0.1U_0402_16V
1 VREF VSS 2
3 4 DDR_B_D5 1 1
8 DDR_B_DM[0..7] DDR_B_D0 VSS DQ4 DDR_B_D4
5 DQ0 DQ5 6

C221

C222
DDR_B_D1 7 8
8 DDR_B_DQS[0..7] DQ1 VSS
9 10 DDR_B_DM0
DDR_B_DQS#0 VSS DM0 2 2
8 DDR_B_MA[0..13] 11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
DDR_B_D2 17 18
D DDR_B_D3 DQ2 VSS DDR_B_D12 D
Layout Note: 19 DQ3 DQ12 20
DDR_B_D13
21 VSS DQ13 22
Place near JDIM2 DDR_B_D8 23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR2
DQS1# CK0 M_CLK_DDR2 7
DDR_B_DQS1 31 32 M_CLK_DDR#2
DQS1 CK0# M_CLK_DDR#2 7
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS

41 VSS VSS 42
2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

330U 2.5V Y D2
1 DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C112

C139

C160

C138

C177

C109

C132

C133

C155

C189
+ 47 48
DDR_B_DQS#2 VSS VSS
49 DQS2# NC 50 PM_EXTTS#1 7
@ DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D28 61 62 DDR_B_D29
DDR_B_D25 DQ24 DQ28 DDR_B_D24
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
Layout Note: DDR_B_D30
71 VSS VSS 72
DDR_B_D26
73 DQ26 DQ30 74
Place one cap close to every 2 pullup DDR_B_D31 75 76 DDR_B_D27
DQ27 DQ31
C
resistors terminated to +0.9VS DDR_CKE2_DIMMB
77 VSS VSS 78
DDR_CKE3_DIMMB C
7 DDR_CKE2_DIMMB 79 CKE0 NC/CKE1 80 DDR_CKE3_DIMMB 7
81 VDD VDD 82
83 NC NC/A15 84
DDR_B_BS#2 85 86 DDR_B_MA14
8 DDR_B_BS#2 BA2 NC/A14 DDR_B_MA14 8
87 VDD VDD 88
DDR_B_MA12 89 90 DDR_B_MA11
DDR_B_MA9 A12 A11 DDR_B_MA7
91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
+0.9VS A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1
A10/AP BA1 DDR_B_BS#1 8
DDR_B_BS#0 107 108 DDR_B_RAS#
8 DDR_B_BS#0 BA0 RAS# DDR_B_RAS# 8
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
8 DDR_B_WE# WE# S0# DDR_CS2_DIMMB# 7
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
8 DDR_B_CAS# CAS# ODT0 M_ODT2 7
0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

DDR_CS3_DIMMB# 115 116 DDR_B_MA13


7 DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
1 1 1 1 1 1 1 1 1 1 1 1 1 1 M_ODT3 119 120
7 M_ODT3 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
2 2 2 2 2 2 2 2 2 2 2 2 2 2
127 VSS VSS 128
C110

C134

C135

C156

C157

C170

C171

C111

C136

C158

C137

C172

C159

C199

DDR_B_DQS#4 129 130 DDR_B_DM4


DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D39
DDR_B_D34 VSS DQ38 DDR_B_D38
135 DQ34 DQ39 136
DDR_B_D35 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
DDR_B_D40 141 142 DDR_B_D45
B DDR_B_D41 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_B_DQS#5
DDR_B_DM5 VSS DQS5# DDR_B_DQS5
Layout Note: 147 DM5 DQS5 148
Place these resistor 149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
closely JP42,all DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
trace length Max=1.5" 155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR3
NC,TEST CK1 M_CLK_DDR3 7
165 166 M_CLK_DDR#3
+0.9VS DDR_B_DQS#6 VSS CK1# M_CLK_DDR#3 7
167 DQS6# VSS 168
DDR_B_DQS6 169 170 DDR_B_DM6
DQS6 DM6
171 VSS VSS 172
DDR_B_D51 173 174 DDR_B_D54
RP18 RP24 56_0404_4P2R_5% DDR_B_D50 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
DDR_B_MA3 1 4 4 1 DDR_B_MA12 177 178
DDR_B_MA1 DDR_B_MA9 DDR_B_D56 VSS VSS DDR_B_D60
2 3 3 2 179 DQ56 DQ60 180
DDR_B_D61 181 182 DDR_B_D57
RP10 56_0404_4P2R_5% RP26 56_0404_4P2R_5% DQ57 DQ61
183 VSS VSS 184
DDR_B_BS#0 1 4 4 1 DDR_B_MA14 DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_B_MA10 DDR_B_MA11 DM7 DQS7# DDR_B_DQS7
2 3 3 2 187 VSS DQS7 188
DDR_B_D59 189 190
RP12 56_0404_4P2R_5% RP19 56_0404_4P2R_5% DDR_B_D58 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
DDR_B_MA0 1 4 4 1 DDR_B_MA5 193 194 DDR_B_D63
DDR_B_BS#1 DDR_B_MA8 ICH_SM_DA VSS DQ63
2 3 3 2 13,15,19 ICH_SM_DA 195 SDA VSS 196
ICH_SM_CLK 197 198 R33
13,15,19 ICH_SM_CLK SCL SAO
RP11 56_0404_4P2R_5% RP21 56_0404_4P2R_5% 199 200 1 2 +3VS
+3VS VDDSPD SA1
DDR_B_RAS# 1 4 4 1 DDR_B_MA7

1
10K_0402_5%
DDR_CS2_DIMMB# 2 3 3 2 DDR_B_MA6 1 1 10K_0402_5%

R34
C61 C60 FOX_AS0A426-NARN-7F~N
A RP9 56_0404_4P2R_5% RP20 56_0404_4P2R_5% A
DDR_B_CAS#
DDR_B_WE#
1 4 4 1 DDR_B_MA4
DDR_B_MA2
0.1U_0402_16V
2 2
2.2U_0603_6.3V6K SO-DIMM B
2 3 3 2
REVERSE
2

RP3
56_0404_4P2R_5% RP4 56_0404_4P2R_5%
DDR_CS3_DIMMB# 2 3 4 1 DDR_B_MA13 Bottom side
M_ODT3 1 4 3 2 M_ODT2

56_0404_4P2R_5% RP25 Security Classification Compal Secret Data Compal Electronics, Inc.
4 1 DDR_B_BS#2 2007/1/15 2008/1/15 Title
DDR_CKE3_DIMMB 1 DDR_CKE2_DIMMB
Issued Date Deciphered Date
2 3 2
R335 56_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
56_0404_4P2R_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 14 of 48
5 4 3 2 1
5 4 3 2 1

+3VS_CK505

FSC FSB FSA CPU SRC PCI REF DOT_96 USB Routing the trace at least 10mil R971
1 2
+3VS
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz CLK_XTAL_OUT 0_0805_5% 1
C1189
1
C1190
1
C1191
1
C1192
1
C1193
1
C1194
1
C1195
CLK_XTAL_IN
*

2
0_0402_5%
0 0 0 266 100 33.3 14.318 96.0 48.0 2
10U_0805_10V
2
0.1U_0402_16V
2
0.1U_0402_16V
2
0.1U_0402_16V
2
0.1U_0402_16V
2
0.1U_0402_16V
2
0.1U_0402_16V

R986
0 0 1 133 100 33.3 14.318 96.0 48.0 14.31818MHZ_16P
Y7 0905 Connect to +VCCP

1
+VCCP +1.05VS_CK505
0 1 0 200 100 33.3 14.318 96.0 48.0 2 1
Place close to U55
D
0 1 1 166 100 33.3 14.318 96.0 48.0 2 2 R972 D
1 2 0.1U_0402_16V 10U_0805_10V 0.1U_0402_16V
C1196 C1197 0_0805_5% 1 1 1 1 1 1 1
1 0 0 333 100 33.3 14.318 96.0 48.0 22P_0402_50V8J
1 1
22P_0402_50V8J C1198 C1199 C1200 C1201 C1202 C1203 C1204

+1.05VS_CK505 2 2 2 2 2 2 2
1 0 1 100 100 33.3 14.318 96.0 48.0
10U_0805_10V 0.1U_0402_16V 0.1U_0402_16V 0.1U_0402_16V

1 1 0 400 100 33.3 14.318 96.0 48.0


+3VS_CK505
1 1 1 Reserved
MEDIA_REQ#32
MEDIA_REQ#32 30
R1020 1 2 0_0402_5% Card Bus
CLK_PCIE_MEDIA 30
R1025 1 2 0_0402_5% CLK_PCIE_MEDIA# 30

R976 1 2 0_0402_5% R_MCH_BCLK# R_CLKREQ#_EXPCARD R977 1 2 0_0402_5%


7 CLK_MCH_BCLK# EXPCARD_REQ#16 26
NB R978 1 2 0_0402_5% R_MCH_BCLK R_PCIE_EXPR R979 1 2 0_0402_5% Express Card
7 CLK_MCH_BCLK CLK_PCIE_EXPR 26
R980 2 1 0_0402_5% R_CPU_BCLK# R_PCIE_EXPR# R981 1 2 0_0402_5%
4 CLK_CPU_BCLK# CLK_PCIE_EXPR# 26
R983 CPU R982 2 1 0_0402_5% R_CPU_BCLK
4 CLK_CPU_BCLK
FSA 1 2 1 2 +3VS_CK505
MCH_CLKSEL0 7
2.2K_0402_5% R984
1K_0402_5%

73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
5 CPU_BSEL0
U55
+3VS_CK505 +1.05VS_CK505

SRC_8/CPU_ITP
GND
VDD_CPU

CPU_0#
VSS_CPU

CPU_1#
VDD_CPU_IO

VDD_SRC_IO

VDD_SRC
CPU_0

CPU_1

CLKREQ_7#

SRC_8#/CPU_ITP#

SRC_7
SRC_7#
VSS_SRC
CLKREQ_6#
SRC_6
SRC_6#
C C
R_CKPWRGD 1 54 H_STP_PCI#
19 CK_PWRGD CKPWRGD/PD# PCI_STOP# H_STP_PCI# 19
CPU_BSEL1 2 53 H_STP_CPU# CPU_STP
FS_B/TEST_MODE CPU_STOP# H_STP_CPU# 19
3 VSS_REF VDD_SRC_IO 52
CLK_XTAL_OUT 4 51
CLK_XTAL_IN XTAL_OUT SRC_10#
5 XTAL_IN SRC_10 50
6 VDD_REF CLKREQ_10# 49
R991 1 2 33_0402_1% FSC 7 48 R_PCIE_SATA R992 1 2 0_0402_5%
19 CLK_14M_ICH REF_0/FS_C/TEST_ SRC_11 CLK_PCIE_SATA 18
PAD T120 8 47 R_PCIE_SATA# R994 1 2 0_0402_5% ICH_SATA
REF_1 SRC_11# CLK_PCIE_SATA# 18
13,14,19 ICH_SM_DA ICH_SM_DA 9 46 R_CLKSATAREQ# R995 1 2475_0402_1%~D
SDA CLKREQ_11# CLKSATAREQ# 19
13,14,19 ICH_SM_CLK ICH_SM_CLK 10 45 R_CLK_PCIE_LAN# R996 1 2 0_0402_5%
SCL SRC_9# CLK_PCIE_LAN# 21
11 44 R_CLK_PCIE_LAN R997 1 2 0_0402_5% GLAN
NC SRC_9 CLK_PCIE_LAN 21
CPU_BSEL1 1 2 12 43 R_CLKREQ#_GLAN
MCH_CLKSEL1 7 VDD_PCI CLKREQ_9# GLAN_REQ#9 21
R998 13 42
1K_0402_5% R1001 33_0402_1% PCI2_TME PCI_1 VSS_SRC R1002 1
1 2 14 PCI_2 CLKREQ_4# 41 2 0_0402_5% WLAN_REQ#4 23
23 CLK_DEBUG_PORT R1004 33_0402_1% R_CLK_PCI_EC R_CLK_PCIE_MCARD# R1005 1
5 CPU_BSEL1 1 2 15 PCI_3 SRC_4# 40 2 0_0402_5% CLK_PCIE_MCARD# 23
27 CLK_PCI_EC R1006 33_0402_1% 27_SEL R_CLK_PCIE_MCARD R1007 1
25 CLK_PCI_TPM 1 2 16 PCI_4/SEL_LCDCL SRC_4 39 2 0_0402_5% CLK_PCIE_MCARD 23 MiniCard_WLAN

USB_1/CLKREQ_A#
R1008 1 2 33_0402_1% ITP_EN 17 38
17 PCI_CLK

LCDCLK#/27M_SS
PCIF_5/ITP_EN VDD_SRC_IO

SRC_0#/DOT_96#
18 VSS_PCI CLKREQ_3# 37

SRC_0/DOT_96

VDD_PLL3_IO
LCDCLK/27M
USB_0/FS_A

VDD_PLL3

VSS_PLL3

VSS_SRC
VDD_48

SRC_2#

SRC_3#
VDD_IO
VSS_48

VSS_IO

SRC_2

SRC_3
S IC ICS9LPRS387AKLFT MLF 72P CLK GEN

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
+3VS_CK505
R_PCIE_ICH# R1010 1 2 0_0402_5%
CLK_PCIE_ICH# 19
R_PCIE_ICH R1012 1 2 0_0402_5% ICH
CLK_PCIE_ICH 19
R1013 1 2 33_0402_1% FSA
19 CLK_48M_ICH
B R1016 R_CLKREQ#_7 R_MCH_3GPLL# R1015 1 0_0402_5% B
7 CLKREQ#_7 1 2 2 CLK_MCH_3GPLL# 7
FSC 1 2 1 2 R1014 475_0402_1%~D +1.05VS_CK505 R_MCH_3GPLL R1018 1 2 0_0402_5% NB_3GPLL
MCH_CLKSEL2 7 CLK_MCH_3GPLL 7
10K_0402_5% R1017 +1.05VS_CK505
1K_0402_5% R1019 UMA@2 1 0_0402_5% R_MCH_DREFCLK
7 CLK_MCH_DREFCLK
NB (UMA) R1021 UMA@2 1 0_0402_5% R_MCH_DREFCLK# SSCDREFCLK# UMA@ R1022 1 2 0_0402_5%
5 CPU_BSEL2 7 CLK_MCH_DREFCLK# MCH_SSCDREFCLK# 7
SSCDREFCLK UMA@ R1023 1 2 0_0402_5%
MCH_SSCDREFCLK 7 NB_SSC (UMA)
R1024 VGA@2 1 0_0402_5%
31 CLK_PCIE_VGA
VGA (Discrete) R1026 VGA@2 1 0_0402_5% VGA@ R1067 1 2 33_0402_1%
31 CLK_PCIE_VGA# CLK_NVSS_27M 31
VGA@ R1195 1 2 33_0402_1% CLK_NV_27M 31 VGA_27M (DIS)

+3VS
0 = SRC8/SRC8#
ITP_EN * 1 = ITP/ITP#
0 = Enable DOT96 & SRC1(UMA)
27_SEL
1 = Enable SRC0 & 27MHz(DIS) EXPCARD_REQ#16 1 2
R90 10K_0402_5%
0 = Overclocking of CPU and SRC Allowed MEDIA_REQ#32 1 2
PCI2_TME R91 10K_0402_5%

*1 = Overclocking of CPU and SRC NOT allowed CLKSATAREQ# 1 2


R88 10K_0402_5%
GLAN_REQ#9 1 2
+3VS_CK505 +3VS_CK505 R87 10K_0402_5%
WLAN_REQ#4 1 2
R85 10K_0402_5%
1

VGA@ CLKREQ#_7 1 2
R1030 R1031 R60 10K_0402_5%
A 10K_0402_5% A
10K_0402_5%
2

ITP_EN 27_SEL PCI2_TME


1

UMA@
R1032
10K_0402_5%
R1033
10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

SCHEMATIC, M/B LA-4232P


2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 15 of 48
5 4 3 2 1 hexainf@hotmail.com
A B C D E

+5VS +CRT_VCC

CRT F7 @
+5VS_CRTVCC
W=40mils
D17 W=40mils
1 2 2 1

VGA@ 1.1A_6VDC_FUSE RB411DT146 SOT23


31 VGA_CRT_R 2 1 1 1

0.1U_0402_16V
R613 0_0402_5% 1 2

C346
VGA@ L26 0_1206_5% C344
2 1 0.1U_0402_16V
31 VGA_CRT_G 2 2 +CRT_VCC +CRT_VCC +3VS +3VS +3VS
R614 0_0402_5%
VGA@ @
31 VGA_CRT_B 2 1

2
R615 0_0402_5% 27 MSEN#

2K_0402_5%

2K_0402_5%
R12 R9 R13 R10

2.2K_0402_5%

2.2K_0402_5%
UMA@ JCRT1
1 2 1 CRT_R_C 1 2 CRT_R_L 6 1
9 CRT_R
R619 0_0402_5% L2 11

1
UMA@ BK1608LL121-T 0603 1
2 1 CRT_G_C 1 2 CRT_G_L 7
9 CRT_G

2
R620 0_0402_5% L3 Q3

G
12
UMA@ BK1608LL121-T 0603 2 UMA@
2 1 CRT_B_C 1 2 CRT_B_L 8 VGA_DDC_DATA_C 1 3 2 1
9 CRT_B 3VDDCDA 9
R621 0_0402_5% L4 13 R628 0_0402_5%

S
22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

2
150_0402_1%

150_0402_1%

150_0402_1%
1 BK1608LL121-T 0603

G
1 1 3
1

1
@ @ @ 1 1 1 DDC_MD2 9 SSM3K7002FU_SC70-3 UMA@
For EMI
R2

R7

R8
C9 C8 C6 14 16 VGA_DDC_CLK_C 1 3 2 1 3VDDCCL 9
C1 C2 C3 4 17 R629 0_0402_5%

S
2 2 2
10
2 2 2
15
2

2 Q1
1 5 VGA@
4.7P_0402_50V8C 4.7P_0402_50V8C 4.7P_0402_50V8C C345 SSM3K7002FU_SC70-3

100P_0402_50V8J
2 1 VGA_DDCDATA 31
SUYIN_070549FR015S200ZR R624 0_0402_5%
+CRT_VCC HSYNC_L VGA@
1 2 CONN@
L25 0_0603_5% 2
2 1 VGA_DDCCLK 31
1 2 2 1 1 VGA_DDC_DATA_C R625 0_0402_5%
C18 0.1U_0402_16V R319 10K_0402_5% 1 2 VSYNC_L C349
L24 0_0603_5% 1
5
1

100P_0402_50V8J

100P_0402_50V8J
UMA@ 2
1 1
P
OE#

CRT_HSYNC 1 2CRT_HSYNC_B 2 4 D_CRT_HSYNC C7 VGA_DDC_CLK_C


9 CRT_HSYNC A Y
R336 30_0402_5% C348 C347 @2
G

U5

15P_0402_50V8J

15P_0402_50V8J
VGA@ 74AHCT1G125GW_SOT353-5 2 2
3

2 1 @1
31 VGA_HSYNC +CRT_VCC
R631 0_0402_5%
VGA@

100P_0402_50V8J
2 1 1 2 C4
31 VGA_VSYNC 2
R632 0_0402_5% C17 0.1U_0402_16V
5
1

UMA@
P
OE#

2 2
CRT_VSYNC 1 2CRT_VSYNC_B 2 4 D_CRT_VSYNC
9 CRT_VSYNC A Y
R337 30_0402_5%
G

U6
74AHCT1G125GW_SOT353-5
3

Close to GMCH Close to VGA

LVDSAC+ UMA@ R508 1 2 0_0402_5% GMCH_LVDSAC+


LCD +LCDVDD +5VALW
W=60mils
+3VS +3VS
LVDSAC- UMA@ R510

LVDSA0+ UMA@ R544


1 2 0_0402_5%

0_0402_5%
GMCH_LVDSAC-

GMCH_LVDSA0+
GMCH_LVDSAC+ 9
GMCH_LVDSAC- 9
1 2
2

GMCH_LVDSA0+ 9
100_0603_1%

47K_0402_5%

LVDSA0- UMA@ R570 1 2 0_0402_5% GMCH_LVDSA0-


GMCH_LVDSA0- 9
R134

R136

EC_ENBKL
27 EC_ENBKL

1
LVDSA1+ UMA@ R595 1 2 0_0402_5% GMCH_LVDSA1+
R21 LVDSA1- UMA@ R596 1 2 0_0402_5% GMCH_LVDSA1- GMCH_LVDSA1+ 9
GMCH_LVDSA1- 9
1 1

D26 4.7K_0402_5% LVDSA2+ UMA@ R597 1 2 0_0402_5% GMCH_LVDSA2+


3

D S
SI2301BDS-T1-E3 1P SOT23 CH751H-40_SC76 LVDSA2- UMA@ R598 0_0402_5% GMCH_LVDSA2- GMCH_LVDSA2+ 9
1 2

2
GMCH_LVDSA2- 9
G
Q7 2 2 1 2 Q6 BKOFF# 1 2 DISPOFF#
27 BKOFF#
2N7002LT1G_SOT23 G R114 1K_0402_5% W=60mils D25
R15 S @ CH751H-40_SC76
3

1 7.3 +LCDVDD 2 R655 1 EC_ENBKL 1 2 EDID_CLK_LCD UMA@ R599 1 2 0_0402_5% GMCH_EDID_CLK_LCD


D 9 GMCH_ENBKL GMCH_EDID_CLK_LCD 9
UMA@ 0_0402_5% EDID_DAT_LCD UMA@ R600 1 2 0_0402_5% GMCH_EDID_DAT_LCD
GMCH_EDID_DAT_LCD 9
1

C196 +LCDVDD
1

D
SSM3K7002FU_SC70-3
2
2 1 1 31 G7X_ENBKL 2 R651 1 R652 R652
100K_0402_5% G Q9 C198 C46 VGA@ 0_0402_5% 2.2K_0402_5%
1

UMA@ S 0.047U_0402_16V7K VGA@


3
10K_0402_5%

4.7U_0805_10V4Z 0.1U_0402_16V
2 2 D3
R15

D9
9 GMCH_LVDDEN GMCH_LVDDEN 2 1 VGA@ INVT_PWM 2
3 CH751H-40PT_SOD323-2 UMA@ 1 100K_0402_5% 3
2

D8 3 UMA@
31 VGA_LVDDEN VGA_LVDDEN 2 1
CH751H-40PT_SOD323-2 VGA@
PJSOT24C_SOT23-3 VGA_LVDSAC+ R630 0_0402_5% VGA@ LVDSAC+
1 2
LCD_VCC_TEST_EN 2 R662 1 @ 31 VGA_LVDSAC+ VGA_LVDSAC- R633 1 2 0_0402_5% VGA@ LVDSAC-
27 LCD_VCC_TEST_EN 31 VGA_LVDSAC-
0_0402_5%
VGA_LVDSA0+ R634 1 2 0_0402_5% VGA@LVDSA0+
31 VGA_LVDSA0+ VGA_LVDSA0- R635 1 2 0_0402_5% VGA@ LVDSA0-
31 VGA_LVDSA0-
DISPOFF# INVT_PWM DAC_BRIG LCD_CBL_DET# JP4 VGA_LVDSA1+ R601 1 2 0_0402_5% VGA@ LVDSA1+
1 2 31 VGA_LVDSA1+ VGA_LVDSA1- R602 1 2 0_0402_5% VGA@ LVDSA1-
+LCDVDD 1 2 +LCDVDD 31 VGA_LVDSA1-
+3VS 3 4 LCD_CBL_DET#
3 4 LCD_CBL_DET# 27
@1 @1 @1 @1 EDID_CLK_LCD 5 6 LCD_TST VGA_LVDSA2+ R603 1 2 0_0402_5% VGA@ LVDSA2+
5 6 LCD_TST 27 31 VGA_LVDSA2+
LVDSA0- 7 8 EDID_DAT_LCD VGA_LVDSA2- R604 1 2 0_0402_5% VGA@ LVDSA2-
7 8 LVDSA0+ 31 VGA_LVDSA2-
100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

9 9 10 10
C14 C15 C19 C20 LVDSA1+ 11 12 LVDSA1-
2 2 2 2 LVDSA2- 11 12
13 13 14 14
15 16 LVDSA2+
LVDSAC+ 15 16 LVDSAC-
17 17 18 18
19 20 VGA_CLK_LCD R644 1 2 0_0402_5% VGA@ EDID_CLK_LCD
19 20 31 VGA_CLK_LCD
21 22 MIC_SIG VGA_DAT_LCD R645 1 2 0_0402_5% VGA@ EDID_DAT_LCD
21 22 MIC_SIG 24 31 VGA_DAT_LCD
MIC_CLK 23 24 +3VS
24 MIC_CLK 23 24
near JP4.38 near JP4.35 near JP4.37 near JP4.4 MIC_DIAG 25 26
27 MIC_DIAG 25 26
27 27 28 28 +5VS
19 USB20_N1 29 29 30 30 USB20_P1 19
EC_SMB_CK2_2R 31 32
+INVPWR_B+ 31 32 EC_SMB_DA2_2R R19
33 33 34 34
INVT_PWM 35 36 +INVPWR_B+ 1 2 +B+
27 INVT_PWM 35 36
MIC_SIG MIC_CLK DAC_BRIG 37 38 DISPOFF# 0_0805_5%
+3VS +5VS 27 DAC_BRIG 37 38
39 39 40 40
41 42
22P_0402_50V8J

22P_0402_50V8J

GND GND
1000P_0402_50V7K~N

1 1 2 2
1 1 ACES_88242-4001~N C32 C34
C40 C41
4 4
C140 @ @ C38 0.1U_0603_50V4Z 0.1U_0603_50V4Z
2 2 @ EC_SMB_CK2 1 1
4,27,31 EC_SMB_CK2 2 R658 1 EC_SMB_CK2_2R
2 @ 2 @ 0_0402_5%

4,27,31 EC_SMB_DA2 EC_SMB_DA2 2 R659 1 EC_SMB_DA2_2R


0.1U_0402_16V @ 0_0402_5%

near JP4.25 near JP4.27


near JP4.11 near JP4.33 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 16 of 48
A B C D E
5 4 3 2 1

+3VS

R1035 1 2 8.2K_0402_5% PCI_DEVSEL#

R1036 1 2 8.2K_0402_5% PCI_STOP#

R1037 1 2 8.2K_0402_5% PCI_TRDY#

R1038 1 2 8.2K_0402_5% PCI_FRAME# U56B


D11 F1 PCI_REQ0#
R1039 1 AD0 REQ0#
2 8.2K_0402_5% PCI_PLOCK# C8 AD1 PCI GNT0# G4 PCI_GNT0#
D PCI_REQ1# D
D9 AD2 REQ1#/GPIO50 B6
R1040 1 2 8.2K_0402_5% PCI_IRDY# E12 A7
AD3 GNT1#/GPIO51 PCI_REQ2#
E9 AD4 REQ2#/GPIO52 F13
R1041 1 2 8.2K_0402_5% PCI_SERR# C9 F12
AD5 GNT2#/GPIO53 PCI_REQ3#
E10 AD6 REQ3#/GPIO54 E6
R1042 1 2 8.2K_0402_5% PCI_PERR# B7 F6 PCI_GNT3#
AD7 GNT3#/GPIO55
C7 AD8
C5 AD9 C/BE0# D8
G11 AD10 C/BE1# B4
F8 AD11 C/BE2# D6
F11 AD12 C/BE3# A5
E7 AD13
A3 D3 PCI_IRDY#
+3VS AD14 IRDY#
D2 AD15 PAR E3
F10 R1 PCI_PCIRST#
AD16 PCIRST# PCI_DEVSEL#
D5 AD17 DEVSEL# C6
R1043 1 2 8.2K_0402_5% PCI_PIRQA# D10 E4 PCI_PERR#
AD18 PERR# PCI_PLOCK#
B3 AD19 PLOCK# C2
R1044 1 2 8.2K_0402_5% PCI_PIRQB# F7 J4 PCI_SERR#
AD20 SERR# PCI_STOP#
C3 AD21 STOP# A4
R1045 1 2 8.2K_0402_5% PCI_PIRQC# F3 F5 PCI_TRDY#
AD22 TRDY# PCI_FRAME#
F4 AD23 FRAME# D7
R1046 1 2 8.2K_0402_5% PCI_PIRQD# C1 AD24 PCI_PLTRST#
G7 AD25 PLTRST# C14
R1047 1 2 8.2K_0402_5% PCI_PIRQE# H7 D4 PCI_CLK
AD26 PCICLK PCI_CLK 15
D1 AD27 PME# R2 EC_PME# 21,23,26,27
R1048 1 2 8.2K_0402_5% PCI_PIRQF# G5 AD28
H6 AD29
R1049 1 2 8.2K_0402_5% PCI_PIRQG# G1 AD30
H3 AD31
R1050 2 1 8.2K_0402_5% PCI_PIRQH#

C PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE# C
PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
E1 PIRQB# PIRQF#/GPIO3 K6
R1051 1 2 8.2K_0402_5% PCI_REQ0# PCI_PIRQC# J6 F2 PCI_PIRQG#
PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH#
C4 PIRQD# PIRQH#/GPIO5 G2
R1052 1 2 8.2K_0402_5% PCI_REQ1#
ICH9M REV 1.0
R1053 1 2 8.2K_0402_5% PCI_REQ2#

R1054 1 2 8.2K_0402_5% PCI_REQ3#

+3VALW

1
@
C101
0.1U_0402_16V4Z
2

5
@ U9
PCI_PCIRST# 2

P
B PCI_RST#
Y 4 PCI_RST# 21,23,25,26
1 A

G
MC74VHC1G08DFT2G SC70 5P

3
R1094
0_0402_5%
A16 swap override Strap Boot BIOS Strap 2 1
B B
Low= A16 swap override Enble
PCI_GNT3# High= Default* PCI_GNT0# SPI_CS#1 Boot BIOS Location

@R1055
@R1055 0 1 SPI +3VALW
PCI_GNT3# 1 2
1K_0402_5%

1 0 PCI @
1
C87
0.1U_0402_16V4Z
2
1 1 LPC *

5
@ U58
PCI_PLTRST# 2

P
+3VALW B PLT_RST#
Y 4 PLT_RST# 7,27,30,31
1 A

G
@ R1058
SPI_CS1#_R 1 2 MC74VHC1G08DFT2G SC70 5P
19 SPI_CS1#_R

3
1K_0402_5%
@ R1060 R1061
PCI_GNT0# 1 2 0_0402_5%
1K_0402_5% 2 1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 17 of 48
5 4 3 2 1 hexainf@hotmail.com
5 4 3 2 1

+RTCVCC
+3VS

1 2 SM_INTRUDER# R1063
R1062 1M_0402_5% GATEA20 1 2
1 2 LAN100_SLP 10K_0402_5%
R1064 332K_0402_1%~D
1 2 ICH_INTVRMEN R1066
R1065 332K_0402_1%~D KB_RST# 1 2
10K_0402_5%

D D

+RTCVCC

U56A LPC_AD[0..3] 23,25,27


1 2
R1068 20K_0402_5% ICH_RTCX1 C23 K5 LPC_AD0
ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_AD1
1 2 C24 RTCX2 FWH1/LAD1 K4
R1109 20K_0402_5% L6 LPC_AD2
ICH_RTCRST# FWH2/LAD2 LPC_AD3
A25 RTCRST# FWH3/LAD3 K2
SRTCRST#

RTC
LPC
F20 SRTCRST#
SM_INTRUDER# C22 K3 LPC_FRAME#
INTRUDER# FWH4/LFRAME# LPC_FRAME# 23,25,27
1 1 +VCCP

2
C1220 C1210 ICH_INTVRMEN B22 J3 LPC_DRQ0# T121 PAD
JOPEN2 JOPEN1 LAN100_SLP INTVRMEN LDRQ0#
A22 LAN100_SLP LDRQ1#/GPIO23 J1 T122 PAD
1U_0603_10V4Z @ 1U_0603_10V4Z @

2
2 2 GATEA20
E25 GLAN_CLK A20GATE N7 GATEA20 27
AJ27 H_A20M# R1070
A20M# H_A20M# 4
C13 56_0402_5%
LAN_RSTSYNC H_DPRSTP_R# R1071 H_DPRSTP#
DPRSTP# AJ25 1 2 H_DPRSTP# 5,7,44
F14 AE23 H_DPSLP# 0_0402_5%

LAN / GLAN
H_DPSLP# 5

1
LAN_RXD0 DPSLP#
G13 LAN_RXD1
D14 AJ26 R_H_FERR# R1072 1 2 H_FERR#
LAN_RXD2 FERR# H_FERR# 4
56_0402_5%
D13 AD22 H_PWRGOOD 3/28 add 56ohm
LAN_TXD0 CPUPWRGD H_PWRGOOD 5
D12 LAN_TXD1
E13 AF25 H_IGNNE#
LAN_TXD2 IGNNE# H_IGNNE# 4
within 2" from R1557

CPU
+1.5VS B10 AE22 H_INIT#
GPIO56 INIT# H_INIT# 4 +VCCP
AG25 H_INTR
C INTR H_INTR 4 C
B28 L3 KB_RST#
GLAN_COMPI RCIN# KB_RST# 27
R1073 24.9_0402_1% 1 2 GLAN_COMP B27 GLAN_COMPO

1
AF23 H_NMI
NMI H_NMI 4
R1074 33_0402_5% 1 2 HDA_BITCLK AF6 AF24 H_SMI# R1075
24 ACZ_BITCLK HDA_BIT_CLK SMI# H_SMI# 4
R1076 33_0402_5% 1 2 HDA_SYNC AH4 56_0402_5%
24 ACZ_SYNC HDA_SYNC
AH27 H_STPCLK#
STPCLK# H_STPCLK# 4
R1077 33_0402_5% 1 2 HDARST# AE7
24 ACZ_RST#

2
HDA_RST# THRMTRIP_ICH# R1078
THRMTRIP# AG26 1 2 54.9_0402_1% H_THERMTRIP# 4,7
HDA_SDIN0 AF4
24 ADC_ACZ_SDIN0 HDA_SDIN0
AG4 HDA_SDIN1 TP12 AG27

IHDA
AH3 HDA_SDIN2
AE5 HDA_SDIN3
SATA4RXN AH11
R1079 33_0402_5% 1 2 HDA_SDOUT AG5 AJ11
24 ACZ_SDOUT HDA_SDOUT SATA4RXP
SATA4TXN AG12
PAD T123 AG7 HDA_DOCK_EN#/GPIO33 SATA4TXP AF12
+3VS 1 2 PAD T124 AE8 HDA_DOCK_RST#/GPIO34
R1080 10K_0402_5% AH9
SATA_LED# SATA5RXN
28 SATA_LED# AG8 SATALED# SATA5RXP AJ9
SATA5TXN AE10
22 PSATA_IRX_DTX_N0_C AJ16 SATA0RXN SATA5TXP AF10
0.01U_0402_16V7K AH16
22 PSATA_IRX_DTX_P0_C

SATA
SATA0RXP
HDD 22 PSATA_ITX_DRX_N0
PSATA_ITX_DRX_N0C1213 1
PSATA_ITX_DRX_P0C1214 1
2
2
PSATA_ITX_DRX_N0_C AF17
PSATA_ITX_DRX_P0_C AG17 SATA0TXN SATA_CLKN AH18
AJ18
CLK_PCIE_SATA#
CLK_PCIE_SATA
CLK_PCIE_SATA# 15
22 PSATA_ITX_DRX_P0 SATA0TXP SATA_CLKP CLK_PCIE_SATA 15
0.01U_0402_16V7K AH13 AJ7
22 ODD_IRX_DTX_N0_C SATA1RXN SATARBIAS#
0.01U_0402_16V7K AJ13 AH7 R1081 1 2
22 ODD_IRX_DTX_P0_C SATA1RXP SATARBIAS
ODD 22 ODD_ITX_DRX_N0
ODD_ITX_DRX_N0 C1215 1
ODD_ITX_DRX_P0 1
2 ODD_ITX_DRX_N0_C
2 ODD_ITX_DRX_P0_C
AG14
AF14
SATA1TXN 24.9_0402_1%
22 ODD_ITX_DRX_P0 SATA1TXP
C1216 Within 500 mils
0.01U_0402_16V7K ICH9M REV 1.0

B B

+3VS

@ R1082
1 2 ACZ_SDOUT ICH_RTCX1
1K_0402_5%
R1069
1 2 2 1 ICH_RTCX2
@ R1083 R985 0_0402_5%
1 2 ICH_RSVD 10M_0402_5%
ICH_RSVD 19
1K_0402_5% 1 1
C1211 C1212
10P_0402_50V8J~D 12P_0402_50V8J~D
2 2
XOR CHAIN ENTRANCE STRAP:RSVD
1

XOR Chain Entrance Strap Y8


IN

OUT

32.768KHZ_12.5PF_1TJS125BJ4A421P

ICH_RSVD_TP3 HDA SDOUT Description


NC

NC

A
0 0 RSVD A
2

0 1 Enter XOR Chain

1 0 Normal Operation (Default)


Security Classification Compal Secret Data Compal Electronics, Inc.
1 1 Set PCIE port config bit 1 Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 18 of 48
5 4 3 2 1
5 4 3 2 1

+3VS 1 2 SERIRQ Place closely pin AF3 Place closely pin H1


R1084 10K_0402_5% +3VALW R1085 1 2 2.2K_0402_5%
1 2 PCI_CLKRUN# R1087 1 2 2.2K_0402_5%
R1086 8.2K_0402_5% U56C CLK_48M_ICH CLK_14M_ICH
1 2 EC_THERM# ICH_SMBCLK G16 AH23 GPIO21 1 2 +3VS
26 ICH_SMBCLK SMBCLK SATA0GP/GPIO21
@ R1088 8.2K_0402_5% ICH_SMBDATA A13 AF19 GPIO19 R1089 8.2K_0402_5%
26 ICH_SMBDATA SMBDATA SATA1GP/GPIO19

1
1 2 OCP# CL_RST#1 E17 AE21 GPIO36 @ @

SATA
GPIO
ME_EC_CLK1 LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36

SMB
R1090 10K_0402_5% C17 AD20 GPIO37 R1091 R1092
SMLINK0 SATA5GP/GPIO37
1 2 LAN_CABDT ME_EC_DATA1 B18 SMLINK1
R311 10K_0402_5% H1 CLK_14M_ICH 10_0402_5% 10_0402_5%
CLK14 CLK_14M_ICH 15
ICH_RI# F19 AF3 CLK_48M_ICH

Clocks
CLK_48M_ICH 15

2
RI# CLK48
1 2 EC_SCI# PAD T125 SUS_STAT# R4 P1 ICH_SUSCLK T126 PAD 1 @ 1 @
@ R1095 8.2K_0402_5% XDP_DBRESET# SUS_STAT#/LPCPD# SUSCLK C1217 C1218
4 XDP_DBRESET# G19 SYS_RESET#
C16 SLP_S3#
D SLP_S3# SLP_S3# 27 D
ICH8 don't have PM_BMBUSY# M6 E16 SLP_S4# 4.7P_0402_50V8C 4.7P_0402_50V8C
7 PM_BMBUSY# PMSYNC#/GPIO0 SLP_S4# SLP_S4# 27 2 2
G17 SLP_S5#
SLP_S5# SLP_S5# 27
27 EC_LID_OUT# EC_LID_OUT# A17 SMBALERT#/GPIO11 R695 100_0402_5%
S4_STATE#/GPIO26 C10 T127 PAD
H_STP_PCI# A14 1 2 M_PWROK
15 H_STP_PCI# STP_PCI#
R_STP_CPU# ICH_PWROK

SYS GPIO
15 H_STP_CPU# E19 STP_CPU# PWROK G20 ICH_PWROK 7,27
+3VS 1 2SB_SPKR 1 2
R1096 @ 10K_0402_5% PCI_CLKRUN# L4 M2 R1097 10K_0402_5%
25,27 PCI_CLKRUN# CLKRUN# DPRSLPVR/GPIO16 DPRSLPVR 7,44
low-->default
ICH_PCIE_WAKE# E20 B13 ICH_LOW_BAT#

Power MGT
27 ICH_PCIE_WAKE# WAKE# BATLOW#
High -->No boot 25,27 SERIRQ
SERIRQ M5 SERIRQ
EC_THERM# AJ23 R3 PWRBTN_OUT#
27 EC_THERM# THRM# PWRBTN# PBTN_OUT# 27

7,27,44 VGATE 1 2 VRMPWRGD D21 VRMPWRGD LAN_RST# D20


R1099 0_0402_5%
+3VS 1 2 GPIO49 1 2 PAD T128 A20 D22 R_EC_RSMRST# R_EC_RSMRST# R1104
1 2 10K_0402_5%
R1101
@ 10K_0402_5% R1102 100K_0402_5% TP11 RSMRST#
@ 4 OCP# OCP# AG19 R5 CK_PWRGD_R R1105 1 2 0_0402_5%
GPIO1 CK_PWRGD CK_PWRGD 15
LAN_LOPWEN AH21
21 LAN_LOPWEN GPIO6
checklist pull hi AG21 R6 M_PWROK
GPIO7 CLPWROK M_PWROK 7
27 EC_SMI# EC_SMI# A21
EC_SCI# GPIO8 +3VS
27 EC_SCI# C12 GPIO12 SLP_M# B16 T129 PAD
PAD T130 C21 GPIO13
AE18 F24 CL_CLK0 R1106
GPIO17 CL_CLK0 CL_CLK0 7
K1 B19 0.1U_0402_16V 1 2
for test point need GPIO18 CL_CLK1 3.24K_0402_1%
T49 AF8 GPIO20

1
AJ22 F22 CL_DATA0 1
SCLOCK/GPIO22 CL_DATA0 CL_DATA0 7
PAD T131 A9 C19 C1219 R1107

GPIO
Controller Link
GPIO27 CL_DATA1 453_0402_1%
PAD T132 D19 GPIO28
CLKSATAREQ# L1 C25 CL_VREF0_ICH
15 CLKSATAREQ# SATACLKREQ#/GPIO35 CL_VREF0 2 NA lead free
AE19 A19

2
SLOAD/GPIO38 CL_VREF1
AG22 SDATAOUT0/GPIO39
C CL_RST# C
AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST# 7
GPIO49 AH24 D18
CL_RST#1 GPIO49 CL_RST1#
+3VALW 1 2 A8 GPIO57/CLGPIO5
R1108 10K_0402_5% A16
ICH_LOW_BAT# SB_SPKR MEM_LED/GPIO24
1 2 24 SB_SPKR M7 SPKR GPIO10/SUS_PWR_ACK C18
R1110 8.2K_0402_5% MCH_ICH_SYNC# AJ24 C11
7 MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT ACIN 27,38,39
1 2 ICH_PCIE_WAKE# ICH_RSVD B21 C20 1 2LAN_CABDT LAN_CABDT 21
18 ICH_RSVD TP3 WOL_EN/GPIO9
R1111 1K_0402_5%

MISC
PAD T133 AH20 TP8
1 2 ICH_RI# PAD T134 AJ20 @ 0_0402_5% R657
R1113 10K_0402_5% TP9
PAD T135 AJ21 TP10
1 2 XDP_DBRESET#
R1114 10K_0402_5%
1 2 ME_EC_CLK1
ICH9M REV 1.0
RSMRST circuit
R1115 10K_0402_5% U56D
1 2 ME_EC_DATA1 N29 V27 DMI_MTX_IRX_N0 DMI_MTX_IRX_N0 7 R1103 @ R656
R1116 10K_0402_5% PERN1 DMI0RXN DMI_MTX_IRX_P0 0_0402_5% 0_0402_5%
N28 PERP1 DMI0RXP V26 DMI_MTX_IRX_P0 7

Direct Media Interface


1 2 EC_LID_OUT# P27 U29 DMI_MRX_ITX_N0 DMI_MRX_ITX_N0 7 1 2 1 2 POK 40
PETN1 DMI0TXN 27 EC_RSMRST#
R1117 10K_0402_5% P26 U28 DMI_MRX_ITX_P0 DMI_MRX_ITX_P0 7
PETP1 DMI0TXP
GLAN_RXN L29 Y27 DMI_MTX_IRX_N1 DMI_MTX_IRX_N1 7 R_EC_RSMRST#
21 GLAN_RXN PERN2 DMI1RXN
GLAN_RXP L28 Y26 DMI_MTX_IRX_P1 DMI_MTX_IRX_P1 7
21 GLAN_RXP PERP2 DMI1RXP
GLAN 0.1U_0402_16V 2 1 C1227
GLAN_TXN_C M27 W29 DMI_MRX_ITX_N1 DMI_MRX_ITX_N1 7
21 GLAN_TXN PETN2 DMI1TXN
1 2 EC_SMI# 0.1U_0402_16V 2 1 C1228
GLAN_TXP_C M26 W28 DMI_MRX_ITX_P1 DMI_MRX_ITX_P1 7
21 GLAN_TXP PETP2 DMI1TXP
R1119 8.2K_0402_5%
PCIE_RXN3 J29 AB27 DMI_MTX_IRX_N2 DMI_MTX_IRX_N2 7
23 PCIE_RXN3 PERN3 DMI2RXN
PCIE_RXP3 J28 AB26 DMI_MTX_IRX_P2 DMI_MTX_IRX_P2 7
23 PCIE_RXP3 PERP3 DMI2RXP

PCI-Express
WLAN 23 PCIE_TXN3 0.1U_0402_16V 2 1 C1223PCIE_C_TXN3 K27 AA29 DMI_MRX_ITX_N2 DMI_MRX_ITX_N2 7
0.1U_0402_16V PETN3 DMI2TXN
23 PCIE_TXP3 2 1 C1224PCIE_C_TXP3 K26 PETP3 DMI2TXP AA28 DMI_MRX_ITX_P2 DMI_MRX_ITX_P2 7
PCIE_RXN4 G29 AD27 DMI_MTX_IRX_N3 DMI_MTX_IRX_N3 7
26 PCIE_RXN4 PERN4 DMI3RXN
PCIE_RXP4 G28 AD26 DMI_MTX_IRX_P3 DMI_MTX_IRX_P3 7
26 PCIE_RXP4 PERP4 DMI3RXP
Express Card 26 PCIE_TXN4 0.1U_0402_16V 2 1 C1225PCIE_C_TXN4 H27 PETN4 DMI3TXN AC29 DMI_MRX_ITX_N3 DMI_MRX_ITX_N3 7
B +3VS 0.1U_0402_16V 2 1 C1226PCIE_C_TXP4 H26 AC28 DMI_MRX_ITX_P3 B
26 PCIE_TXP4 PETP4 DMI3TXP DMI_MRX_ITX_P3 7
E29 T26 CLK_PCIE_ICH#
30 PCIE_RXN5 PERN5 DMI_CLKN CLK_PCIE_ICH# 15
E28 T25 CLK_PCIE_ICH
30 PCIE_RXP5 PERP5 DMI_CLKP CLK_PCIE_ICH 15
1

2.2K_0402_5% CardBus 30 PCIE_TXN5


0.1U_0402_16V 2 1 C1307 F27 PETN5
2.2K_0402_5% R1123 R1124
30 PCIE_TXP5
0.1U_0402_16V 2 1 C1306 F26 PETP5 DMI_ZCOMP AF29 R1120 24.9_0402_1% Within 500 mils
AF28 DMI_IRCOMP 1 2 +1.5VS
Q106 DMI_IRCOMP
C29 PERN6/GLAN_RXN
SSM3K7002FU_SC70-3 C28 AC5 USB20_N0
USB20_N0 29
2

PERP6/GLAN_RXP USBP0N
S

3 1 ICH_SMBDATA ICH_SMBDATA 26 D27 AC4 USB20_P0 USB0


13,14,15 ICH_SM_DA PETN6/GLAN_TXN USBP0P USB20_P0 29
D26 AD3 USB20_N1
PETP6/GLAN_TXP USBP1N USB20_N1 16
S

13,14,15 ICH_SM_CLK 3 1ICH_SMBCLK ICH_SMBCLK 26 USBP1P AD2 USB20_P1


USB20_P1 16 Camera
USB20_N2
G

D23 AC1 USB20_N2 29


2

SPI_CLK USBP2N USB20_P2


Q107 SPI_CS1#_R
D24 SPI_CS0# USBP2P AC2
USB20_N3
USB20_P2 29 USB1
G

17 SPI_CS1#_R F23 AA5 USB20_N3 29


2

SSM3K7002FU_SC70-3 SPI_CS1#/GPIO58/CLGPIO6 USBP3N USB20_P3


+3VS USBP3P AA4
USB20_N4
USB20_P3 29 Felica
D25 SPI_MOSI USBP4N AB2 USB20_N4 29
SPI

E23 AB3 USB20_P4 BlueTooth


SPI_MISO USBP4P USB20_P4 29
AA1 USB20_N5
USBP5N USB20_N5 29
USB_OC#0 N4 AA2 USB20_P5 FingerPrinter
29 USB_OC#0 OC0#/GPIO59 USBP5P USB20_P5 29
USB_OC#1 N5 W5 USB20_N6
OC1#/GPIO40 USBP6N USB20_N6 23
USB_OC#2 USB20_P6
29 USB_OC#2
USB_OC#3
N6
P6
OC2#/GPIO41 USBP6P USB W4
Y3 USB20_N7
USB20_P6 23 Mini Card
OC3#/GPIO42 USBP7N USB20_N7 26
EC_SWI# 1 2 USB_OC#4 M1 Y2 USB20_P7 Express Card
+3VALW OC4#/GPIO43 USBP7P USB20_P7 26
USB_OC#1 R22 1 2 10K_0402_5% USB_OC#5 N2 W1 USB20_N8
OC5#/GPIO29 USBP8N USB20_N8 29
USB_OC#2 R20 1 2 10K_0402_5% EC_SWI# M4 W2 USB20_P8 USB2
27 EC_SWI# OC6#/GPIO30 USBP8P USB20_P8 29
USB_OC#4 R14 1 2 10K_0402_5% USB_OC#7 M3 V2 USB20_N9
OC7#/GPIO31 USBP9N USB20_N9 29
R6 10K_0402_5% USB_OC#8_9 N3 V3 USB20_P9 USB3
29 USB_OC#8_9 OC8#/GPIO44 USBP9P USB20_P9 29
USB_OC#8_9 N1 U5
USB_OC#10 OC9#/GPIO45 USBP10N
P5 OC10#/GPIO46 USBP10P U4
USB_OC#11 P3 U1
USB_OC#7 OC11#/GPIO47 USBP11N
1 2 USBP11P U2
A USB_OC#8_9 R48 1 A
2 10K_0402_5% USBRBIAS AG2 USBRBIAS
USB_OC#0 R47 1 2 10K_0402_5% AG1 USBRBIAS#
1

R37 10K_0402_5% Within 500 mils ICH9M REV 1.0


R1125
22.6_0402_1%
2

USB_OC#3 1 2
USB_OC#5 R89 1
USB_OC#10 R56 1
2 10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
2 10K_0402_5% Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
USB_OC#11 R52 1 2 10K_0402_5%
R51 10K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 19 of 48
5 4 3 2 1 hexainf@hotmail.com
5 4 3 2 1

+RTCVCC +VCCP U56E


20 mils G3: 6uA U56F 1634mA AA26 VSS[1] VSS[107] H5
A23 VCCRTC VCC1_05[1] A15 AA27 VSS[2] VSS[108] J23

1U_0603_10V4Z~D
0.1U_0402_16V

0.1U_0402_16V
VCC1_05[2] B15 AA3 VSS[3] VSS[109] J26
1 1 1 +ICH_V5REF_RUN 2mA A6 C15 0.1U_0402_16V 0.1U_0402_16V AA6 J27
V5REF VCC1_05[3] VSS[4] VSS[110]

C1229

C1230
VCC1_05[4] D15 1 1 AB1 VSS[5] VSS[111] AC22

C1231
+ICH_V5REF_SUS 2mA AE1 E15 C1232 C1233 AA23 K28
V5REF_SUS VCC1_05[5] VSS[6] VSS[112]
VCC1_05[6] F15 AB28 VSS[7] VSS[113] K29
2 2 2
AA24 VCC1_5_B[1] VCC1_05[7] L11 AB29 VSS[8] VSS[114] L13
2 2
AA25 VCC1_5_B[2] VCC1_05[8] L12 AB4 VSS[9] VSS[115] L15
AB24 VCC1_5_B[3] VCC1_05[9] L14 AB5 VSS[10] VSS[116] L2
AB25 L16 L97 AC17 L26
VCC1_5_B[4] VCC1_05[10] VSS[11] VSS[117]
L96 40 mils AC24 VCC1_5_B[5] VCC1_05[11] L17 BLM18PG181SN1_0603~D AC26 VSS[12] VSS[118] L27
+1.5VS 1 2 +1.5VS_VCC1_5 22U_0805_6.3V6M~D 646mA AC25 L18 0.01U_0402_16V7K 1 2 +1.5VS AC27 L5
BLM21PG600SN1D_0805~D VCC1_5_B[6] VCC1_05[12] VSS[13] VSS[119]
1 AD24 VCC1_5_B[7] VCC1_05[13] M11 AC3 VSS[14] VSS[120] L7
D D
1 1 1 AD25 VCC1_5_B[8] VCC1_05[14] M18 1 1 AD1 VSS[15] VSS[121] M12

220U_D2_4VM
+ C1235 C1236 C1237 AE25 P11 C1238 C1239 AD10 M13
VCC1_5_B[9] VCC1_05[15] VSS[16] VSS[122]

C1234
AE26 P18 10U_0805_10V AD12 M14
VCC1_5_B[10] VCC1_05[16] VSS[17] VSS[123]
AE27 VCC1_5_B[11] VCC1_05[17] T11 AD13 VSS[18] VSS[124] M15
2 2 2 2 2 2
AE28 VCC1_5_B[12] VCC1_05[18] T18 AD14 VSS[19] VSS[125] M16
AE29 U11 AD17 M17

CORE
2.2U_0603_6.3V4Z VCC1_5_B[13] VCC1_05[19] VSS[20] VSS[126]
F25 VCC1_5_B[14] VCC1_05[20] U18 AD18 VSS[21] VSS[127] M23
+5VS +3VS 22U_0805_6.3V6M~D G25 V11 AD21 M28
VCC1_5_B[15] VCC1_05[21] 5ohm@100MHz VSS[22] VSS[128]
H24 VCC1_5_B[16] VCC1_05[22] V12 AD28 VSS[23] VSS[129] M29
H25 V14 +VCCP_VCCDMI 1 2 +VCCP AD29 N11
VCC1_5_B[17] VCC1_05[23] VSS[24] VSS[130]
1

22U_0805_6.3VAM
J24 V16 L98 AD4 N12
R1127 D45 VCC1_5_B[18] VCC1_05[24] BLM18PG181SN1_0603~D VSS[25] VSS[131]
J25 VCC1_5_B[19] VCC1_05[25] V17 1 AD5 VSS[26] VSS[132] N13
100_0402_5%~D K24 V18 C1240 AD6 N14
CH751H-40PT_SOD323-2 VCC1_5_B[20] VCC1_05[26] VSS[27] VSS[133]
K25 VCC1_5_B[21] AD7 VSS[28] VSS[134] N15
L23 R29 +1.5VS_VCCDMIPLL AD9 N16
2

VCC1_5_B[22] VCCDMIPLL 2 VSS[29] VSS[135]


L24 VCC1_5_B[23] AE12 VSS[30] VSS[136] N17
+ICH_V5REF_RUN L25 W23 23mA AE13 N18
VCC1_5_B[24] VCC_DMI[1] +VCCP VSS[31] VSS[137]
1 20 mils M24 VCC1_5_B[25] VCC_DMI[2] Y23 AE14 VSS[32] VSS[138] N26
M25 VCC1_5_B[26] AE16 VSS[33] VSS[139] N27
C1241 N23 AB23 48mA AE17 P12
1U_0603_10V6K~D VCC1_5_B[27] V_CPU_IO[1] VSS[34] VSS[140]
N24 VCC1_5_B[28] V_CPU_IO[2] AC23 AE2 VSS[35] VSS[141] P13
2

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
N25 VCC1_5_B[29] AE20 VSS[36] VSS[142] P14
0.1U Change to 1U P24 AG29 2mA 0.1U_0402_16V4Z +3VS 1 1 1 AE24 P15
VCC1_5_B[30] VCC3_3[1] VSS[37] VSS[143]

C1242

C1243

C1244
P25 VCC1_5_B[31] AE3 VSS[38] VSS[144] P16

VCCA3GP
R24 AJ6 0.1U_0402_16V4Z 1 +3VS 1 AE4 P17
+5VALW +3VALW VCC1_5_B[32] VCC3_3[2] VSS[39] VSS[145]
R25 VCC1_5_B[33] AE6 VSS[40] VSS[146] P2
2 2 2

C1245

C1246
R26 AC10 0.1U_0402_16V4Z 1 +3VS AE9 P23
VCC1_5_B[34] VCC3_3[7] VSS[41] VSS[147]
R27 VCC1_5_B[35] AF13 VSS[42] VSS[148] P28
1

2 2

C1247
D46 T24 AD19 AF16 P29
R1128 VCC1_5_B[36] VCC3_3[3] VSS[43] VSS[149]

VCCP_CORE
T27 VCC1_5_B[37] VCC3_3[4] AF20 AF18 VSS[44] VSS[150] P4
100_0402_5%~D 2 (DMI)
T28 VCC1_5_B[38] VCC3_3[5] AG24 AF22 VSS[45] VSS[151] P7
CH751H-40PT_SOD323-2 T29 AC20 +3VS AH26 R11
C VCC1_5_B[39] VCC3_3[6] VSS[46] VSS[152] C
U24 308mA AF26 R12
2

+ICH_V5REF_SUS VCC1_5_B[40] VSS[47] VSS[153]


U25 VCC1_5_B[41] VCC3_3[8] B9 AF27 VSS[48] VSS[154] R13

0.1U_0402_16V4Z

C1248

0.1U_0402_16V4Z

C1249

0.1U_0402_16V4Z

C1250
20 mils V24 VCC1_5_B[42] VCC3_3[9] F9 1 1 1 Add 0.1uF AF5 VSS[49] VSS[155] R14
1 V25 VCC1_5_B[43] VCC3_3[10] G3 AF7 VSS[50] VSS[156] R15
C1251 U23 G6 AF9 R16
VCC1_5_B[44] VCC3_3[11] VSS[51] VSS[157]
W24 VCC1_5_B[45] VCC3_3[12] J2 AG13 VSS[52] VSS[158] R17
0.1U_0402_16V 2 2 2

PCI
W25 VCC1_5_B[46] VCC3_3[13] J7 AG16 VSS[53] VSS[159] R18
2
K23 VCC1_5_B[47] VCC3_3[14] K7 AG18 VSS[54] VSS[160] R28
Y24 VCC1_5_B[48] AG20 VSS[55] VSS[161] T12
L99 Y25 AJ4 0.1U_0402_16V +3VS AG23 T13
10UH_LB2012T100MR_20%_0805~D 47mA VCC1_5_B[49] VCCHDA VSS[56] VSS[162]
1 AG3 VSS[57] VSS[163] T14
+1.5VS 1 2 +1.5VS_VCCSATAPLL AJ19 AJ3 11mA 0.1U_0402_16V +3VALW C1252 AG6 T15
VCCSATAPLL VCCSUSHDA VSS[58] VSS[164]
1 AG9 VSS[59] VSS[165] T16
10U_0805_10V
1U_0603_10V4Z

AC16 AC8 11mA C1253 AH12 T17


+1.5VS VCC1_5_A[1] VCCSUS1_05[1] T140 2 VSS[60] VSS[166]
1 AD15 VCC1_5_A[2] VCCSUS1_05[2] F17 AH14 VSS[61] VSS[167] T23
T141
C1254

1 1 AD16 VCC1_5_A[3] AH17 VSS[62] VSS[168] B26


2
ARX
C1255

C1256 AE15 AD8 +VCCSUS1_5_ICH_1 AH19 U12


VCC1_5_A[4] VCCSUS1_5[1] T142 VSS[63] VSS[169]
AF15 VCC1_5_A[5] AH2 VSS[64] VSS[170] U13
2 1U_0603_10V4Z +VCCSUS1_5_ICH_2
AG15 VCC1_5_A[6] VCCSUS1_5[2] F18 AH22 VSS[65] VSS[171] U14
2 2 T143
AH15 VCC1_5_A[7] 1 AH25 VSS[66] VSS[172] U15
AJ15 C1257 AH28 U16
VCC1_5_A[8] VSS[67] VSS[173]
A18 AH5 U17
VCCPSUS

VCCSUS3_3[1] +3VALW VSS[68] VSS[174]


AC11 D16 0.1U_0402_16V4Z AH8 AD23
+1.5VS VCC1_5_A[9] VCCSUS3_3[2] 2 VSS[69] VSS[175]
1 AD11 VCC1_5_A[10] VCCSUS3_3[3] D17 AJ12 VSS[70] VSS[176] U26
C1258 AE11 E22 AJ14 U27
VCC1_5_A[11] VCCSUS3_3[4] VSS[71] VSS[177]
ATX

AF11 VCC1_5_A[12] AJ17 VSS[72] VSS[178] U3


1U_0603_10V4Z AG10 AJ8 V1
2 VCC1_5_A[13] VSS[73] VSS[179]
AG11 VCC1_5_A[14] VCCSUS3_3[5] AF1 B11 VSS[74] VSS[180] V13
AH10 VCC1_5_A[15] 212mA B14 VSS[75] VSS[181] V15
AJ10 VCC1_5_A[16] VCCSUS3_3[6] T1 B17 VSS[76] VSS[182] V23
VCCSUS3_3[7] T2 B2 VSS[77] VSS[183] V28
AC9 VCC1_5_A[17] VCCSUS3_3[8] T3 B20 VSS[78] VSS[184] V29
B
T4 +3VALW B23 V4 B
VCCSUS3_3[9] VSS[79] VSS[185]

0.1U_0402_16V

0.022U_0402_16V7K~D

0.022U_0402_16V7K~D
1342mA AC18 VCC1_5_A[18] VCCSUS3_3[10] T5 B5 VSS[80] VSS[186] V5
AC19 VCC1_5_A[19] VCCSUS3_3[11] T6 B8 VSS[81] VSS[187] W26
U6 1 1 1 C26 W27
VCCPUSB

+1.5VS VCCSUS3_3[12] VSS[82] VSS[188]


AC21 VCC1_5_A[20] VCCSUS3_3[13] U7 C27 VSS[83] VSS[189] W3

C1259

C1260

C1261
1 VCCSUS3_3[14] V6 E11 VSS[84] VSS[190] Y1
C1262 G10 V7 E14 Y28
VCC1_5_A[21] VCCSUS3_3[15] 2 2 2 VSS[85] VSS[191]
G9 VCC1_5_A[22] VCCSUS3_3[16] W6 E18 VSS[86] VSS[192] Y29
0.1U_0402_16V W7 E2 Y4
2 VCCSUS3_3[17] VSS[87] VSS[193]
AC12 VCC1_5_A[23] VCCSUS3_3[18] Y6 E21 VSS[88] VSS[194] Y5
AC13 VCC1_5_A[24] VCCSUS3_3[19] Y7 E24 VSS[89] VSS[195] AG28
+1.5VS AC14 VCC1_5_A[25] VCCSUS3_3[20] T7 E5 VSS[90] VSS[196] AH6
1 11mA E8 AF2
C1263 +VCCCL1_05_ICH VSS[91] VSS[197]
AJ5 VCCUSBPLL VCCCL1_05 G22 F16 VSS[92] VSS[198] B25
11mA T144
1 F28 VSS[93]
0.1U_0402_16V AA7 G23 +VCCCL1_5 C1264 F29 A1
2 VCC1_5_A[26] VCCCL1_5 VSS[94] VSS_NCTF[1]
USB CORE

AB6 VCC1_5_A[27]
19/73/73mA G12 VSS[95] VSS_NCTF[2] A2
AB7 A24 +3VS 1 1 0.1U_0402_16V4Z G14 A28
VCC1_5_A[28] VCCCL3_3[1] 2 VSS[96] VSS_NCTF[3]
AC6 VCC1_5_A[29] VCCCL3_3[2] B24 G18 VSS[97] VSS_NCTF[4] A29
C1265 1U_0603_10V4Z

C1266 0.1U_0402_16V

AC7 VCC1_5_A[30] G21 VSS[98] VSS_NCTF[5] AH1


@ @ G24 AH29
VCC_LAN1_05_INT_ICH_1 2 2 VSS[99] VSS_NCTF[6]
1 2 A10 VCCLAN1_05[1] G26 VSS[100] VSS_NCTF[7] AJ1
+3VS C1267 VCC_LAN1_05_INT_ICH_2 A11 G27 AJ2
0.1U_0402_16V VCCLAN1_05[2] VSS[101] VSS_NCTF[8]
G8 VSS[102] VSS_NCTF[9] AJ28
1 2 +LAN_IO_VCCLAN 19/78/78mA A12 H2 AJ29
VCCLAN3_3[1] VSS[103] VSS_NCTF[10]
0.1U_0402_16V

1 R1129 0_0603_5% B12 H23 B1


C1268 VCCLAN3_3[2] VSS[104] VSS_NCTF[11]
23mA H28 VSS[105] VSS_NCTF[12] B29
+1.5VS 1 2 +1.5VS_VCCGLANPLL A27 H29
L100 VCCGLANPLL VSS[106]
80mA
2
GLAN POWER
10U_0805_10V

1UH_20%_0805~D ICH9M REV 1.0


2.2U_0603_6.3V4Z

+1.5VS D28 VCCGLAN1_5[1]


D29 VCCGLAN1_5[2]
1 1 1 E26 VCCGLAN1_5[3]
A C1269 C1270 C1271 A
E27 VCCGLAN1_5[4]
1mA
+3VS A26
VCCGLAN3_3
2 2 2
ICH9M REV 1.0
4.7U_0603_6.3V6M~D

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 20 of 48
5 4 3 2 1
5 4 3 2 1

W=60mils SI3456BDV-T1-E3 1N TSOP6


W=60mils
+3VALW +LAN_IO
Q59 +LAN_VDD
1.5A R105

D
6 R111 1 2 +LAN_DVDD12

S
1 5 4 +LAN_IO_R 2 1

0.1U_0402_16V C572

0.1U_0402_16V C698

0.1U_0402_16V C782

0.1U_0402_16V C780

0.1U_0402_16V C779

0.1U_0402_16V C700
C790 2 1 1 1 1 1 1 1 0_0603_5% 1 1 1 1 1 1
1U_0603_10V6K 1 0_1206_5%~D C812 C777 C787 C781 C802 C804 C45
@

G
2

3
2 2 2 2 2 2 2 2 2 2 2 2 2

22U_1206_6.3V6M

22U_1206_6.3V6M

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V
+B+_BIAS

2
D D
R1239
470K_0402_5%

1 EN_WOL
These caps close to U64: Pin 13, 30, 36
1

2
D
Q58 R906
These caps close to U64: Pin 29, 37, 44, 45
27 EN_WOL# 2
G SSM3K7002FU_SC70-3 1.5M_0402_5%
S
3

1
+LAN_IO

1 1
C783 C792

22U_1206_6.3V6M

0.1U_0402_16V
2 2
+LAN_IO

R1241 3.6K_0402_5%
1 2
U64

2 1 GLAN_RXP_C 20 33 LAN_LED3
19 GLAN_RXP HSOP LED3/EEDO
C1473 0.1U_0402_16V 34 LAN_LED2
GLAN_RXN_C LED2/EEDI/AUX LAN_LED1
19 GLAN_RXN 2
C1476
1
0.1U_0402_16V
21 HSON LED1/EESK 35 These caps close to U64: Pin 44,45
EECS 32
GLAN_TXP 15 ( Should be place within 200 mils )
19 GLAN_TXP HSIP
38 LAN_LED0
C GLAN_TXN LED0 C
19 GLAN_TXN 16 HSIN
RTL8111DL MDIP0 2 LAN_MDIP0 W=60mils +LAN_VDD
17 3 LAN_MDIN0
15 CLK_PCIE_LAN REFCLK_P MDIN0
18 5 LAN_MDIP1 L107
15 CLK_PCIE_LAN# REFCLK_M MDIP1
6 LAN_MDIN1 1 2 CM1293-04SO_SOT23-6
MDIN1 LAN_MDIP2
15 GLAN_REQ#9 25 CLKREQB MDI P2 8
9 LAN_MDIN2 4.7UH_1008HC-472EJFS-A_5%_1008
1 1 RJ45_TX0- 1 4 RJ45_RX1-
MDI N2 LAN_MDIP3 C1478 C1479 CH1 CH4
17,23,25,26 PCI_RST# 27 PERSTB MDI P3 11

22U_1206_6.3V6M
0.1U_0402_16V
12 LAN_MDIN3 These components close to U64: Pin 48
MDI N3
2 2
1
R1244
2
2.49K_0402_1%
46 RSET FB12 4 +LAN_DVDD12 ( Should be place within 200 mils ) 2 Vn Vp 5 +3VS
R1245
17,23,26,27 EC_PME# 26 48 +LAN_VDD_L W=60mils W=30mils L110 W=30mils
LANWAKEB SROUT12
+3VS 1 2ISOLATEB 28 ISOLATEB
0_0603_5%
19 +LAN_VDD_EVDD 2 1 +LAN_VDD RJ45_TX0+ 3 6 RJ45_RX1+
1K_0402_5% EVDD12 CH2 CH3
41 CKTAL1 DVDD12 30 +LAN_DVDD12
2

42 36 1 2 @ D28
R1246 CKTAL2 DVDD12 C1484 1U_0402_6.3V6K~D
DVDD12 13
15K_0402_5% AVDD12 10 1 2
R1253 C1485 1U_0402_6.3V6K~D CM1293-04SO_SOT23-6
2

0_0402_5% 39
1

AVDD12 RJ45_TX2- RJ45_TX3-


1 CH1 CH4 4
19 LAN_CABDT LAN_CABDT
23 44 +LAN_IO These caps close to U64: Pin 19
NC VDDSR
24 NC VDDSR 45
1

7 GND VDD33 29 2 Vn Vp 5 +3VS


Y9 14 GND VDD33 37
27P_0402_50V8J

27P_0402_50V8J

31 0_0603_5% L108
GND +LAN_AVDD33
1 2 47 GND AVDD33 1 2 1 +LAN_IO
2 2 40 RJ45_TX2+ 3 6 RJ45_TX3+
AVDD33 CH2 CH3
C1488

C1489

25MHZ_20P_1BX25000CK1A 22 43 +LAN_IO 1 2
EGND ENSR C1486 0.1U_0402_16V @ D29
B B
1 2
1 1 RTL8111DL-GR_LQFP48 C1487 0.1U_0402_16V
1 2 JRJ45
C1495 0.1U_0402_16V
1 2 LAN_LED0 1 R968 2LAN_ACTIVITY# 13
C1496 0.1U_0402_16V 220_0402_5% Yellow LED-

+LAN_IO 12 Yellow LED+


0_0402_5% RJ45_TX3- 8 PR4-

C103

C122
LAN_LOPWEN 1 2 ISOLATEB 1 1
19 LAN_LOPWEN
@ R1374 These caps close to U64: Pin 1, 40,29,37 RJ45_TX3+ 7 PR4+
@ @ RJ45_RX1- 6
2 2 PR2-

220P_0603_10V7K

220P_0603_10V7K
T51
RP42 RJ45_TX2- 5
C1490 1 PR3-
2 0.01U_0402_16V7K +V_DAC 1 TCT1 MCT1 24 8 1 D54
LAN_MDIN3 2 23 RJ45_TX3- 7 2 LAN_LED2 1 2 LED2_LED3 RJ45_TX2+ 4
LAN_MDIP3 TD1+ MX1+ RJ45_TX3+ PR3+
3 TD1- MX1- 22 6 3
5 4 CH751H-40PT_SOD323-2 RJ45_RX1+ 3
C1491 1 PR2+
2 0.01U_0402_16V7K +V_DAC 4 TCT2 MCT2 21
LAN_MDIN2 5 20 RJ45_TX2- 75_1206_8P4R_5% D55 RJ45_TX0- 2
LAN_MDIP2 TD2+ MX2+ RJ45_TX2+ LAN_LED3 1 PR1-
6 TD2- MX2- 19 2 2 GND 15
C1493 RJ45_TX0+ 1
C1492 1 +V_DAC PR1+
2 0.01U_0402_16V7K 7 TCT3 MCT3 18 1000P_1206_2KV7K CH751H-40PT_SOD323-2
GND 14
LAN_MDIN1 8 17 RJ45_RX1- LED2_LED3 1 R969 2 LINK_10_1000# 11
LAN_MDIP1 TD3+ MX3+ RJ45_RX1+ 1 220_0402_5% Green LED-
9 TD3- MX3- 16
LED1_LED3 1 R970 2 LINK_100_1000# 9
C1494 1 Orange LED-
2 0.01U_0402_16V7K +V_DAC 10 TCT4 MCT4 15 D56 220_0402_5%
LAN_MDIN0 11 14 RJ45_TX0- LAN_LED1 1 2 LED1_LED3 +LAN_IO 10
LAN_MDIP0 TD4+ MX4+ RJ45_TX0+ Green-Orange LED+
12 TD4- MX4- 13

C141

C142

C144
CH751H-40PT_SOD323-2 1 1 1
C-1775553
A D57 CONN@ A
BOTH_GST5009-LF LAN_LED3 1 2 @ @ @
2 2 2

220P_0603_10V7K

220P_0603_10V7K

220P_0603_10V7K
CH751H-40PT_SOD323-2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/03/21 Deciphered Date 2009/03/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 21 of 48
5 4 3 2 1 hexainf@hotmail.com
5 4 3 2 1

SATA HDD CONN SATA ODD CONN

JSATA1 JSATA2
1 GND
1 ODD_ITX_DRX_P0 2
GND 18 ODD_ITX_DRX_P0 RX+
PSATA_ITX_DRX_P0 2 ODD_ITX_DRX_N0 3
D 18 PSATA_ITX_DRX_P0 A+ 18 ODD_ITX_DRX_N0 RX- D
PSATA_ITX_DRX_N0 3 4
18 PSATA_ITX_DRX_N0 A- GND
C393 3900P_0402_50V7K 4 C326 1 2 0.01U_0402_16V7K ODD_IRX_DTX_N0 5
GND 18 ODD_IRX_DTX_N0_C TX-
2 1 5 C327 1 2 0.01U_0402_16V7K ODD_IRX_DTX_P0 6
18 PSATA_IRX_DTX_N0_C B- 18 ODD_IRX_DTX_P0_C TX+
6 B+ 7 GND
18 PSATA_IRX_DTX_P0_C 2 1 7 GND
close JODD1 8 DP
C392 3900P_0402_50V7K 9 +5V
+5VS 10 +5V
8 VCC3.3 11 MD
9 VCC3.3 12 GND GND1 14
10 VCC3.3 13 GND GND2 15
11 GND
12 TYCO_2-1759838-5_NR~D
GND
13 GND
+5VS 14 VCC5
15 VCC5
16 VCC5
17 GND
18 RESERVED
19 GND
20 VCC12
21 VCC12 GND 23
22 VCC12 GND 24

+5VS
+5VS SUYIN_127043FB022G345ZR_NR
CONN@
10U_0805_10V 0.1U_0402_16V
10U_0805_10V 0.1U_0402_16V
1 1 1 1
1 1 1 1 C499
C498 C506 C503
C C574 C296 C377 C376 C
2 2 2 2
2 2 2 2
1U_0603_10V4Z 1000P_0402_50V7K~N
0.1U_0402_16V 1000P_0402_50V7K~N

Close to ODD Conn


Close to SATA HDD

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 22 of 48
5 4 3 2 1
A B C D E

Mini-Express Card---WLAN +1.5VS


+3V_WLAN

R411 1
@
2 +3VALW
0_0805_5%
R412 1 2 +3VS
0_0805_5%
JMINI2 @
17,21,26,27 EC_PME# EC_PME# 1 1
2 2
CH_DATA @
@R380 2 MINI_PIN3
R380 1 0_0402_5% 3 +3V_WLAN
29 CH_DATA 3
4 4
CH_CLK @R381
@ 2 MINI_PIN4
R381 1 0_0402_5% 5 0.01U_0402_16V7K 4.7U_0805_10V4Z~N
29 CH_CLK 5
6 6
15 WLAN_REQ#4 WLAN_REQ#4 7 1 1 1
1 7 C500 C489 C456 1
18,25,27 LPC_FRAME# 8 8
9 9
LPC_AD3 10 10 2 2 2
15 CLK_PCIE_MCARD# 11 11
LPC_AD2 12 12 0.1U_0402_16V
15 CLK_PCIE_MCARD 13 13
LPC_AD1 14 14
15 15
LPC_AD0 16 +1.5VS
PCI_RST# 16
18,25,27 LPC_AD[0..3] 1 2 17 17
R444 0_0402_5% 18 0.01U_0402_16V7K
18
15 CLK_DEBUG_PORT 19 19
27 WL_OFF# WL_OFF# 20 1 1
20 C488
21 21
17,21,25,26 PCI_RST# 22 22
19 PCIE_RXN3 PCIE_RXN3 1 2 PCIE_C_RXN3 23 C485
R4032 23 2 2
+3VALW 10_0402_5% 24 24
19 PCIE_RXP3 PCIE_RXP3 R4061 20_0402_5% PCIE_C_RXP3 25
R404 0_0402_5% 25 0.01U_0402_16V7K
26 26
27 27
+1.5VS 28 28
29 29
30 +3VALW +3V_WLAN
PCIE_TXN3 30 Q130
19 PCIE_TXN3 31 31
32 32

D
PCIE_TXP3 33 6

S
19 PCIE_TXP3 33
34 34 1 5 4
35 C1468 2
USB20_N6 35 1U_0603_10V6K
19 USB20_N6 36 36 1
37 SI3456BDV-T1-E3 1N TSOP6

G
USB20_P6 37 2
19 USB20_P6 38

3
38 +B+_BIAS
+3V_WLAN 39 39
2 2
40 40
41 41

2
PAD T61 LED_WWAN# 42 42 R36
43 43
28 LED_WLAN# LED_WLAN# 44 470K_0402_5%
44
45 45
+3V_WLAN 1 2 46

1
R86 100K_0402_5% 46 WLANPW_EN
47 47
+1.5VS 48 48

2
D
49 49
50 WLANPW_EN# 2 Q5 R1243
50 WLANPW_EN#
51 G SSM3K7002FU_SC70-3 1.5M_0402_5%
51 @
+3V_WLAN 52 S

3
52

1
53 GND1
54 GND2 Power status(Left)
FOX_AS0B246-S50U-7F
LED1
12-21-BHC-ZL1M2RY-2C BLUE +5VALW

PWR_BLUE_LED# 2 1 1 R472 2
27,28 PWR_BLUE_LED#
200_0603_5%

LED2 +5VALW
+3VS BATT_LOW_LED# 3 Y
27 BATT_LOW_LED#
1 1 R471 2
3 +1.5VS BATT_CHG_LED# 2 3
27 BATT_CHG_LED#
B 200_0603_5%
12-22/Y2BHC-A30/2C_Y/B~D

JMINI1
1 1 2 2
3 3 4 4
5 5 6 6
7 7 8 8 LPC_FRAME# 18,25,27
9 10 LPC_AD3
9 10 LPC_AD2
11 11 12 12
1 2 13 14 LPC_AD1
27 EC_RX_P80_DATA 13 14
@ R1431
0_0402_5% 15 16 @ R1430 10_0402_5%2 LPC_AD0
PCI_RST# 15 16
1 2 17 17 18 18 LPC_AD[0..3] 18,25,27
@ R1432
0_0402_5% 19 20 @ R1429 10_0402_5%2 EC_TX_P80_DATA 27
15 CLK_DEBUG_PORT 19 20
21 21 22 22 PCI_RST# 17,21,25,26
23 23 24 24 +3VS
25 25 26 26
27 27 28 28 +1.5VS
29 29 30 30
31 31 32 32
33 33 34 34
35 35 36 36
37 37 38 38
+3VS 39 39 40 40
41 41 42 42
43 43 44 44
45 45 46 46
47 47 48 48 +1.5VS
49 49 50 50
51 51 52 52 +3VS
4 4
53 GND1 GND2 54

ACES_88910-5204
@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 23 of 48
A B C D E hexainf@hotmail.com
5 4 3 2 1

+MIC1_VREFO

@ MICROPHONE IN JACK

1
+3VS +VDDA

1U_0402_6.3V
1

C814
+5VS R506 R505
1 2 +DVDD_IO 1 2 4.7K_0402_5% 4.7K_0402_5%
R106 0_0603_5% L21 0_0805_5%

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V
2

1U_0402_6.3V

1U_0402_6.3V
10U_0603_6.3V

10U_0603_6.3V
1 1 1 1 1 1 1 1

2
C806

C809

C797

C796

C818

C817

C825

C820
1U_0402_6.3V
1

C816
JMIC1
1 1
+VDDA 2 2 2 2 2 2 2 2 MIC_LEFT 1 2 1 2 2 2
2 C42 L70 BLM18BD601SN1D_0603~D 6 6 7 7
MIC_RIGHT 1 2 1 2 3 3 8 8
C43 L71 BLM18BD601SN1D_0603~D GND

27
38

39
45
9

1
U60 MIC_JD 4 4 GND 10
D

DVDD_IO
D

DVDD

AVDD
AVDD

PVDD
PVDD
DVDD_CORE
1 2 SENSEB @ C525 @ C524 5 5

3
R135 100K_0402_5%

100P_0402_25V8K

100P_0402_25V8K
@ D16 FOX_JA63331-B39S4-7F

SM05T1G_SOT23-3~D
18 ACZ_BITCLK 6 HDA_BITCLK HP0_PORT_A_L 28
29

1
HP0_PORT_A_R
18 ADC_ACZ_SDIN0 2 1 8 HDA_SDI VREFOUT_A_or_F 23
33_0402_5% R128
5 31 HP_LEFT
18 ACZ_SDOUT HDA_SDO HP1_PORT_B_L
32 HP_RIGHT
HP1_PORT_B_R +MIC1_VREFO
18 ACZ_SYNC 10 HDA_SYNC
19 MIC_LEFT
PORT_C_L MIC_RIGHT
18 ACZ_RST# 11 HDA_RST# PORT_C_R 20
24
10mil
VREFOUT_C
16 MIC_CLK 1 R744 2 0_0402_5% 2 DMIC_CLK/GPIO1
R107 0_0402_5%
40 SPKER_L1_R 1 2 SPKER_L1
SPKR_PORT_D_L+ SPKER_L2_R SPKER_L2
16 MIC_SIG 1 R745 2 0_0402_5% 4 DMIC0/GPIO2 SPKR_PORT_D_L- 41 1 2
R108 0_0402_5%
46 DMIC1/GPIO0/SPDIF_OUT_1
SPKR_PORT_D_R- 43 Speaker Connector
@ 48 44
R113 0_0402_5% SPDIF_OUT_0 SPKR_PORT_D_R+

27 EC_MUTE 1 2 47 EAPD PORT_E_L 15


@ D12
16 JSPK2
C477 1 PORT_E_R R103
2 35 CAP- 2
17 1 2 1 SPKER_L1 1 3
PORT_F_L GNDA 1 G1
2.2U_0603_6.3V6K 36 18 0_0805_5% @ 3 SPKER_L2 2 4
CAP+ PORT_F_R R753 R115 2 G2
+5VS 1 2
R98 2.49K_0402_1% SENSEB 14 12 1 2 0_0402_5% MONO_IN 1 2 ACES_88266-0200
HP_JD SENSE_B PC_BEEP 0_0805_5% SM05T1G_SOT23-3~D
1 2
R379 20K_0402_1% 25 R116
MIC_JD MONO_OUT
1 2 13 SENSE_A 1 2

@
10K_0402_1% R384 22 0_0805_5%
CAP2 R117
2 1

C33

C35
_0402_50V7K~N C44

100P_0402_25V8K

100P_0402_25V8K
7 DVSS VREFFILT 21 1 2
42 0_0805_5% @
PVSS R118
26 AVSS V- 34
C 30 1 2 C
AVSS 0_0805_5% @
33 AVSS VREG 37
49 AGND
@ GND GNDA

1U_0402_6.3V
10U_0603_6.3V
1 1 1 1

2.2U_0603_6.3V6K

C826

C827

C828
C28 2 1 ACZ_BITCLK 92HD81B1X5NLGXA1X8 48P C496
@ R127 10_0402_5%
15P_0402_50V8J 4.7U_0603_6.3V
2 2 2 2
near U9.6

HEADPHONE OUT JACK


JHP1
1 1
HP_LEFT 1 2 1 2 2 2
56_0402_5% R747 L66 BLM18BD601SN1D_0603~D 6 6 7 7
HP_RIGHT 1 2 1 2 3 3 8 8

C260

C252
1000P_0402_50V7K~N C224

C225
56_0402_5% R748 1 1 L67 BLM18BD601SN1D_0603~D GND 9
HP_JD 4 4 GND 10

@ @ 5

0.01U_0402_16V7K

0.01U_0402_16V7K
5

1000P_0402_50V7K~N
2 2
2 2

3
FOX_JA63331-B39S4-7F

@ D23
B 1 1 B
SM05T1G_SOT23-3~D For IDT
1

@ @

S TR SSM3K131TU 1N UFM
CO-LAY MOS

1
D D D D
Q15 2 2 2 2 Q10

Q132
2N7002_SOT23-3 G G G G 2N7002_SOT23-3
@S Q131S S S @

3
+5VALW S TR SSM3K131TU 1N UFM
@ @

3
S S S S

S TR SSM3K131TU 1N UFM
2

2N7002_SOT23-3 2N7002_SOT23-3
G G G G
2 2 2 2
EC Beep R54
R1433 Q11 Q133 Q16

Q134
C16 0.1U_0402_16V 10K_0402_1% S TR SSM3K131TU 1N UFM
D D D D

1
1 2 MONO_IN
27 BEEP
1

499K_0402_1%~D
1

2
D
EC_MUTE 2 R1434
G Q135 100K_0402_5%
S SSM3K7002FU_SC70-3 @
3

ICH Beep

1
R62
C25 0.1U_0402_16V
19 SB_SPKR 1 2

499K_0402_1%~D
A A
10K_0402_5%
2
R129

@
1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/08/05 Deciphered Date 2007/08/05 Title
SCHEMATIC, M/B LA-4232P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 24 of 48
5 4 3 2 1
5 4 3 2 1

D
TPM 1.2 D

JTPM1

LPC_FRAME# 1 2 LPC_AD0
18,23,27 LPC_FRAME# GND1 RES0 LPC_AD0 18,23,27
3 4 LPC_AD1
17,21,23,26 PCI_RST# IAC_SDATA_OUT RES1 LPC_AD1 18,23,27
SERIRQ 5 6 LPC_AD2
19,27 SERIRQ GND2 3.3V LPC_AD2 18,23,27
PCI_CLKRUN# 7 8 LPC_AD3
19,27 PCI_CLKRUN# IAC_SYNC GND3 LPC_AD3 18,23,27
+3VS 12mA 9 IAC_SDATA_IN GND4 10 CLK_PCI_TPM 15
+3VALW 11 IAC_RESET# IAC_BITCLK 12

GND
GND
GND
GND
GND
GND
* Base I/O Address
ACES_88018-124L 0 = 02Eh

13
14
15
16
17
18
1 = 04Eh

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/08/05 Deciphered Date 2007/08/05 Title
SCHEMATIC, M/B LA-4232P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 25 of 48
5 4 3 2 1

hexainf@hotmail.com
5 4 3 2 1

Express card

D JEXP1 D
+1.5VS_PEC
Express Card Power Switch 4.7U_0805_10V4Z~N 1 GND
USB20_N7 2
19 USB20_N7 USB_D-
+1.5VS 1 1 USB20_P7 3
U11 +1.5VS_PEC 19 USB20_P7 USB_D+
EXPR_CPUSB# 4
C90 C89 CPUSB#
2 1 12 1.5Vin 1.5Vout 11 5 RSV
C91 0.1U_0402_16V 14 13 0.1U_0402_16V 6
1.5Vin 1.5Vout 2 2 ICH_SMBCLK RSV
+3VS 19 ICH_SMBCLK 7 SMB_CLK
+3VS_PEC ICH_SMBDATA 8
19 ICH_SMBDATA SMB_DATA
2 1 2 3.3Vin 3.3Vout 3 +1.5VS_PEC 9 +1.5V
C74 0.1U_0402_16V 4 5 10
3.3Vin 3.3Vout +3V_PEC +1.5VS_PEC +1.5V
+3VALW 17,21,23,27 EC_PME# 11 WAKE#
2 1 17 AUX_IN AUX_OUT 15 +3V_PEC 12 +3.3VAUX
C85 0.1U_0402_16V +3V_PEC PERST# 13
PCI_RST# 4.7U_0805_10V4Z~N PERST#
17,21,23,25 PCI_RST# 6 SYSRST# OC# 19 +3VS_PEC 14 +3.3V
15 +3.3V
SYSON 20 8 PERST# 15 EXPCARD_REQ#16 EXPCARD_REQ#16 16
27,36,41 SYSON SHDN# PERST# CLKREQ#
1 1 CPPE# 17
SUSP# CLK_PCIE_EXPR# CPPE#
27,36,41,42,43 SUSP# 1 STBY# NC 16 15 CLK_PCIE_EXPR# 18 REFCLK-
C92 C93 CLK_PCIE_EXPR 19
15 CLK_PCIE_EXPR REFCLK+
CPPE# 10 7 0.1U_0402_16V 20
CPPE# GND 2 2 PCIE_RXN4 GND
19 PCIE_RXN4 21 PERn0
EXPR_CPUSB# 9 19 PCIE_RXP4 PCIE_RXP4 22
CPUSB# PERp0
23 GND
18 PCIE_TXN4 24
RCLKEN +3VS_PEC 19 PCIE_TXN4 PETn0
PCIE_TXP4 25
19 PCIE_TXP4 PETp0
P2231NL E2 QFN 20P 4.7U_0805_10V4Z~N 26 GND
C +1.5V_CARD Max. 650mA, Average 500mA 27 GND
C
1 1 28 GND
+3V_CARD Max. 1300mA, Average 1000mA 29 GND
C75 C73 30
0.1U_0402_16V GND
2 2 FOX_1CH4312C-TB_LB

CONN@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 26 of 48
5 4 3 2 1
L18
+3VALW +EC_AVCC 2 1
+EC_AVCC +3VALW
1 2 FBM-11-160808-601-T_0603 +3VALW
C481
1 1 1 1 1 1 1000P_0402_50V7K~N
C482
0.1U_0402_16V
Board ID
+3VALW

0.1U_0402_16V
C281

0.1U_0402_16V
C285

0.1U_0402_16V
C277

0.1U_0402_16V
C493

1000P_0402_50V7K~N
C269

1000P_0402_50V7K~N
C291

1
ECAGND2 1
2 1
FBM-11-160808-601-T_0603 L19 R232
2 2 2 2 2 2 100K_0402_5%
Ra

2
R405 AD_BID

15K_0402_5%
10K_0402_5% 1

111
125

2
22
33
96

67
1

R231
EC_PME# EC_PME# 17,21,23,26 U29 C272
EC_PME_R# 0.1U_0402_16V
1 2 Rb

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
R414 0_0402_5% 2

1
1 2 GATEA20 1 21
19 ICH_PCIE_WAKE# 18 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM 16
R413 0_0402_5% KB_RST# 2 23 BEEP
18 KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP 24
@ SERIRQ 3 26 W_DISABLE# W_DISABLE# 29
19,25 SERIRQ SERIRQ# FANPWM1/GPIO12
LPC_FRAME# ACOFF Rev
18,23,25 LPC_FRAME#
LPC_AD3
4
5
LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF 39 0.1 0.2 0.3 0.4 1.0
18,23,25 LPC_AD3 LAD3
CLK_PCI_EC LPC_AD2 7 PWM Output C273 1 2 0.01U_0402_16V7K ECAGND
18,23,25 LPC_AD2 LAD2
LPC_AD1 8 63 BATT_TEMP
18,23,25 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 45
1

LPC_AD0 BATT_OVP Voltage


R272
18,23,25 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BATT_OVP 45 0 0.105 0.210 0.3 0.430
ADP_I/AD2/GPIO3A 65 ADP_I 39
CLK_PCI_EC 12 AD Input 66 AD_BID
15 CLK_PCI_EC PCICLK AD3/GPIO3B
@ 10_0402_5% R228 PLT_RST# 13 75 MIC_DIAG BATT_OVP 1 2 ECAGND
7,17,30,31 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 MIC_DIAG 16
EC_RST# POW_MON C276 0.01U_0402_16V7K
+3VALW 1 2 37 76 POW_MON 44 Rb ----- 3.3K 6.8K 10K 15K
2

EC_SCI# ECRST# SELIO2#/AD5/GPIO43


1 19 EC_SCI# 20 SCI#/GPIO0E
@ C282
@C282 47K_0402_5% PCI_CLKRUN# 38
19,25 PCI_CLKRUN# CLKRUN#/GPIO1D
2 68 DAC_BRIG
2
15P_0402_50V8J C268
KSI[0..7]
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D 70 EN_DFAN1
IREF
DAC_BRIG 16
EN_DFAN1 4 SPI Flash connect
0.1U_0402_16V 28 KSI[0..7] DA Output IREF/DA2/GPIO3E 71 IREF 39 JBIOS1
KSI0 55 72 M_PWROK_EC 1 2
1 KSO[0..15] KSI0/GPIO30 DA3/GPIO3F CHGVADJ 39
KSI1 56 R256 0_0402_5% SPI_CS# 1 2 +3VALW
+3VALW 28 KSO[0..15] KSI1/GPIO31 1 2
KSI2 57 SPI_SO 3 4
KSI2/GPIO32 3 4
KSI3 58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE
EC_MUTE 24 M/B rev:0.1; 0.2 ; 0.3 ; 0.4 +3VALW 5 5 6 6 SPI_CLK_R
KSO1 2 1 @ KSI4 59 84 LCD_TST 7 8 SPI_SI
R139 47K_0402_5% KSI5 60
KSI4/GPIO34 PSDAT1/GPIO4B
85 VGA_ON
LCD_TST 16 Voltage:0.0; 0.105; 0.210; 0.3 7 8
KSI5/GPIO35 PSCLK2/GPIO4C VGA_ON 42
LCD_CBL_DET# 16Rb: ---;3.3K ;6.8K ;10K
KSO2 2 1 @ KSI6 61 PS2 Interface 86 LCD_CBL_DET# E&T_2941-G08N-00E~D
R140 47K_0402_5% KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK ME@
62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK 28
EC_MUTE R312 1 2 10K_0402_5% KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 28
KSO1 40
KSO2
KSO3
KSO4
41
42
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23 SDICS#/GPXOA00 97 SPI_PULLDOWN 2 R274
EN_WOL#
1 4.7K_0402_5%
SPI Flash (8Mb*1) @ C507
43 KSO4/GPIO24 SDICLK/GPXOA01 98 EN_WOL# 21
KSO5 BT_OFF# 2SPI_CLK_R
+5VALW KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
VGATE
BT_OFF# 29 1
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 VGATE 7,19,44
KSO7 46 SPI Device Interface 0.1U_0402_16V
EC_SMB_DA1 R263 2 KSO7/GPIO27
1 4.7K_0402_5% KSO8 47 KSO8/GPIO28
+3VALW
KSO9 48 119 FRD#SPI_SO C314
EC_SMB_CK1 R262 2 KSO9/GPIO29 SPIDI/RD# 20mils
1 4.7K_0402_5% KSO10 49 KSO10/GPIO2A SPIDO/WR# 120 FWR#SPI_SI 1 2
KSO11 50 SPI Flash ROM 126 SPI_CLK 2 R437 1
+3VS KSO12 KSO11/GPIO2B SPICLK/GPIO58 FSEL#SPICS# 0.1U_0402_16V 10K_0402_5%
51 KSO12/GPIO2C SPICS# 128
KSO13 52 U37
EC_SMB_DA2 KSO14 KSO13/GPIO2D FSEL#SPICS# 2
R264 2 1 4.7K_0402_5% 53 KSO14/GPIO2E 1SPI_CS# 1 CS# VCC 8
KSO15 54 73 WLANPW_EN# R439 15_0402_5% 2 7
KSO15/GPIO2F CIR_RX/GPIO40 WLANPW_EN# 23 SO HOLD#
EC_SMB_CK2 R265 2 1 4.7K_0402_5% 81 74 MSEN# FRD#SPI_SO 1 2SPI_SO 3 SPI_CLK_R 1
6 2 SPI_CLK
KSO16/GPIO48 CIR_RLC_TX/GPIO41 MSEN# 16 WP# SCLK
82 89 FSTCHG 15_0402_5% R275 4 5 15_0402_5% R420
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG 39 GND SI
LCD_TST @ R269 2 1 4.7K_0402_5% 90 BATT_CHG_LED# SPI_SI 1 2 FWR#SPI_SI
BATT_CHGI_LED#/GPIO52 BATT_CHG_LED# 23
91 CAPSLED# MX25L1605AM2C-12G_SO8 15_0402_5% R438
CAPS_LED#/GPIO53 CAPSLED# 28
LCD_CBL_DET# R276 2 1 4.7K_0402_5% EC_SMB_CK1 77 GPIO 92 BATT_LOW_LED#
45 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_LOW_LED# 23
EC_SMB_DA1 78 93 SCRLED#
45 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 SCRLED# 28
MIC_DIAG R308 1 2 10K_0402_5% EC_SMB_CK2 79 SM Bus 95 SYSON
4,16,31 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 26,36,41
4,16,31 EC_SMB_DA2 EC_SMB_DA2 80 121 VR_ON
SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 44
EC_FB_SDATA R303 2 1 4.7K_0402_5% 127 ACIN
AC_IN/GPIO59 ACIN 19,38,39
EC_FB_SCLK R304 2 1 4.7K_0402_5%
SLP_S3# 6 100 EC_RSMRST#
19 SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 19
MSEN# R309 1 2 10K_0402_5% SLP_S5# 14 101 EC_LID_OUT#
19 SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 19
EC_SMI# 15 102 EC_ON
19 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 28
LID_SW# 16 103 EC_SWI#
LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# 19
EC_FB_SCLK 17 104 ICH_PWROK
28 EC_FB_SCLK SUSP#/GPIO0B ICH_PWROK/GPXO06 ICH_PWROK 7,19
28 EC_FB_SDATA EC_FB_SDATA 18 GPO 105 BKOFF#
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 16
EC_PME_R# 19 GPIO 106 WL_OFF#
EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# 23
VGA_THER 25 107 LCD_VCC_TEST_EN
+5VS 31 VGA_THER EC_THERM#/GPIO11 GPXO10 LCD_VCC_TEST_EN 16
FAN_SPEED1 28 108 PSID_DISABLE#
4 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 PSID_DISABLE# 38
R271 28 TOUCHKEY_TINT TOUCHKEY_TINT 29
4.7K_0402_5% EC_TX_P80_DATA FANFB2/GPIO15
23 EC_TX_P80_DATA 30 EC_TX/GPIO16
TP_DATA 1 2 EC_RX_P80_DATA 31 110 SLP_S4# SLP_S4# 19
23 EC_RX_P80_DATA EC_RX/GPIO17 PM_SLP_S4#/GPXID1
TP_CLK 1 2 ON_OFF 32 112 EC_ENBKL EC_ENBKL 16
28 ON_OFF ON_OFF/GPIO18 ENBKL/GPXID2
R270 PWR_BLUE_LED# 34 114 USB_EN USB_EN 29
23,28 PWR_BLUE_LED# PWR_LED#/GPIO19 GPXID3
4.7K_0402_5% NUMLED# 36 GPI 115 EC_THERM#
28 NUMLED# NUMLED#/GPIO1A GPXID4 EC_THERM# 19
116 SUSP#
GPXID5 SUSP# 26,36,41,42,43
117 PBTN_OUT#
GPXID6 PBTN_OUT# 19
118 PS_ID
XCLKI GPXID7 PS_ID 38
122 XCLK1
XCLKO 123 124 +V18R1 2 1U_0603_10V4Z
XCLK0 V18R C322
AGND

0.1U_0402_16V
GND
GND
GND
GND
GND

C270 2 1

KB926QFA1_LQFP128
11
24
35
94
113

69

+3VALW
U8 ECAGND
APX9132ATI-TRL_SOT23-3 1 R278 2 XCLKI
XCLKO@ 20M_0603_5%
LID_SW# 3 2
GND

VOUT VDD
2

1
R277
@ C275 0_0402_5%
1

@ 0.1U_0402_16V
2
1

C292 C297
1

+3VALW
15P_0402_50V8J

15P_0402_50V8J

U1
IN

OUT

APX9132ATI-TRL_SOT23-3

LID_SW# 3 2
GND

VOUT VDD
NC

NC

1 Security Classification Compal Secret Data Compal


0.5A per each pinElectronics, Inc.
C274 2007/1/15 2008/1/15 Title
Issued Date Deciphered Date
1

0.1U_0402_16V 32.768KHZ_12.5P_1TJS125BJ2A251
2 X2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
REED Switch MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 27 of 48

hexainf@hotmail.com
A B C D E

INT_KBD CONN. JKB1


KSO8 @C449
@ C449 100P_0402_25V8K KSI7 @C235
@ C235 100P_0402_25V8K

+3VALW KSI0 1 KSI3 @C239


@ C239 100P_0402_25V8K KSI6 @C236
@ C236 100P_0402_25V8K
KSI1 1
2
Power Button 27 KSI[0..7]
KSI[0..7] KSI2 3
2
3
KSO9 @C249
@ C249 100P_0402_25V8K KSI5 @C237
@ C237 100P_0402_25V8K

100K_0402_5%
KSI3 4
KSI4 4 KSI2 @C240
@ C240 100P_0402_25V8K KSO0 @C441
@ C441 100P_0402_25V8K
5 5

R297
KSI5 6
KSI6 6 KSI1 @C241
@ C241 100P_0402_25V8K KSO1 @C442
@ C442 100P_0402_25V8K
7 7
KSO[0..15] KSI7 8
27 KSO[0..15]

1
D15 KSO0 8 KSO10 @C248
@ C248 100P_0402_25V8K KSO2 @C443
@ C443 100P_0402_25V8K
9 9
2 KSO1 10
ON_OFF 27 10
PWR_ON-OFF_BTN# 1 KSO2 11 KSO11 @C247
@ C247 100P_0402_25V8K KSI4 @C238
@ C238 100P_0402_25V8K
51ON# KSO3 11
3 51ON# 38 12 12
1 KSO4 KSI0 @C242
@ C242 100P_0402_25V8K KSO3 @C444
@ C444 100P_0402_25V8K 1
13 13
CHN202UPT SC-70 KSO5 14
KSO6 14 KSO12 @C246
@ C246 100P_0402_25V8K KSO4 @C445
@ C445 100P_0402_25V8K
15 15
+3VALW KSO7 16 16

1
2 KSO8 17 KSO13 @C245
@ C245 100P_0402_25V8K KSO5 @C446
@ C446 100P_0402_25V8K
KSO9 17
18 18
2

C313 D13 KSO10 19 KSO14 @C244


@ C244 100P_0402_25V8K KSO6 @C447
@ C447 100P_0402_25V8K
R296 1000P_0402_50V7K~N RLZ20A_LL34 KSO11 19
20 20
4.7K_0402_5% 1 KSO12 KSO15 @C243
@ C243 100P_0402_25V8K KSO7 @C448
@ C448 100P_0402_25V8K
21

2
@ KSO13 21
22 22

1
D KSO14 23
1

23
27 EC_ON
EC_ON 1
R291
2 2
G Q26
KSO15 24
25
24
25
For EMI
0_0402_5% S SSM3K7002FU_SC70-3 26
3
26

27 GND1
28 GND2

ACES_88514-2601

Function/B CONN.

C324 1 2 4.7U_0603_6.3V
2 +3VS_FUN 2
+3VS R880
Regulator for ENE sensor @ 0_0603_5%
1 2 1
JFN1
1
18 SATA_LED# 1 2R_SATA_LED# 2 2
+3VALW R622 0_0402_5% 3
For ENE R611 PWR_ON-OFF_BTN# 3
+5VS
Adjustable Output 4 4
SUPPRE_ KC FBMA-11-100505-801T 0402 23 LED_WLAN# LED_WLAN# 5
R901 RT9198-33PBR SOT-23 5P 5
27 EC_FB_SDATA 1 2 FB_SDATA 6
FB_SCLK 6
1 2 3 SHDN# BP 4 27 EC_FB_SCLK 1 2 7 7
+3VS_FUN R612 8
10K_0603_1% SUPPRE_ KC FBMA-11-100505-801T 0402 BLUETOOTH_LED# 8
2 29 BLUETOOTH_LED# 9
1U_0402_6.3V4Z

GND 9
10 10
1 1 5 PWR_BLUE_LED# 11
VIN VOUT 23,27 PWR_BLUE_LED# 11
C250

27 TOUCHKEY_TINT TOUCHKEY_TINT 1 2 12
NUMLED# R606 0_0402_5% 12
U54 27 NUMLED# 13 13
CAPSLED# 14
2 +3VALW 27 CAPSLED# 14
SCRLED# 15
27 SCRLED# 15
BTOP_BTN# 16
FB_SCLK 16
17 GND
18 GND
0.1U_0402_16V4Z
1 ACES_88512-1641
C29

22P_0402_50V8J
1
D58
@2 C39
@ PWR_ON-OFF_BTN# 2
2
1
BTOP_BTN# 3

3 PJSOT24C_SOT23-3 3
near JFN1.3 @
near JFN1.7

Touch PAD/B CONN.


TP/B TO M/B ACES_88514-0441
+5VS
6 G2
5 G1
4 4
1 TP_CLK 3
27 TP_CLK 3
TP_DATA 2
27 TP_DATA 2
C300 1
0.01U_0402_16V7K 1
2 1 1
@ @ JP1

C309

100P_0402_25V8K C310

3
2 2
D24

100P_0402_25V8K
SM05T1G_SOT23-3~D
@

1
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 28 of 48
A B C D E
+5VALW +USB_AS
0.1U_0402_16V
1
80 mils U12
19 USB20_P0
USB20_P0

1
1 8 + C434 C223 USB_P0
GND OUT R155 USB_N0
2 IN OUT 7
3 6 150U_B2_6.3VM_R45M 470_0603_5% USB20_N0
IN OUT 2 19 USB20_N0
1 USB_EN# 4 5 JUSBP2
C228 EN# OC#
1

1 2
RT9711PS SO 8P GND
D 2 1 2 D+
0.1U_0402_16V R1 0_0402_5% 3
2 USB_EN# Q14 D-
2 2 1 +USB_AS W=60mils 4 VCC
G SSM3K7002FU_SC70-3 R3 0_0402_5%

1
USB_OC#0 19 S 5

3
R154 GND1
6 GND2
100K_0402_5% 7
@ GND3
8 GND4

2
ALLTO_C10797-10403-L

+USB_CS
+5VALW

80 mils 1
U14
GND OUT 8

1
2 IN OUT 7 Daughter board on right side CONN@
3 6 R156
USB_EN# IN OUT ACES_87213-1200G
1 4 EN# OC# 5 470_0603_5%
C253 14
RT9711PS SO 8P +USB_CS GND2
13

2
0.1U_0402_16V GND1
2
W=80mils
12 12
USB_OC#8_9 19 19 USB20_N2 11 11
19 USB20_P2 10 10
9 9
8 8

1
D
19 USB20_N8 7 7
USB_EN# 2 Q13 6
19 USB20_P8 6
G SSM3K7002FU_SC70-3 5 5
S 19 USB20_N9 4

3
4
+USB_BS
W=60mils 19 USB20_P9 3 3
+USB_BS 2 2
+5VALW 1
27 W_DISABLE# 1
JUSBP3

80 mils 1
U13
GND OUT 8
2 IN OUT 7
3 IN OUT 6
1 USB_EN# 4 5
C64 EN# OC#
CM1293-04SO_SOT23-6

1
RT9711PS SO 8P
0.1U_0402_16V R157 1 4 USB_P0
2 CH1 CH4
470_0603_5%

USB_OC#2 19

2
2 Vn Vp 5 +USB_AS
CM1293-04SO_SOT23-6 D2
1 4 USB20_N5 3 6 USB_N0 W_DISABLE# 2
CH1 CH4 CH2 CH3

1
D
1
USB_EN# 2 Q8 @D19
@ D19 3
G SSM3K7002FU_SC70-3
2 5 +3VS S

3
Vn Vp PJSOT24C_SOT23-3
@

Fingerprint 3 CH2 CH3 6 USB20_P5

JFP1 D21
19 USB20_N5 1 1
19 USB20_P5 2 2
3 +3VS
+3VS 3
4 4
5 5
6 6
7
8
GND
1
0.1U_0402_16V4Z
Bluetooth
GND C30
ACES_88512-0641 JBT1
1 1
@2 near JFP1.4 2
19 USB20_P4 2
19 USB20_N4 3 3
PAD T62 BT_ACTIVE 4 4
23 CH_CLK 5 5
27 BT_OFF# BT_OFF# 6 6
23 CH_DATA 7 7
+3VS 8 8
28 BLUETOOTH_LED# 9 9
Felica Conn 10
11
10 +3VS
GND
12 GND
ACES_88512-0641 +5VALW ACES_88460-1001
+5VS 8 0.1U_0402_16V4Z
GND
7 GND 1
2

6 C31
USB20_N3 6 R222
19 USB20_N3 5 5
USB20_P3 4 10K_0402_5%
19 USB20_P3 4
3 @2 near JBT1.8
TP1 LEC 3
2
1

2 USB_EN#
1 1
1
1

JFE1 D
@ 27 USB_EN USB_EN 2 Q4
C315 G SSM3K7002FU_SC70-3
10U_0805_10V 2 S
3

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 29 of 48

hexainf@hotmail.com
5 4 3 2 1

U16 +1.8VS_CB
1 5 R1376
+3VALW VIN VOUT

2
2 61.9K +-1% 0402
GND
36,43 SUSP# 3 EN FB 4

1U_0402_6.3V6K~D
RT9043-GB_SOT23-5~D

1
2
1
+1.8VS_CB R1394 1

C218
R1375 10K_0402_5%

2
1 2 +1.8PE_VCCA C217
0_0402_5% 2 22U_0805_6.3V6M~D

1
@ 2 100K_0402_5%
R1392

4.7U_0805_10V4Z

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V
1 1 1

1
D D

C1746

C1747

C1748

C1771

0_0402_5%
2 2 2

R1027
1
@

Q129
AO3413_SOT23 +1.8VS_CB

+VCCA_OUT
S

D
+1.8V 3 1 @

0.01U_0402_16V7K

4.7U_0805_10V4Z

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V
R1377
G

1 1 1
2

36,43 SUSP 1 2

C1750

C1751

C1752

C1753
100K_0402_5% 1 U46
@ R1379
2 2 2
C1754

@ 1 2
0_0402_5% 7 33 IEEE1394_TPBN0
2 @ PE_VCCA 1394_TPBN IEEE1394_TPBP0
14 PE_VCCA 1394_TPBP 34
17 PE_VCCA
+3VS 36 IEEE1394_TPAN0 Layout Note: Place close to
1394_TPAN IEEE1394_TPAP0

+VCCD_OUT
1 37
VCCA_OUT
POWER 1394_TPAP OZ888 and Shield GND.
4 38 IEEE1394_TPBIAS0
CORE_VCCD 1394_TPBIAS C1745

0.1U_0402_16V

0.1U_0402_16V

4.7U_0805_10V4Z
18 CORE_VCCD
+3VS_PHY 1 1 24 CORE_VCCD IEEE1394 1394_XI 42 OZ888XI 2 1 OZ888XI
0_0603_5% 41 43 OZ888XO
CORE_VCCD 1394_XO
C1757

C1756

C1755
1 2 64 R1378
+3VS CORE_VCCD 22P_0402_50V8J

2
R1381 39 1 2 +3VS_CR X3
2 2 1394_REF 5.9K_0402_1%
20 VCCD_OUT
0.1U_0402_16V

0.1U_0402_16V

4.7U_0805_10V4Z

28 VCCD_OUT MMI_VCC 26

4.7U_0805_10V4Z
1 1 24.576MHz_16P_3XG-24576-43E1
C1749

1
44 3.3VCCD
C1760

C1761

C1762

27 25 XD_CD# 2 1 1 2 OZ888XO
3.3VCCD MMI_XD_CD#

C1772
+3VS_PHY 19 29 MS_CD# 0_0402_5% R1408
2 2 3.3VCCD MMI_MS_CD# SD_CD#
C
MMI_SD_MMC_CD# 30 22P_0402_50V8J
C
2 3.3VCCA
40 45 MSCLK_XDCE#
3.3VCCA MS_CLK/XD_CE# SD_CLK
35 3.3VCCA SD_MMC_CLK 46
61 MMI_WPI#
R1380 MMI_WPI#
1 2+PE_3.3VCCA 3 PE_3.3VCCA MMI_XD_WPO 63 MMI_XD_WPO
0_0603_5% C1758 4.7U_0805_10V4Z 62 XD_RE#
R1393 1 MMI_XD_RE# XD_RB#
2 0_0402_5% MMI_XD_RB# 23
C1759 0.1U_0402_16V @ 22 XD_CLE
R1391 1 MMI_XD_CLE SD_CMD
1 2 2 0_0402_5%11 PLL_REF_RETURN SD_MMC_CMD 48
R1382 1.2K_0402_1% 21 XD_WE#
MMI_XD_WE# MSBS_XDALE
2 1 9 PE_RTERM2 MS_BS/XD_ALE 47

5.1K_0402_1% 2 R1383 1 10 49 MMC_XD_D7


PE_RTERM1 MMC_MS_XD_D7 MMC_XD_D6
MMC_MS_XD_D6 50
12 51 MMC_XD_D5
19 PCIE_TXP5 PE_RXP MMC_MS_XD_D5 +3VS_CR
13 52 MMC_XD_D4
19 PCIE_TXN5 PE_RXN MMC_MS_XD_D4
PCIe
19 PCIE_RXP5
C1763 2 1 0.1U_0402_16V 15 PE_TXP CardReader
+3VS C1764 2 1 0.1U_0402_16V 16 53 MS_XD_D3
19 PCIE_RXN5 PE_TXN MS_XD_D3
R1384 54 MMC_SD_D3 1 1 1
SD_MMC_D3 MS_XD_D2
1 2 15 CLK_PCIE_MEDIA 5 PE_REFCLKP MS_XD_D2 55
10K_0402_5% 6 56 MMC_SD_D2 C1768 C1767 C1765
15 CLK_PCIE_MEDIA# PE_REFCLKN SD_MMC_D2
57 MS_XD_D1 1U 10V Z Y5V 0603 1U 10V Z Y5V 0603 1U 10V Z Y5V 0603
MS_XD_D1 MMC_SD_D1 2 2 2
15 MEDIA_REQ#32 32 PE_CLKREQ# SD_MMC_D1 58
59 MS_XD_D0
MS_XD_D0 MMC_SD_D0
7,17,27,31 PLT_RST# 31 PE_RST# SD_MMC_D0 60

65 DGND AGND 8
GND

OZ888GS0L1N_QFN64_8X8

B B

+3VS_CR +3VS_CR

IEEE1394_TPBIAS0 JSD1
3 XD-VCC SD-VCC 21
1U_0402_6.3V6K

MS-VCC 28
1

1
56.2_0402_1%

56.2_0402_1%

1 MS_XD_D0 R1387 1 2 0_0402_5% XDD0 32 XD-D0


R1385

R1386

C1770

MS_XD_D1 R1388 1 2 0_0402_5% XDD1 10 7 IN 1 CONN 20 SDCLK R1093 1 2 22_0402_5% SD_CLK


MS_XD_D2 R1389 1 0_0402_5% XDD2 XD-D1 SD_CLK SDDAT0 R1409 1 0_0402_5% MMC_SD_D0
2 9 XD-D2 SD-DAT0 14 2
MS_XD_D3 R1390 1 2 0_0402_5% XDD3 8 12 SDDAT1 R1410 1 2 0_0402_5% MMC_SD_D1
2 MMC_XD_D4 R1425 1 0_0402_5% XDD4 XD-D3 SD-DAT1 SDDAT2 R1411 1 0_0402_5% MMC_SD_D2
2 7 30 2
2

MMC_XD_D5 R1428 1 0_0402_5% XDD5 XD-D4 SD-DAT2 SDDAT3 R1412 1 0_0402_5% MMC_SD_D3
2 6 XD-D5 SD-DAT3 29 2
MMC_XD_D6 R1426 1 2 0_0402_5% XDD6 5 27 MMC_D4 R1413 1 2 0_0402_5% MMC_XD_D4
MMC_XD_D7 R1427 1 0_0402_5% XDD7 XD-D6 SD-DAT4 MMC_D5 R1414 1 0_0402_5% MMC_XD_D5
2 4 XD-D7 SD-DAT5 23 2
18 MMC_D6 R1415 1 2 0_0402_5% MMC_XD_D6
J139A1 XD_WE# R1395 1 0_0402_5% XDWE SD-DAT6 MMC_D7 R1416 1 0_0402_5% MMC_XD_D7
2 34 XD-WE SD-DAT7 16 2
IEEE1394_TPAP0 4 5 MMI_XD_WPO R1396 1 2 0_0402_5% XDWP 33
IEEE1394_TPAN0 TPA+ GND MSBS_XDALE R1397 1 0_0402_5% XD_ALE XD-WP SDCD R1398 1 SD_CD#
3 TPA- GND 6 2 35 XD-ALE SD-CD 1 2 0_0402_5%
IEEE1394_TPBP0 2 7 XD_CD# R1399 1 2 0_0402_5% XDCD 40 2 SDWP R1417 1 2 0_0402_5% MMI_WPI#
IEEE1394_TPBN0 TPB+ GND XD_RB# R1402 1 0_0402_5% XDRB XD-CD SD-WP SDCMD R1418 1 SD_CMD
1 TPB- GND 8 2 39 XD-R/B SD-CMD 25 2 0_0402_5%
XD_RE# R1403 1 2 0_0402_5% XDRE 38
SUYIN_020204FR004S506ZL~D MSCLK_XDCE# R1404 1 0_0402_5% XDCE XD-RE MSCLK R1419 1 MSCLK_XDCE#
2 37 XD-CE MS-SCLK 26 2 22_0402_5%
conn@ XD_CLE R1405 1 2 0_0402_5% XDCLE 36 13 MSBS R1420 1 2 0_0402_5% MSBS_XDALE
XD-CLE MS-BS
1

1
56.2_0402_1%

56.2_0402_1%

22 MSINS R1406 1 2 0_0402_5% MS_CD#


MS-INS
R1401 R1400 11 17 MSDATA0 R1421 1 2 0_0402_5% MS_XD_D0
7in1-GND MS-DATA0 MSDATA1 R1422 1 0_0402_5% MS_XD_D1
31 7in1-GND MS-DATA1 15 2
41 19 MSDATA2 R1423 1 2 0_0402_5% MS_XD_D2
2

7in1-GND MS-DATA2 MSDATA3 R1424 1 0_0402_5% MS_XD_D3


42 7in1-GND MS-DATA3 24 2
5.1K_0402_1%

270P_0402_50V7K
2

2 TAITW_R015-A10-LM
R1407 C1769
All DATA spacing=8mil, CLK spacing=15mil
A
1 A
1

Layout Note: Place close to OZ888 Chipset.

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/1/3 Deciphered Date 2009/01/3 Title
SCHEMATIC, M/B LA-4232P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 30 of 48
5 4 3 2 1
5 4 3 2 1

U59A U59C
PEG_NRX_GTX_P[0..15] VGA_LVDSAC+ AC4 G4
9 PEG_NRX_GTX_P[0..15] 16 VGA_LVDSAC+ IFPA_TXC IFPC_AUX
PEG_NTX_GRX_P0 AE12 Part 1 of 5 N1 16 VGA_LVDSAC- VGA_LVDSAC- AD4 Part 3 of 5 G5
PEG_NRX_GTX_N[0..15] PEG_NTX_GRX_N0 PEX_RX0 GPIO0 VGA_LVDSA0+ IFPA_TXC_N IFPC_AUX_N
9 PEG_NRX_GTX_N[0..15] AF12 PEX_RX0_N GPIO1 G1 16 VGA_LVDSA0+ V5 IFPA_TXD0 IFPC_L0 P4
PEG_NTX_GRX_P1 AG12 C1 NV_INVTPWM PAD T145 16 VGA_LVDSA0- VGA_LVDSA0- V4 N4
PEG_NTX_GRX_N1 PEX_RX1 GPIO2 VGA_LVDDEN VGA_LVDSA1+ IFPA_TXD0_N IFPC_L0_N
AG13 PEX_RX1_N GPIO3 M2 VGA_LVDDEN 16 16 VGA_LVDSA1+ AA5 IFPA_TXD1 IFPC_L1 M5
PEG_NTX_GRX_P[0..15] PEG_NTX_GRX_P2 AF13 M3 G7X_ENBKL VGA_LVDSA1- AA4 M4
9 PEG_NTX_GRX_P[0..15] PEX_RX2 GPIO4 G7X_ENBKL 16 16 VGA_LVDSA1- IFPA_TXD1_N IFPC_L1_N
PEG_NTX_GRX_N2 AE13 K3 GPU_VID0 For Internal Thermal VGA_LVDSA2+ W4 L4
PEX_RX2_N GPIO5 GPU_VID0 42 16 VGA_LVDSA2+ IFPA_TXD2 IFPC_L2
PEG_NTX_GRX_N[0..15] PEG_NTX_GRX_P3 AE15 K2 GPU_VID1 Sensor VGA_LVDSA2- Y4 K4
9 PEG_NTX_GRX_N[0..15] PEX_RX3 GPIO6 GPU_VID1 42 16 VGA_LVDSA2- IFPA_TXD2_N IFPC_L2_N
PEG_NTX_GRX_N3 AF15 J2 MEM_VID PAD R1131 2 1 VGA@ +3VS AB4 H4
PEX_RX3_N GPIO7 IFPA_TXD3 IFPC_L3

DVO / GPIO

MXM/DVI/DP
PEG_NTX_GRX_P4 AG15 C2 VGA_THER T150 10K_0402_5% AB5 J4
PEX_RX4 GPIO8 VGA_THER 27 IFPA_TXD3_N IFPC_L3_N
PEG_NTX_GRX_N4 AG16 M1 THER_ALERT# AB3
PEX_RX4_N GPIO9 THER_ALERT# IFPB_TXC
PEG_NTX_GRX_P5 AF16 D2 MEM_VREF MEM_VREF 32 2 1 +3VS AB2 R5 1 2
PEX_RX5 GPIO10 IFPB_TXC_N IFPC_RSET

LVDS
D PEG_NTX_GRX_N5 AE16 D1 R1130 10K_0402_5% W1 R720 1K_0402_1%~D D
PEG_NTX_GRX_P6 PEX_RX5_N GPIO11 IFPB_TXD4
AE18 PEX_RX6 GPIO12 J3 VGA@ V1 IFPB_TXD4_N IFPE_AUX D3
PEG_NTX_GRX_N6 AF18 J1 W3 D4
PEG_NTX_GRX_P7 PEX_RX6_N GPIO13 IFPB_TXD5 IFPE_AUX_N
AG18 PEX_RX7 GPIO14 K1 W2 IFPB_TXD5_N IFPE_L0 F5
PEG_NTX_GRX_N7 AG19 F3 AA2 F4
PEG_NTX_GRX_P8 PEX_RX7_N GPIO15 IFPB_TXD6 IFPE_L0_N
AF19 PEX_RX8 GPIO16 G3 AA3 IFPB_TXD6_N IFPE_L1 E4
PEG_NTX_GRX_N8 AE19 G2 AB1 D5
PEG_NTX_GRX_P9 PEX_RX8_N GPIO17 DVI_MODE1 IFPB_TXD7 IFPE_L1_N
AE21 PEX_RX9 GPIO18 F1 T148PAD~D AA1 IFPB_TXD7_N IFPE_L2 C3
PEG_NTX_GRX_N9 AF21 F2 HDMI_DET1 T149PAD~D C4
PEG_NTX_GRX_P10 PEX_RX9_N GPIO19 IFPE_L2_N
AG21 PEX_RX10 2 1 AB6 IFPAB_RSET IFPE_L3 B3
PEG_NTX_GRX_N10 AG22 AD2 VGA_HSYNC VGA_HSYNC 16 @R1134
@R1134 1K_0402_5%~D B4
PEG_NTX_GRX_P11 PEX_RX10_N DACA_HSYNC VGA_VSYNC IFPE_L3_N
AF22 PEX_RX11 DACA_VSYNC AD1 VGA_VSYNC 16 A7 HDA_BCLK
PEG_NTX_GRX_N11 AE22 AE2 VGA_CRT_R VGA_CRT_R 16 B7 M6 1 @ 2

HDA
PEG_NTX_GRX_P12 PEX_RX11_N DACA_RED VGA_CRT_B HDA_SYNC IFPE_RSET R721 1K_0402_1%~D
AE24 PEX_RX12 DACA_BLUE AD3 VGA_CRT_B 16 A6 HDA_SDI
PEG_NTX_GRX_N12 AF24 AE3 VGA_CRT_G VGA_CRT_G 16 B6 C9 ROM_SCLK_GPU
PEG_NTX_GRX_P13 PEX_RX12_N DACA_GREEN DACA_RSET R132 2 HDA_SDO ROM_SCLK ROM_SI_GPU
AG24 PEX_RX13 DACA_RSET AE1 1 2 1 C6 HDA_RST_N ROM_SI A10
PEG_NTX_GRX_N13 AF25 AF1 DACA_VREF R1140 124_0402_1%~D 1 2 VGA@ 10K_0402_5% C10 ROM_SO_GPU
PEG_NTX_GRX_P14 PEX_RX13_N DACA_VREF C1272 ROM_SO
AG25 PEX_RX14 VGA@ C15 RFU0(NC) ROMCS_N B10
PEG_NTX_GRX_N14 AG26 F7 0.1U_0402_16V D15
PEG_NTX_GRX_P15 PEX_RX14_N DACB_RED RFU1(NC) STRAP0
AF27 PEX_RX15 DACB_BLUE E6 VGA@ J5 RFU2(NC) STRAP0 C7
PEG_NTX_GRX_N15 STRAP1
AE27 PEX_RX15_N DACB_GREEN E7
F8
F6
J22
RFU3(NC) GENERAL STRAP1 B9
A9 STRAP2
DACB_RSET RFU4(NC) STRAP2

DACs
PEG_NRX_GTX_P0 C1273 1 2 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_P0 AD10 D6 L22 F10 STRAP_CAL_PU_GND0
PEG_NRX_GTX_N0 C1274 1 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_N0 PEX_TX0 DACB_CSYNC RFU5(NC) STRAP_CAL_PD_3V3(NC) STRAP_CAL_PU_GND1

PCI EXPRESS
2 AD11 PEX_TX0_N DACB_VREF G6 AG9 RFU6(NC) STRAP_CAL_PD_MIOB(NC) F11
PEG_NRX_GTX_P1 C1275 1 2 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_P1 AD12 AE9
PEG_NRX_GTX_N1 C1276 1 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_N1 PEX_TX1 RFU7(NC)
2 AC12 PEX_TX1_N DACC_HSYNC U6 SPDIF F9 2 1
PEG_NRX_GTX_P2 C1277 1 2 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_P2 AB11 U4 AA6 N5 R39 1K_0402_5%~D
PEG_NRX_GTX_N2 C1278 1 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_N2 PEX_TX2 DACC_VSYNC NC0 BUFRST_N
2 AB12 PEX_TX2_N DACC_RED T5 AC19 NC1
PEG_NRX_GTX_P3 C1279 1 2 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_P3 AD13 R4 E15 D9 D+ D+
PEG_NRX_GTX_N3 C1280 1 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_N3 PEX_TX3 DACC_BLUE NC2 THERMDP
2 AD14 PEX_TX3_N DACC_GREEN T4 T6 NC3 THERMDN D8 1
PEG_NRX_GTX_P4 C1281 1 2 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_P4 AD15 V6 +3VS C1283 @
PEG_NRX_GTX_N4 C1282 1 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_N4 PEX_TX4 DACC_RSET 2200P_0402_50V7K
2 AC15 PEX_TX4_N DACC_VREF R6
C PEG_NRX_GTX_P5 C1284 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_P5 NB9M-GS_BGA533~D C
PEG_NRX_GTX_N5 C1285 1
1 2
VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_N5
AB14 PEX_TX5 VGA_CLK_LCD 2 D-
Close to Sensor
2 AB15 PEX_TX5_N 1 2 VGA@ VGA@ D-
PEG_NRX_GTX_P6 C1286 1 2 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_P6 AC16 R1 VGA_DDCCLK VGA_DDCCLK 16 2.2K_0402_5% R142
PEG_NRX_GTX_N6 C1287 1 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_N6 PEX_TX6 I2CA_SCL VGA_DDCDATA VGA_DAT_LCD
2 AD16 PEX_TX6_N I2CA_SDA T3 VGA_DDCDATA 16 <---CRT 1 2 VGA@
PEG_NRX_GTX_P7 C1288 1 2 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_P7 AD17 R2 I2CB_CLK 2.2K_0402_5% R273
PEX_TX7 I2CB_SCL
PEG_NRX_GTX_N7 C1289 1 2 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_N7 AD18 PEX_TX7_N I2CB_SDA R3 I2CB_DA I2CB_CLK 1 2 VGA@ Strap pin define +3VS
PEG_NRX_GTX_P8 C1290 1 2 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_P8 AC18 A2 VGA_CLK_LCD VGA_CLK_LCD 16 2.2K_0402_5% R280
PEG_NRX_GTX_N8 C1291 1 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_N8 PEX_TX8 I2CC_SCL VGA_DAT_LCD I2CB_DA
2 AB18 B1 VGA_DAT_LCD 16<---LVDS 1 2 VGA@

I2C
PEG_NRX_GTX_P9 C1292 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_P9 PEX_TX8_N I2CC_SDA I2CD_CLK 2.2K_0402_5% R281
1 2 AB19 PEX_TX9 I2CD_SCL N2
PEG_NRX_GTX_N9 C1293 1 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_N9 I2CD_DA I2CD_CLK 2 VGA@

VGA@ 4.99K_0402_1%~D
2 AB20 PEX_TX9_N I2CD_SDA N3 1

1
10K_0402_5%
1K_0402_5%~D

1K_0402_5%~D

1K_0402_5%~D
PEG_NRX_GTX_P10 C1294 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_P10 I2CE_CLK 2.2K_0402_5% R282

45.3K_0402_1%~D
1 2 AD19 PEX_TX10 I2CE_SCL Y6

1
R1142

R1144
PEG_NRX_GTX_N10 C1295 1 2 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_N10 AD20 W6 I2CE_DA I2CD_DA 1 2 VGA@
PEX_TX10_N I2CE_SDA

R1143

R1145

R1146

R1147
PEG_NRX_GTX_P11 C1296 1 2 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_P11 AD21 A3 I2CH_CLK 2.2K_0402_5% R283
PEG_NRX_GTX_N11 C1297 1 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_N11 PEX_TX11 I2CH_SCL I2CH_DA 0_0402_5%~D I2CE_CLK
2 AC21 PEX_TX11_N I2CH_SDA A4 1 2 VGA@
PEG_NRX_GTX_P12 C1298 1 2 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_P12 AB21 T1 EC_SMB_CK2_R 1 2 2.2K_0402_5% R284

VGA@
EC_SMB_CK2 4,16,27

2
PEX_TX12 I2CS_SCL

VGA@
PEG_NRX_GTX_N12 C1299 1 2 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_N12 AB22 T2 EC_SMB_DA2_R R130 1 2 EC_SMB_DA2 4,16,27 I2CE_DA 1 2 VGA@ @ @ @

2
PEG_NRX_GTX_P13 C1300 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_P13 PEX_TX12_N I2CS_SDA R131 VGA@ 0_0402_5%~D 2.2K_0402_5% R285 STRAP0
1 2 AC22 PEX_TX13
PEG_NRX_GTX_N13 C1301 1 2 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_N13 AD22 AF3 PAD VGA@ I2CH_CLK 1 2 VGA@ STRAP1
PEX_TX13_N JTAG_TCK TP2
PEG_NRX_GTX_P14 C1302 1 2 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_P14 AD23 AG4 PAD 2.2K_0402_5% R286 STRAP2
PEX_TX14 JTAG_TDI TP3
PEG_NRX_GTX_N14 C1303 1 2 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_N14 AD24 AE4 PAD I2CH_DA 1 2 VGA@ ROM_SCLK_GPU
PEX_TX14_N JTAG_TDO TP4
PEG_NRX_GTX_P15 C1304 1 2 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_P15 AE25 AF4 PAD 2.2K_0402_5% R287 ROM_SI_GPU
PEX_TX15 JTAG_TMS TP5

TEST
PEG_NRX_GTX_N15 C1305 1 2 VGA@ 0.1U_0402_16V PEG_NRX_C_GTX_N15 AE26 AG3 PAD ROM_SO_GPU
PEX_TX15_N JTAG_TRST_N TP6
TESTMODE AD25 2 1
CLK_PCIE_VGA AB10 R1148 10K_0402_5%~D VGA@
15 CLK_PCIE_VGA PEX_REFCLK

1K_0402_5%~D
CLK_PCIE_VGA#

4.99K_0402_1%~D
15 CLK_PCIE_VGA# AC10 PEX_REFCLK_N PEX_TSTCLK_OUT AF10

1
10K_0402_5%

15K_0402_5%
1K_0402_5%~D
VGA@ AE10 1 2
PEX_TSTCLK_OUT_N
CLOSE TO GPU

@ R1151

VGA@ R1152

VGA@ R1154

@ R1155
30K_0402_5%

R1156
R1150 1 2 0_0402_5%~D AD9 R1149 200_0402_5% VGA@
7,17,27,30 PLT_RST# PEX_RST_N
Check reset timing

R1153
PEX_TERMP AG10 PEX_TERMP VGA@
34 XTALOUTBUFF XTALOUTBUFF E9 D10 1 2 VGA_CRT_R 1 2 VGA@ @
CLK_NV_27M 15

2
XTALOUTBUFF XTALIN R1197 0_0402_5%~D R1161 150_0402_5%~D @
34 XTALSSIN
@ 1 2XTALSSIN_R D11 XTALSSIN
CLK XTALOUT E10 VGA_CRT_G 1 2 VGA@
B R1158 1 2 0_0402_5%~D R1162 150_0402_5%~D B
15 CLK_NVSS_27M
R1159 VGA@ 0_0402_5%~D VGA_CRT_B 1 2 VGA@
NB9M-GS_BGA533~D R1164 150_0402_5%~D R1155 for X76 control
STRAP_CAL_PU_GND0 1 2 VGA@
Resistor Multilevel Tied to VCC Tied to Ground
VGA@ R1168 40.2K_0402_1% Each strap pin represents a 4 bit value
STRAP_CAL_PU_GND1 Value
1 2 VGA@
R1169 40.2K_0402_1% Pullup or Pulldown configures the MSB 3 Kohms Y 1000 0000
Y5 6 Kohms Y 1001 0001
4 3 Resistor Value determines the 3 LSBs 12 Kohms Y 1010 0010
GND OUT
24 Kohms Y 1011 0011
1 2 Resistor range is R*n 48 Kohms Y 1100 0100
IN GND
96 Kohms Y 1101 0101
1 2 PEX_TERMP 1 27MHZ_16PF_X7T027000BG1H-V~D
1 where n is 0-9 and R is 5K ohm. 192 Kohms Y 1110 0110
R1160 2.49K_0402_1% VGA@ C616 @ C617 284 Kohms Y 1111 0111
2 Kohms* N 1xxx 0xxx
18P_0402_50V8J 18P_0402_50V8J
2 2 @
@

CLOSE TO VGA PIN D10,E10

+3VS

External Thermal sensor


1

R79
200_0402_5%
C197 @ @
A 0.1U_0402_16V U7 A
2

2 1 1 VCC 8 EC_SMB_CK2_R
SCLK
D+ 2 7 EC_SMB_DA2_R
D+
D-
DXP SDA
THER_ALERT#
DELL CONFIDENTIAL/PROPRIETARY
D- 3 DXN ALERT# 6

VGA_THER 4 OVERT# GND 5 Compal Electronics, Inc.


PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
MAX6649MUA+T_UMAX8~D TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
@ BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATIC, M/B LA-4232P
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. C
401593
Date: Saturday, June 06, 2009 Sheet 31 of 48
5 4 3 2 1

hexainf@hotmail.com
5 4 3 2 1

FBAD[0:63]
FBAD[0:63] 35
FBAA[0..11]
DQMA#[0:7] FBAA[0..11] 35
D
DQMA#[0:7] 35 D
DQSA_WP[0:7] FBBA[2..5]
DQSA_WP[0:7] 35 FBBA[2..5] 35
DQSA_RN[0:7]
DQSA_RN[0:7] 35

U59B

FBAD0 D21 F26 FBAA4


FBAD7 FBAD0 FBA_CMD0 FBARAS#
C22 FBAD1 FBA_CMD1 J24 FBARAS# 35
FBAD6 B22 F25 FBAA5
FBAD4 FBAD2 Part 2 of 5 FBA_CMD2 FBA_BA1
A22 FBAD3 FBA_CMD3 M23 FBA_BA1 35
FBAD1 C24 N27 FBBA2
FBAD5 FBAD4 FBA_CMD4 FBBA4
B25 FBAD5 FBA_CMD5 M27
FBAD3 A25 K26 FBBA3
FBAD2 FBAD6 FBA_CMD6 FBA_BA2_CMD7
A26 FBAD7 FBA_CMD7 J25 1 2 FBA_BA2 FBA_BA2 35
FBAD10 D22 J27 FBACS0# R562 @ 0_0402_5%
FBAD8 FBA_CMD8 FBACS0# 35
FBAD12 E22 G23 FBAA11
FBAD9 FBAD9 FBA_CMD9 FBACAS#
E24 FBAD10 FBA_CMD10 G26 FBACAS# 35
FBAD15 D24 J23 FBAWE#
FBAD11 FBA_CMD11 FBAWE# 35
FBAD13 D26 M25 FBA_BA0
FBAD12 FBA_CMD12 FBA_BA0 35
FBAD8 D27 K27 FBBA5
FBAD11 FBAD13 FBA_CMD13 FBA_CS1
C27 FBAD14 FBA_CMD14 G25 FBA_CS1 35
FBAD14 B27 L24 FBA_RST_R 1 2 FBA_RST
FBAD15 FBA_CMD15 FBA_RST 35

1
FBAD16 D16 K23 FBAA7 R560 VGA@ 0_0402_5%
C FBAD20 FBAD16 FBA_CMD16 FBAA10 R571 C
E16 FBAD17 FBA_CMD17 K24
FBAD18 D17 G22 FBA_CKE 10K_0402_5%
FBAD18 FBA_CMD18 FBA_CKE 35
FBAD22 F18 K25 FBAA0 VGA@
FBAD19 FBA_CMD19

1
FBAD17 D20 H22 FBAA9

2
FBAD21 FBAD20 FBA_CMD20 FBAA6 R563
F20 FBAD21 FBA_CMD21 M26
FBAD19 E21 H24 FBAA2 10K_0402_5% R571 & R563 Pull-down for initialization
FBAD23 FBAD22 FBA_CMD22 FBAA8 VGA@
F21 F27

INTERFACE
FBAD29 C16
FBAD23 FBA_CMD23
J26 FBAA3 CKE & RESET/ODT

2
FBAD28 FBAD24 FBA_CMD24 FBAA1
B18 G24

MEMORY
FBAD30 FBAD25 FBA_CMD25
C18 FBAD26 FBA_CMD26 G27
FBAD31 D18 M24 FBA_BA2_CMD27 1 2 FBA_BA2
FBAD27 FBA_CMD27 FBA_BA2 35
FBAD27 C19 K22 SNN_FBA_CMD28 T152PAD~D R561 VGA@ 0_0402_5%
FBAD25 FBAD28 FBA_CMD28
C21 FBAD29
FBAD26 B21 D23 DQMA#0
FBAD24 FBAD30 FBADQM0 DQMA#1
A21 FBAD31 FBADQM1 C26
FBAD38 P22 D19 DQMA#2
FBAD36 FBAD32 FBADQM2 DQMA#3
P24 FBAD33 FBADQM3 B19
FBAD37 R23 T24 DQMA#4
FBAD39 FBAD34 FBADQM4 DQMA#5
R24 FBAD35 FBADQM5 T26
FBAD32 T23 AA23 DQMA#6
FBAD35 FBAD36 FBADQM6 DQMA#7
U24 FBAD37 FBADQM7 AB27
FBAD34 V23
FBAD33 FBAD38 DQSA_RN0
V24 FBAD39 FBADQS_RN0 B24
FBAD44 N25 D25 DQSA_RN1
FBAD45 FBAD40 FBADQS_RN1 DQSA_RN2
N26 FBAD41 FBADQS_RN2 E18
FBAD47 R25 A18 DQSA_RN3
FBAD46 FBAD42 FBADQS_RN3 DQSA_RN4
R26 FBAD43 FBADQS_RN4 R22
FBAD41 T25 R27 DQSA_RN5
FBAD42 FBAD44 FBADQS_RN5 DQSA_RN6
V26 FBAD45 FBADQS_RN6 Y24
FBAD43 V25 AA27 DQSA_RN7
FBAD40 FBAD46 FBADQS_RN7
V27 FBAD47
FBAD48 V22 A24 DQSA_WP0
B FBAD53 FBAD48 FBADQS_WP0 DQSA_WP1 +1.8VS B
W22 FBAD49 FBADQS_WP1 C25
FBAD50 W23 E19 DQSA_WP2
FBAD51 FBAD50 FBADQS_WP2 DQSA_WP3
W24 FBAD51 FBADQS_WP3 A19

1
1K_0402_1%~D
R1172
FBAD49 AA22 T22 DQSA_WP4
FBAD55 FBAD52 FBADQS_WP4 DQSA_WP5
AB23 FBAD53 FBADQS_WP5 T27
FBAD54 AB24 AA24 DQSA_WP6
FBAD52 FBAD54 FBADQS_WP6 DQSA_WP7
AC24 FBAD55 FBADQS_WP7 AA26 @
FBAD61 W25

2
FBAD62 FBAD56 FBA_VREF 10mil
W26 FBAD57 FB_VREF A16
FBAD59 W27 FBAD58

0.1U_0402_16V
FBAD57 AA25 F24 FBACLK0 FBACLK0 35
FBAD59 FBA_CLK0

1
1K_0402_1%~D
R1173
FBAD60 AB25 F23 FBACLK0# FBACLK0# 35 1
FBAD60 FBA_CLK0_N

R84 2K_0402_5%
FBAD58 AB26 N24 FBACLK1 FBACLK1 35
FBAD61 FBA_CLK1

C1310
FBAD56 AD26 N23 FBACLK1# FBACLK1# 35
FBAD63 FBAD62 FBA_CLK1_N
AD27 FBAD63 FBA_DEBUG M22 T153PAD~D @
2
2 1 +1.8VS

2
VGA@ R1174 @
NB9M-GS_BGA533~D 10K_0402_5%~D @1

D
MEM_VREF 2
31 MEM_VREF G Q28
S SSM3K7002FU_SC70-3
3

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATIC, M/B LA-4232P
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. C
401593
Date: Saturday, June 06, 2009 Sheet 32 of 48
5 4 3 2 1
5 4 3 2 1

Place near GPU


PEX_IOVDD = 500mA
+1.1V_GFX_PCIE
PEX_IOVDDQ = 1600mA

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

4.7U_0603_6.3V4Z~D

4.7U_0603_6.3V4Z~D

22U_0805_6.3V6M

22U_0805_6.3V6M
D D

1 1 1 1 1 1 1

C916
C917
C1313

C1314

C1327

C1315

C1316
+VGA_CORE 2 2 2 2 2 2 2

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@
Place near Balls U59D

J10 VDD_0 PEX_IOVDD_0 AC9


J12 Part 4 of 5 AD7
VDD_1 PEX_IOVDD_1

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D
J13 VDD_2 PEX_IOVDD_2 AD8
J9 VDD_3 PEX_IOVDD_3 AE7
L9 AF7 +1.1V_GFX_PCIE
1 1 1 VDD_4 PEX_IOVDD_4
M11 AG7 PEX_PLLVDD = 100mA VGA@ +1.1V_GFX_PCIE
VDD_5 PEX_IOVDD_5

C1422

C1423

C1424
M17 VDD_6 PEX_IOVDDQ_0 AB13 10 mil
M9 AB16 +PEX_PLLVDD 2 1
2 2 2 VDD_7 PEX_IOVDDQ_1

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

0.1U_0402_16V

0.01U_0402_16V7K

1U_0402_6.3V6K~D

4.7U_0603_6.3V4Z~D
N11 AB17 L101
VDD_8 PEX_IOVDDQ_2 10NH_LQG15HS10NJ02D_5%_0402~D
N12 VDD_9 PEX_IOVDDQ_3 AB7
N13 VDD_10 PEX_IOVDDQ_4 AB8 1 1 1 1 1 1 1 1 1 1
VGA@ VGA@ VGA@ N14 AB9
VDD_11 PEX_IOVDDQ_5

C1325

C1311

C1312

C193

C194

C195

C1317

C1318

C1319

C1320
N15 VDD_12 PEX_IOVDDQ_6 AC13
N16 VDD_13 PEX_IOVDDQ_7 AC7
2 2 2 2 2 2 2 2 2 2

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@
N17 VDD_14 PEX_IOVDDQ_8 AD6
0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

VGA@

VGA@

VGA@

VGA@
N19 VDD_15 PEX_IOVDDQ_9 AE6
N9 VDD_16 PEX_IOVDDQ_10 AF6
1 1 1 1 1 P11 VDD_17 PEX_IOVDDQ_11 AG6 Place near Balls
P12 VDD_18
C161

C162

C180

C188

C192
P13 VDD_19 PEX_PLLVDD AF9 +PEX_PLLVDD
2 2 2 2 2
P14 VDD_20 +1.8VS
Place near Balls Place near GPU
VGA@

VGA@

VGA@

VGA@

VGA@
P15 VDD_21 VDD_SENSE W15 GPU_VDD_SENSE 42
P16 VDD_22
P17 VDD_23 FBVDDQ_0 A13

4.7U_0603_6.3V4Z~D
R11 VDD_24 FBVDDQ_1 B13

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
C C
R12 VDD_25 FBVDDQ_2 C13
+1.1V_GFX_PCIE
FB_PLLVDD = 40 mA R13 VDD_26 FBVDDQ_3 D13
L102 R14 D14 1 1 1 1 1 1 1 1
BLM18AG121SN1D_0603~D VDD_27 FBVDDQ_4
R15 E13

POWER
VDD_28 FBVDDQ_5
0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K

C1365

C1366

C1367

C1368

C1343

C1344

C1347

C1346
1 2 +FB_PLLVDD R16 F13
VGA@ VDD_29 FBVDDQ_6
R17 VDD_30 FBVDDQ_7 F14
2 2 2 2 2 2 2 2
0.01U_0402_16V7K

1 1 1 1 1 1 1 1 1 R9 VDD_31 FBVDDQ_8 F15


IFPAB_PLLVDD = 100 mA +1.8VS
4.7U_0603_6.3V6M~D

1U_0402_6.3V6K~D

0.1U_0402_16V

T11 F16 L105


VDD_32 FBVDDQ_9
C1425

C1430

C1431

C1432

C1433

C1434

C1435

C1436

C1437
T17 F17 BLM18AG121SN1D_0603~D
VDD_33 FBVDDQ_10 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ +IFPAB_PLLVDD
1 1 1 1 T9 VDD_34 FBVDDQ_11 F19 1 2
2 2 2 2 2 2 2 2 2
C1421

VGA@

VGA@

4700P_0402_25V7K~D
U19 F22 VGA@
VDD_35 FBVDDQ_12
C1353

C1354

C1355

470P_0402_50V7K~D

4.7U_0603_6.3V6M~D

4.7U_0603_6.3V6M~D
U9 VDD_36 FBVDDQ_13 H23
W10 VDD_37 FBVDDQ_14 H26
2 2 2 2 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ W12 VDD_38 FBVDDQ_15 J15 1 1 1 1
W13 VDD_39 FBVDDQ_16 J16

C1381

C1388

C1389

C1384
W18 VDD_40 FBVDDQ_17 J18
VGA@ VGA@ VGA@ VGA@ W19 J19
VDD_41 FBVDDQ_18 VGA@ 2 2 2 2
W9 VDD_42 FBVDDQ_19 L19
+3VS L23
FBVDDQ_20
A12 VDD33_0 FBVDDQ_21 L26
1U_0805_10V7K~D

0.1U_0402_16V

0.1U_0402_16V

B12 M19 VGA@ VGA@


VDD33_1 FBVDDQ_22
C12 VDD33_2 FBVDDQ_23 N22
2 1 1 D12 VDD33_3 FBVDDQ_24 U22
E12 VDD33_4 FBVDDQ_25 Y22
C1369

C1370

C1371

F12 VDD33_5 VGA@


V3 +IFPAB_IOVDD
1 2 2 IFPA_IOVDD +1.8VS
R49 +DACA_VDD AG2 DACA_VDD IFPB_IOVDD V2 1 2 IFPAB_IOVDD = 100mA L106
1 2 D7 J6 R77 10K_0402_5% VGA@ BLM18AG121SN1D_0603~D
VGA@ 10K_0402_5% +DACC_VDD W5 DACB_VDD IFPC_IOVDD +IFPAB_IOVDD
DACC_VDD IFPE_IOVDD H6 1 2 1 2

470P_0402_50V7K~D

4700P_0402_25V7K~D

4.7U_0603_6.3V6M~D
VGA@ VGA@ VGA@ R78 10K_0402_5% VGA@ VGA@
+FB_PLLVDD R19 AD5 +IFPAB_PLLVDD
FB_PLLAVDD IFPAB_PLLVDD
T19 FB_DLLAVDD IFPC_PLLVDD P6 1 2 1 1 1
B R63 10K_0402_5% VGA@ B
IFPE_PLLVDD N6

C1385

C1386

C1387
+1.8VS 1 2 FB_CAL_PD_VDDQ B15 FBCAL_PD_VDDQ
R1175 44.2_0402_1%~D K5 +GPU_PLLVDD VGA@
VGA@ PLLVDD 2 2 2
VID_PLLVDD K6
SP_PLLVDD L6

VGA@ VGA@
2 1 +DACC_VDD NB9M-GS_BGA533~D
R1176 10K_0402_5%~D
VGA@ VGA@

DACA VDD= 53mA


+3VS L104
BLM18AG121SN1D_0603~D
1 2 +DACA_VDD GPU_PLLVDD = 140 mA +1.1V_GFX_PCIE
VGA@
4.7U_0603_6.3V6M~D

4700P_0402_25V7K~D

470P_0402_50V7K~D

0.1U_0402_16V

+GPU_PLLVDD 1 2
L103

4.7U_0603_6.3V6M~D

0.1U_0402_16V

0.1U_0402_16V

0.1U_0402_16V

1U_0402_6.3V6K~D
1 1 1 1 BLM18AG121SN1D_0603~D
VGA@
C1377

C1378

C1379

C1372

1 1 1 1 1
2 2 2 2

C1390

C1375

C1374

C1380

C1376
2 2 2 2 2

VGA@ VGA@ VGA@ VGA@


VGA@ VGA@ VGA@ VGA@ VGA@

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATIC, M/B LA-4232P
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. C
401593
Date: Saturday, June 06, 2009 Sheet 33 of 48
5 4 3 2 1 hexainf@hotmail.com
5 4 3 2 1

D_C L50
BLM18AG121SN1D_0603~D
+3VS +3VL 1 2 +3VS

0.1U_0402_16V
-1.75% (DOWN) 0

10U_0805_10V
10K_0402_5%~D

10K_0402_5%~D
1 1

C870
D
±0.875% (CENTER) 1 @
D

R708

R709

C871
2 2
D_C Internal pull up
U45

2
31 XTALOUTBUFF 1 XIN/CLKIN XOUT 8
2 VSS VDD 7
3 D_C PD# 6
31 XTALSSIN 4 ModOUT REFCLK 5 @ @

1
@

10K_0402_5%~D

10K_0402_5%~D

0_0402_5%~D
P1819GF-08SR_SO8~D @

R710

R711

R712
@ @ @

2
@

U59E
AC11 GND_0
AC14 Part 5 of 5 L16
GND_1 GND_48
AC17 GND_2 GND_49 L17
C AC2 GND_3 GND_50 L2 C
AC20 GND_4 GND_51 L5
AC23 GND_5 GND_52 M12
AC26 GND_6 GND_53 M13
AC5 GND_7 GND_54 M14
AC8 GND_8 GND_55 M15
AF11 GND_9 GND_56 M16
AF14 GND_10 GND_57 P19
AF17 GND_11 GND_58 P2
AF2 GND_12 GND_59 P23
AF20 GND_13 GND_60 P26
AF23 GND_14 GND_61 P5
AF26 GND_15 GND_62 P9
AF5 GND_16 GND_63 T12
AF8 GND_17 GND_64 T13
B11 GND_18 GND_65 T14
B14 GND_19 GND_66 T15
B17 GND_20 GND_67 T16
B2 GND_21 GND_68 U11
B20 GND_22 GND_69 U12
B23 GND_23 GND_70 U13
B26 GND_24 GND_71 U14
B5 GND_25 GND_72 U15
B8 GND_26 GND_73 U16
GND

B E11 GND_27 GND_74 U17 B


E14 GND_28 GND_75 U2
E17 GND_29 GND_76 U23
E2 GND_30 GND_77 U26
E20 GND_31 GND_78 U5
E23 GND_32 GND_79 V19
E26 GND_33 GND_80 V9
E5 GND_34 GND_81 W11
E8 GND_35 GND_82 W14
H2 GND_36 GND_83 W17
H5 GND_37 GND_84 Y2
J11 GND_38 GND_85 Y23
J14 GND_39 GND_86 Y26
J17 GND_40 GND_87 Y5
K19 GND_41
K9 GND_42 RFU_GND AC6 Close to U44 pin W16
L11 GND_43
L12 W16 GND_SENSE 1 2
GND_44 GND_SENSE R707 0_0402_5%~D
L13 GND_45
L14 A15 FB_CAL_PU_GND 1 VGA@ 2
GND_46 FBCAL_PU_GND FB_CAL_TERM_GND R703 1
L15 GND_47 FBCAL_TERM_GND B16 2 30.9_0402_1%~D
R702 40.2_0402_1%~D
VGA@
NB9M-GS_BGA533~D
A VGA@ A
VGA@ DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATIC, M/B LA-4232P
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. C
401593
Date: Saturday, June 06, 2009 Sheet 34 of 48
5 4 3 2 1
5 4 3 2 1

FBAD[0..63]
+1.8VS 32 FBAD[0..63]
FBADQS#[0..7]
1 32 DQSA_RN[0:7]
DQSA_WP[0:7]

G11

G11
D12

D12
B12

P12

B12

P12
T12

T12
32 DQSA_WP[0:7]

L11

L11
G2

G2
D1
D4
D9

D1
D4
D9
R908

B1
B4
B9

P1
P4
P9

B1
B4
B9

P1
P4
P9
T1
T4
T9

T1
T4
T9
L2

L2
1.05K_0402_1% U51 U52 DQMA#[0..7]
VGA@ +VREFA2 32 DQMA#[0:7]

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
FBAA[0..11]
2

+VREFA0 32 FBAA[0..11]
FBAA0 K4 FBAA0 K4 FBBA[2..5]
A0 A0 32 FBBA[2..5]
1

1 FBAA1 H2 B2 FBAD1 FBAA1 H2 B2 FBAD40


R912 C933 FBAA2 A1 DQ0 FBAD3 FBBA2 A1 DQ0 FBAD41
K3 A2 DQ1 B3 K3 A2 DQ1 B3
2.49K_0402_1% 0.01U_0402_16V7K FBAA3 M4 C2 FBAD2 FBBA3 M4 C2 FBAD42 FBA_BA0
D A3 DQ2 A3 DQ2 32 FBA_BA0 D
VGA@ VGA@ FBAA4 K9 C3 FBAD5 FBBA4 K9 C3 FBAD43
2 FBAA5 A4 DQ3 FBAD7 FBBA5 A4 DQ3 FBAD44 FBA_BA1
H11 E2 H11 E2 32 FBA_BA1
2

FBAA6 A5 DQ4 FBAD4 FBAA6 A5 DQ4 FBAD45


K10 A6 DQ5 F3 K10 A6 DQ5 F3
FBAA7 L9 F2 FBAD0 FBAA7 L9 F2 FBAD46 FBA_BA2
A7 DQ6 A7 DQ6 32 FBA_BA2
FBAA8 K11 G3 FBAD6 FBAA8 K11 G3 FBAD47
FBAA9 A8/AP DQ7 FBAD16 FBAA9 A8/AP DQ7 FBAD35
M9 A9 DQ8 B11 M9 A9 DQ8 B11
FBAA10 K2 B10 FBAD17 FBAA10 K2 B10 FBAD34
+1.8VS FBAA11 A10 DQ9 FBAD18 FBAA11 A10 DQ9 FBAD32
L4 A11 DQ10 C11 L4 A11 DQ10 C11
FBA_BA0 G4 C10 FBAD19 FBA_BA0 G4 C10 FBAD33
FBA_BA1 BA0 DQ11 FBAD20 FBA_BA1 BA0 DQ11 FBAD39
G9 BA1 DQ12 E11 G9 BA1 DQ12 E11
1

F10 FBAD21 F10 FBAD36


R917 DQMA#0 DQ13 FBAD22 DQMA#5 DQ13 FBAD37
E3 DM0 DQ14 F11 E3 DM0 DQ14 F11
1.05K_0402_1% DQMA#2 E10 G10 FBAD23 DQMA#4 E10 G10 FBAD38
VGA@ +VREFA3 DQMA#3 DM1 DQ15 FBAD27 DQMA#6 DM1 DQ15 FBAD51
N10 DM2 DQ16 M11 N10 DM2 DQ16 M11
DQMA#1 N3 L10 FBAD25 DQMA#7 N3 L10 FBAD48
2

+VREFA1 DM3 DQ17 FBAD24 DM3 DQ17 FBAD53


DQ18 N11 DQ18 N11
DQSA_WP0 D2 M10 FBAD26 DQSA_WP5 D2 M10 FBAD50
WDQS0 DQ19 WDQS0 DQ19
1

1 DQSA_WP2 D11 R11 FBAD31 DQSA_WP4 D11 R11 FBAD52


R918 C924 DQSA_WP3 WDQS1 DQ20 FBAD28 DQSA_WP6 WDQS1 DQ20 FBAD49
P11 WDQS2 DQ21 R10 P11 WDQS2 DQ21 R10
2.49K_0402_1% 0.01U_0402_16V7K DQSA_WP1 P2 T11 FBAD30 DQSA_WP7 P2 T11 FBAD54
VGA@ VGA@ WDQS3 DQ22 FBAD29 WDQS3 DQ22 FBAD55
DQ23 T10 DQ23 T10
2 +VREFA0 FBAD10 +VREFA2 FBAD59
H1 M2 H1 M2
2

+VREFA1 VREF DQ24 FBAD12 +VREFA3 VREF DQ24 FBAD57


H12 VREF DQ25 L3 H12 VREF DQ25 L3
J2 N2 FBAD9 J2 N2 FBAD61
FBA_CS1 RFU1 DQ26 FBAD15 FBA_CS1 RFU1 DQ26 FBAD62
32 FBA_CS1 J3 RFU2 DQ27 M3 32 FBA_CS1 J3 RFU2 DQ27 M3
R2 FBAD8 R2 FBAD60
FBARAS# DQ28 FBAD13 FBARAS# DQ28 FBAD63
32 FBARAS# H3 RAS# DQ29 R3 H3 RAS# DQ29 R3
FBACAS# F4 T2 FBAD11 FBACAS# F4 T2 FBAD56
32 FBACAS# CAS# DQ30 CAS# DQ30
FBAWE# H9 T3 FBAD14 FBAWE# H9 T3 FBAD58
32 FBAWE# WE# DQ31 WE# DQ31
FBACS0# F9 FBACS0# F9
32 FBACS0# CS# CS#
FBA_CKE H4 A1 +1.8VS FBA_CKE H4 A1 +1.8VS
C 32 FBA_CKE CKE VDDQ CKE VDDQ C
FBACLK0 J11 A12 FBACLK1 J11 A12
FBACLK0# CK VDDQ FBACLK1# CK VDDQ
J10 CK# VDDQ C1 J10 CK# VDDQ C1
VDDQ C4 VDDQ C4
1 2 A4 ZQ VDDQ C9 1 2 A4 ZQ VDDQ C9
R919 243_0402_1% A9 C12 R920 243_0402_1% A9 C12
VGA@ MF VDDQ VGA@ MF VDDQ
VDDQ E1 VDDQ E1
DQSA_RN0 D3 E4 DQSA_RN5 D3 E4
DQSA_RN2 RDQS0 VDDQ DQSA_RN4 RDQS0 VDDQ
D10 RDQS1 VDDQ E9 D10 RDQS1 VDDQ E9
DQSA_RN3 P10 E12 DQSA_RN6 P10 E12
DQSA_RN1 RDQS2 VDDQ DQSA_RN7 RDQS2 VDDQ
P3 RDQS3 VDDQ J4 P3 RDQS3 VDDQ J4
VDDQ J9 VDDQ J9
+1.8VS A2 VDD VDDQ N1 +1.8VS A2 VDD VDDQ N1
A11 VDD VDDQ N4 A11 VDD VDDQ N4
F1 VDD VDDQ N9 F1 VDD VDDQ N9
F12 VDD VDDQ N12 F12 VDD VDDQ N12
M1 VDD VDDQ R1 M1 VDD VDDQ R1
M12 VDD VDDQ R4 M12 VDD VDDQ R4
V2 VDD VDDQ R9 V2 VDD VDDQ R9
V11 VDD VDDQ R12 V11 VDD VDDQ R12
VDDQ V1 VDDQ V1
V4 V12 +1.8VS V4 V12 +1.8VS
FBA_RST SEN VDDQ FBA_RST SEN VDDQ
32 FBA_RST V9 RESET V9 RESET
FBA_BA2 H10 K1 FBA_BA2 H10 K1
BA2 VDDA BA2 VDDA
VDDA K12 VDDA K12
1 1 1 1
J1 VSSA J1 VSSA
J12 C889 C890 J12 C891 C892
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA 0.1U_0402_16V 0.1U_0402_16V VSSA 0.1U_0402_16V 0.1U_0402_16V
VGA@2 2 VGA@ VGA@2 2 VGA@
K4J52324QE-BC14_FBGA136~D K4J52324QE-BC14_FBGA136~D
A3
A10
G1
G12
L1
L12
V3
V10

A3
A10
G1
G12
L1
L12
V3
V10
@ @

B B

+1.8VS GDDR3 BGA MEMORY +1.8VS GDDR3 BGA MEMORY

0.01U_0402_16V7K 0.1U_0402_16V 0.1U_0402_16V 1U_0402_6.3V4Z 10U_0805_10V 0.01U_0402_16V7K 0.1U_0402_16V 0.1U_0402_16V 1U_0402_6.3V4Z 10U_0805_10V
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C894 C895 C896 C897 C898 C899 C900 C901 C902 C903 C904 C905 C906 C907 C908 C909 C910 C911 C912 C913 C914 C915
VGA@
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1000P_0402_50V7K 0.01U_0402_16V7K 0.1U_0402_16V 0.1U_0402_16V 1U_0402_6.3V4Z 22U_0805_6.3V6M 1000P_0402_50V7K 0.01U_0402_16V7K 0.1U_0402_16V 0.1U_0402_16V 1U_0402_6.3V4Z 22U_0805_6.3V6M

FBACLK1
32 FBACLK1

2
R610
FBACLK0 475_0402_1%~D
32 FBACLK0
VGA@

1
2

A R607 FBACLK1# A
32 FBACLK1#
475_0402_1%~D
VGA@
1

FBACLK0#
32 FBACLK0#

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2007/02/12 Deciphered Date 2008/02/12
SCHEMATIC, M/B LA-4232P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 35 of 48
5 4 3 2 1 hexainf@hotmail.com
A B C D E

+3VALW to +3VS Transfer +5VALW to +5VS Transfer +1.8V to +1.8VS Transfer


+3VALW +3VS
+B+_BIAS +5VALW +5VS +1.8V +1.8VS
+B+_BIAS
4.7A
U40
8 1 10U_0805_10V U39 U41
1 D S 10U_0805_10V
7 D S 2 8 D S 1 8 D S 1

47K_0402_5%
R198 1 6 3 7 2 7 2
D S D S D S

R559
5 D G 4 1 1 1 6 D S 3 1 6 D S 3
330K_0402_5% C271 C465 C256 C278 5 4 1 1 VGA@ 5 4 1 1
SI4800DY_SO8 D G C284 C283 C727 D G C728 C697
2

1 2 10U_0805_10V SI4800DY_SO8 SI4800DY_SO8 1


VGA@

1
2 2 2 10U_0805_10V 10U_0805_10V 2 10U_0805_10V 0.1U_0402_16V
RUNON 3VS_GATE 2 2 VGA@ 2 2
1 2 VGA@ VGA@
R197 1 RUNON 1 2 1 5VS_GATE 0.1U_0402_16V
100K_0402_5% 0.1U_0402_16V R267 C279
C264 47K_0402_5%
1

D 0.01U_0402_25V7K~N 0.01U_0402_25V7K~N 1.8VS ON 1 1.8VS_GATE


2
SUSP 2 2 R608
2 1
G Q18 100K_0402_5%
S SSM3K7002FU_SC70-3 VGA@ C696
3

1
D 0.01U_0402_25V7K~N
VGA_PWGOD# 2 VGA@
2
G Q48
S SSM3K7002FU_SC70-3

3
SUSP 1 R665 2 VGA@
+CPU_CORE 1 2 +VCCP @ 0_0402_5%
C211 0.1U_0402_16V

2 +3VALW 2
1

R409

100K_0402_5%
2

SYSON#
1

D
SYSON 2 Q42
26,27,41 SYSON
G SSM3K7002FU_SC70-3
S
3
2

R365
10K_0402_5%
1

+5VALW

+1.1V_GFX_PCIE +VGA_CORE +1.8VS


1

R340

1
3 3

1
100K_0402_5% R647 R609
R646 470_0603_5% 470_0603_5%
2

SUSP 470_0603_5%
30,43 SUSP
VGA Discharge circuit VGA@
VGA@ VGA@

2
1

1 2
SUSP# 2 Q32
26,27,41,42,43 SUSP#

1
G SSM3K7002FU_SC70-3 D D D
2

S SUSP 2 SUSP 2 VGA_PWGOD# 2


3

G G G
S Q61 VGA@ S Q62 VGA@ S Q65 VGA@

3
R338 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3
10K_0402_5%
1

Discharge circuit-1 +1.8V +0.9VS +5VS +3VS +1.5VS


+1.8VS_CB
1

1
1

+5VALW +3VALW R133 R351 R391 R383 R382


R536 470_0603_5% 470_0603_5% 470_0603_5% 39_0603_5% 470_0603_5%
470_0603_5% @ @ @ @
1

@
2

2
1

R668
2

R551 VGA@
1

1
100K_0402_5% D D D D D
1

100K_0402_5% D SYSON# SUSP SUSP SUSP SUSP


2 2 2 2 2
2

VGA_PWGOD# SUSP 2 Q50 G G G G G


2

4 G SSM3K7002FU_SC70-3 S Q12 @ S Q33 @ S Q39 @ S Q38 S Q37 @ 4


3

3
1

D SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3


S @
3

VGA_PWGOD 2 Q49
42 VGA_PWGOD
G SSM3K7002FU_SC70-3
VGA@ S
3

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

SYSON -> SUSP# -> VGA_ON->VGA_PWGOD THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 36 of 48
A B C D E
5 4 3 2 1

D D
FD1 FD2 FD3 FD4 FD5 FD6 FD7 FD8
FIDUCAL FIDUCAL FIDUCAL FIDUCAL FIDUCAL FIDUCAL FIDUCAL FIDUCAL
@ @ @ @ @ @ @ @
1

1
H28
@ HOLEA
H_2P8X2P5N
1

H29
@ HOLEA
H_2P8X4P8N
1

H1 H2 H3 H25 H5 H6 H10 H21 H27


@ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA

H_2P8
1

1
C C

H12 H9 H11 H14 H8 H23 H13 H26


@ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA
H_2P8
1

H19 H22
H_3P3 @ HOLEA @ HOLEA
1

H4
H_3P8 @ HOLEA
1

B B

H15 H18 H16 H17


@ HOLEA @ HOLEA @ HOLEA @ HOLEA
H_4P3
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 37 of 48
5 4 3 2 1 hexainf@hotmail.com
5 4 3 2 1

ADPIN VIN

PL17
SMB3025500YA_2P
PJPDC1 PC156 PR188
1 1 2 @ 2200P_0402_50V7K~D @ 56K_0402_5%~D
1
2 2
3 3 1 2 1 2
4 4
5 5

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D
6 PR189
6

100P_0402_50V8J~D

100P_0402_50V8J~D

100P_0402_50V8J~D
7 @ 1M_0402_1%~N
GND

1
PC287

PC157

PC159
D D
GND 8 1 2

PC286

PC158

PC160
VIN
ACES_88299-0600 VS VIN

0.01U_0402_25V7K~D
@
@ @

1
@ PR191 @ PR192

1
PC161
PR190 10K_0402_5%~D 1K_0402_5%~D
82.5K_0402_1%~D 1 2 ACIN 19,27,39

2
PR193

2
8
PL16 @ 22K_0402_1%~D @
PU12A
FBM-L11-160808-601LMT 0603~D N41 1 2 N40 3

P
+
2 1 DOCK_PSID O 1

19.6K_0402_1%~D
0.1U_0402_16V7K~D
@ N35 2 -

1
@ @ @

1
PC162

PR194
@ LM393DR_SO8 PR195

4
PC163 PD1 10K_0402_5%~D
VIN 1000P_0402_50V7K~D RLZ4.3B_LL34

2
2

2
2
PD3 @ PR198
10K_0402_5%~D
PJP1 2 1
PD4
@ JUMP_43X118 RLS4148_LL34-2 RTCVREF

1 1
2 1 1 1 2 2
BATT+ 3.3V

8
PR203 PR204 @ PU12B
5

P
1SS355TE-17_SOD323-2 68_1206_5%~D 68_1206_5%~D +
O 7
6 -

G
2

2
PQ50 LM393DR_SO8
Vin Detector

4
C CHGRTCP TP0610K-T1-E3_SOT23-3 C
3 1 VS
0.22U_1206_25V7K~D

32.8 Max. typ. Min.


1

PR205 1 L-->H 18.234 17.841 17.449


PC164

100K_0402_5%~D PC165
0.1U_0603_25V7K~D H-->L 17.597 17.210 16.813
2

PR206
2

22K_0402_5%~D
28 51ON# 1 2
1

RTCVREF PR207
200_0805_5%
+5VALW +3VALW
PU14 BIT3021 SOT89 3P
2

3 OUT IN 2

DA204U_SOT323
1
4.7U_0805_6.3V6K~D
1

GND
PC166

PC167

2
PD5

2.2K_0402_5%~D
1U_0805_25V4Z~D @ PR208
2

1
1 2
2

2
0_0402_5%~D
B B

PR209
PR212

1
33_0402_5%~D

1
DOCK_PSID

S
1 3 1 2 PS_ID 27
PQ53
RHU002N06_SOT323-3

G
2
15K_0402_1%~D 100K_0402_1%~D
+5VALW

2
+5VALW

DA204U_SOT323
PR213
PJP2 PJP4

10K_0402_1%~D
@ JUMP_43X118 @ JUMP_43X118

2
PD6
+1.1V_GFX_PCIEP 1 1 2 2 +1.1V_GFX_PCIE 1 1 2 2

1
+1.5VS

PR214
+1.5VSP C
2 PQ54
PJP3 PJP6 B MMST3904-7-F_SOT323~D @

2
@ JUMP_43X118 @ JUMP_43X118 E

2
PR215
+5VALWP 1 1 2 2 +0.9VSP 1 1 2 2 +0.9VS

1
+5VALW @
1
PD7 PR216
PJP5 PJP8 SM24_SOT23 1 2 PSID_DISABLE# 27

1
@ JUMP_43X118 @ JUMP_43X118
1 1 @ 10K_0402_1%~D
2 2 +VCCPP 1 1 2 2 +VCCP

PJP7 PJP10
@ JUMP_43X118 @ JUMP_43X118
+3VALWP 1 1 2 2 +3VALW 1 1 2 2

PJP9 PJP23
A @ JUMP_43X118 @ JUMP_43X118 A

+1.8VP 1 1 2 2 +1.8V 1 1 2 2

PJP11
@ JUMP_43X118 PJP12
1 1 @ JUMP_43X118
2 2
+VGA_COREP 1 1 2 2 +VGA_CORE Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/10/1 Deciphered Date 2007/5/01 Title
PJP14
@ JUMP_43X118 SCHEMATIC, M/B LA-4232P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1 1 Size Document Number Rev
2 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 38 of 48
5 4 3 2 1
A B C D E

PQ55 PQ56 +B+


VIN FDS4435BZ_SO8 FDS4435BZ_SO8
PR217
8 1 1 8 0.015_2512_1%
D S S D

0.01U_0402_25V7K~D
7 2 2 7 PL19
D S S D CHG_B+
6 D S 3 3 S D 6 1 4 1 2

1
3.3_1210_5%~D 3.3_1210_5%~D
5 D G 4 4 G D 5

2
PC171

PC292

PC172

PC293

PC173
2 3 FBMA-L11-322513-151LMA50T_1210 PR218

0.1U_0603_25V7K~D
PC168 100K_0402_1%~D

2
PR339

0.01U_0402_25V7K~D

1
2

100K_0402_1%~D
PC274

CHGEN#

2
1

1000P_0402_50V7K~D

1000P_0402_50V7K~D
4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
PC170 PC175 PC177

1
2

5
6
7
8

1
0.01U_0603_50V7K~D

PC174

PR219
0.1U_0402_16V7K~D PU15 0.1U_0805_25V7K

1 2

1
1
1 2 1 28 1 2 PQ57 /BATDRV 1
CHGEN PVCC

2
1

4
3
2
1
PR272
PR220 FDS8884_SO8

2
PC178 PC176 2.2_0603_5%~D PQ58

S
S
S
G
0.1U_0603_25V7K~D 0.1U_0603_25V7K~D 27 1 2 4 FDS4435BZ_SO8

2
BTST

2
2

PR221

D
D
D
D
340K_0402_1%~D 2 26 DH_CHG
ACN HIDRV
2

3
2
1

5
6
7
8
PC169 ACP PR222

1
2.2U_0805_25V6K~D 4 25 LX_CHG PL18 0.02_2512_1%
1

ACDET ACDRV PH PD8 10UH_SIL1045RA-100PF_4.5A_30% BATT+


5 ACDET
2 1 1 2 1 2 1 4

10U_1206_25V6M~D

10U_1206_25V6M~D
ACSET RLS4148_LL34-2 PC179

REGN
2 3

680P_0603_50V7K~D
PR224 0.1U_0603_25V7K~D

5
6
7
8

1
PC310

PC181

PC273
PR223 115K_0402_1%

10U_1206_25V6M~D
54.9K_0402_1% 1 2 6 PQ59
+3VALW

PC180
ACSET

2
24

2
REGN

1
FDS6690AS_NL_SO8
1

1
PR225 PC183

1
1
PC182 100K_0402_1%~D 1U_0603_10V6K~D 4
0.01U_0402_25V7K~D

2
2

@ @

4.7_1206_5%~D
PR354
90W adapter 1 2 7 ACOP
PR226 PC184 23 DL_CHG

3
2
1

2
340K_0402_1%~D 0.47U_0603_16V7K~D LODRV
Icharge=(Vsrset/Vvdac)*(0.1/PR222)=3.3A CP setting
1

Iadapter=(Vacset/Vvdac)*(0.1/PR217)=3.1A PGND 22
OVPSET 8 PC185
OVPSET 0.1U_0402_16V7K~D
Input OVP : 22.3V
1 2
2 2
Input UVP : 16.98V 9 AGND LEARN 21 ACOFF 27
2

1
Fsw : 300KHz PR227
54.9K_0402_1% VREF PC186 PC187
20 CELLS 0.1U_0603_25V7K~D 0.1U_0603_25V7K~D

2
CELLS
1

10 VREF

1
PQ60 3

1
SI2301BDS-T1-E3_SOT23-3 PC188
1U_0603_10V6K~D PR372
VREF PR228 @ 0_0402_5%~D 19

2
100K_0402_1%~D SRP
CELLS GND 3 Cell

2
1 2 GATE
2 11 18
VDAC SRN
2

VREF 4 Cell
PR229 1 2 17
+3VALW BAT
1

47K_0402_1%~D PR373

1
PC189 0_0402_5%~D VADJ 12
0.1U_0603_25V7K~D VADJ PC190
1

ACSET 0.1U_0603_25V7K~D

2
CELLS 29
ACGOOD# TP
13 ACGOOD ICHG setting
1

D RTCVREF VREF
2 3cell/4cell# 45 PR231
G REGN 16 2 1 IREF 27
SRSET

2
S PQ61 /BATDRV 14 49.9K_0402_1%~D
3

BATDRV

1
SSM3K7002F_SC59-3

1
PR234 PR230 PR232
1

PC191 100K_0402_1%~D 100K_0402_1%~D


Cells selector PR51 IADAPT 15 1 2 100K_0402_1%~D
@0.01U_0402_25V7K~D

1
@ 0_0402_5%~D BQ24751ARHDR_QFN28_5X5 PR233

2
PR53 10_0603_5%~D ACIN 19,27,38
210K_0402_1%~D
2

1
3 VADJ D 3
27 CHGVADJ 1 2
27 ADP_I ACGOOD# 2 PQ62
1

G SSM3K7002F_SC59-3

1
PR54 S

3
499K_0402_1%~D PC192 IREF Current
100P_0402_50V8J~D

2
2

2.968V 3A
+COINCELL
PR235
PQ63 COIN RTC Battery
+B+ 1 2 3 TP0610K-T1-E3_SOT23-3
1 +B+_BIAS
VREF
1
470K_0402_5%~D

100_0805_5%~D 32.8 VREF


0.1U_0805_25V7M~D

PR1 PJP24 VREF


2

1
+5VALW 1K_0402_5%~D GATE
PR236

PC193 PR352

2
RTCVREF 200K_0402_1%~D
1

1
PR237
2

1
D
Z4012

100K_0402_1%~D
1

2
1
220K_0402_5%

1SS355_SOD323-2

PD9 +COINCELL 1 2 PR350 2 PQ83


+ -
2

100K_0402_1%~D G SSM3K7002F_SC59-3

1
PR238

3
1
D
CHGEN#
2

ACOFF 1 2 2 PQ82
2

1
+RTCVCC G SSM3K7002F_SC59-3 D
32.8
1

1
PQ64 D PC309 PQ65
S 27 FSTCHG 2

3
SUYIN_060003FA002G201NL~D .1U_0402_16V7K~D G SSM3K7002F_SC59-3
2
0.1U_0603_25V7K~D

G RHU002N06_SOT323-3 @ PR351 S

3
220K_0402_5%

S PD2 340K_0402_1%~D
3

1
2

BAT54CW_SOT323~D
2
1
PC194

PR239

1
4 PC1 4

27.4 1U_0603_10V4Z~D
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/10/1 Deciphered Date 2007/5/01 Title
SCHEMATIC, M/B LA-4232P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 39 of 48
A B C D E hexainf@hotmail.com
5 4 3 2 1

ISL6237_B+
ISL6237_B+
+B+
PJP20 PR240
@ JUMP_43X118 0_0805_5%
1 1 2 2 1 2

2200P_0402_50V7K~D

2200P_0402_50V7K~D
4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
VL

5
6
7
8
PC195

PC196

PC197

8
7
6
5

1
PC200
D D

PC198

PC199
2

1U_0603_10V6K~D
PQ67

2
2
PQ66 AO4466_SO8

2
AO4466_SO8 PC201

4.7U_0805_6.3V6K~D
4

1
PC202
4 0.1U_0603_25V7K~D

PC203
1
+5VALWP

3
2
1
1
2
3
PL21

7
PL20 PU16 PC207 2 1
1 2 1U_0603_10V6K~D 3.3UH_1164AY-3R3N-P3_7.5A_30%

LDO
VIN

VCC
+3VALWP

4.7_1206_5%~D
3.3UH_1164AY-3R3N-P3_7.5A_30% 33 19 1 2
TP PVCC

5
6
7
8

1
1

8
7
6
5

PR242
680P_0603_50V7K~D 4.7_1206_5%~D
DH3 26 15 DH5
UGATE2 UGATE1

PR241
PR243 PR245 PQ69
0_0402_5%~D

PQ68 2 1 BST3A 24 17 BST5A 2 1 AO4712_SO8


BOOT2 BOOT1
2

1 AO4712_SO8 0_0603_5%~D
0_0603_5%~D

2
2

2
PR244

61.9K_0402_1%~D
4

2
PC204 + 4 PC205 PC208

2
680P_0603_50V7K~D
0.1U_0603_25V7K~D 0.1U_0603_25V7K~D

1
1

PR246
330U_D3L_6.3VM_R25M LX3 25 16 LX5 1
1

2 PHASE2 PHASE1

PC206

PC209
3
2
1

2
+ PC210

1
2
3
DL3 23 18 DL5 330U_D3L_6.3VM_R25M

1
LGATE2 LGATE1
2
10K_0402_1%~D
2

PGND 22

2
PR247

C FB3 30 C
OUT2

10K_0402_1%~D
PR248
OUT1 10
VL 32
1

@ REFIN2

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 REF
PC211 0.22U_0603_10V7K~D
BYP 9
8 LDOREFIN @ PR249 0_0402_5%~D
Rds(on) = 15m ohm(max) ; Rds(on) = 12m ohm(typical) SKIP 29 2 1 VL
PR250 0_0402_5%~D
1 2
3.3VALWP PD10 PR251
20 NC POK2 28

Imax=6A VS RLZ5.1B_LL34 100K_0402_1%~D


POK 19
1 2 1 2 4 EN_LDO POK1 13 PR253
2
200K_0402_5%~D

255K_0402_1%
Iocp=9A
2
PR252

PC212 14 12 ILM1 2 1
0.22U_0603_25V7K~D EN1 ILIM1
PR255
1

27 31 ILIM2 2 1

GND
TON
1

EN2 ILIM2

NC
2
B 255K_0402_1% B

0_0402_5%~D
@ PR254 ISL6237IRZ-T_QFN32_5X5

21
VL 0_0402_5%~D
Rds(on) = 15m ohm(max) ; Rds(on) = 12m ohm(typical)
806K_0603_1%

PR256
2

1
PR257

2VREF_ISL6237 1

PR260

1
PR259
@ 47K_0402_5%~D
PC285
PR258
@
5VALWP
1

2 1 1 2 1U_0603_10V6K~D Imax=6A
2

2VREF_ISL6237 2
45 MAINPWON 0_0402_5%~D
0_0402_5%~D
0.047U_0402_16V7K~D

PC213
Iocp=9A
1

1
2

0.047U_0603_16V7K~D

PC214
2

PQ79
TP0610K-T1-E3_SOT23-3
@
1 3

PD16
1 2
1SS355TE-17_SOD323-2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/10/1 Deciphered Date 2007/05/30 Title
SCHEMATIC, M/B LA-4232P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 40 of 48
5 4 3 2 1
5 4 3 2 1

PC239 PC240

1
1U_0402_6.3V6K~D 1U_0402_6.3V6K~D

2
PGOOD1 PGOOD2 串1K電組 上@ 2
PR288
1 1
PR289
2
+5VALWP +5VALWP
2.2_0603_1%~D 2.2_0603_1%~D

PJP21 +5VALWP

1
@ JUMP_43X118 PC241 PC242
D D
1 1 0.1U_0603_25V7K~D 0.1U_0603_25V7K~D
+B+ 2 2
ISL6228_B+

2
1
PR290 2 PR291 2 PR292

680P_0402_50K X7R~D
470P_0402_50V8J~D
ISL6228_B+ 1 1 ISL6228_B+
1

1
PC290

PC291
1K_0402_1%~D 10_0603_1% 10_0603_1%
@
2

2
PC244
1000P_0402_50V7K~D PR294

1
PR293 18.2K_0402_1%~D
1000P_0402_50V7K~D 3.3K_0402_5%~D PR295 PC243 22K_0402_1%~D
90.9K_0402_1%~N 1000P_0402_50V7K~D
PR296

1
PC245
2 1 1 2

1
PR297

1
2 1
29

PGOOD1

FSET1

VIN1

VCC1

VCC2

VIN2

FSET2
68K_0402_1% GND_T

2
PR298 PR300 3.3K_0402_5%~D
1 2 8 FB1 PGOOD2 28 2 PR299 1 +5VALWP 34K_0402_1% PR301
1000P_0402_50V7K~D
PC246
6.34K_0402_1%~D 1K_0402_1%~D 2 1 1 2

1
@
ISL6228_B+ PR302
9 VO1 FB2 27 1 2

68K_0402_1%
4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
1

1
PC249

PC247

8
7
6
5

PC248 PR303
0.068U_0402_16V7K~D 10 26 1 2
D
D
D
D
2

PQ74 OCSET1 VO2


1 2
FDS6294_NL_SO8 24K_0402_1%~D
C C
2

G 4
PR305 VCCPP_EN 11 25
6.34K_0402_1%~D PR306 EN1 PU18 OCSET2 PR307
S
S
S

1 2 0_0402_5%~D
PL26 ISL6228HRTZ-T_QFN28_4X4 1 2 ISL6228_B+
1

1
2
3

1UH +-20% PCMB103E-1R0MS 20A 0_0603_5%~D SYSON 26,27,36


+VCCPP 1 2 LX_VCCPP 12 24 6800P_0402_25V7K~D
PHASE1 EN2 PC252

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
1

5
6
7
8

1
PC253

PC250
1 2 PC254
8
7
6
5

1 1 PR308 PQ75 1 2
4.7_1206_5%~D AO4456_SO8 @ 0.01U_0402_25V7K~D

2
+ +
PC308

PC251

UG_VCCPP 13
220U_D2_4VM

220U_D2_4VM

23 PQ76
UGATE1 PHASE2

2
AO4466_SO8 PR309
680P_0603_50V8J~D
2

4 24K_0402_1%~D
2 2 PR311
4
1

PC255

0_0603_5%~D
2 1 2 1BST_VCCPP
14 22 UG_1.8V 1 2

1
BOOT1 UGATE2 PL27
2

3
2
1
PR310
LGATE1

LGATE2
PC256 LX_1.8V 1 2
PGND1

PGND2

BOOT2
PVCC1

PVCC2
+1.8VP
1
2
3

1
0_0603_5%~D

220U_D2_4VM
0.1U_0402_16V7K~D
PR312 1.5UH_MPL73-1R5_9A_20%

5
6
7
8
DCR 2.51m ohm(max) 4.7_1206_5%~D 1
15

16

17

18

19

20

21
+

PC260
680P_0603_50V8J~D
VCCPP PC259

2
PQ77
Imax=9A PR313 AO4712_SO8 DCR 15m ohm(max)

1
2

PC261
+5VALWP +5VALWP BST_1.8V 1 2 1 2 4
1.8VP
2

2
2.2_0603_5%~D
Iocp=19.43A

2
0.1U_0402_16V7K~D
PC257 PC258 Imax=9A
1U_0402_6.3V6K~D 1U_0402_6.3V6K~D
1

3
2
1
Iocp=12.31A
LG_VCCPP LG_1.8V

B B
PR314
0_0402_5%~D
2 1 VCCPP_EN
26,27,36,42,43 SUSP#
0.01U_0402_25V7K~D
1

PC262
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/10/1 Deciphered Date 2007/5/01 Title
SCHEMATIC, M/B LA-4232P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5 4 3 2
Date: Saturday, June 06, 2009
1
Sheet 41 of
hexainf@hotmail.com
48
5 4 3 2 1

PC215 PC216

1
1U_0402_6.3V6K~D 1U_0402_6.3V6K~D
VGA@
PGOOD1 PGOOD2 串1K電組 上@ PR261 PR262

2
2.2_0603_1%~D 2.2_0603_1%~D
+5VALWP 2 1 1 2 +5VALWP

VGA@
PJP22 +5VALWP
@ JUMP_43X118

1
1 1 PC217 PC218
+B+ 2 2 0.1U_0603_25V7K~D 0.1U_0603_25V7K~D
ISL6228_B++
VGA@

2
1
D D
PR264
PR263 ISL6228_B++ 2 1 2 PR265 1 ISL6228_B++
1K_0402_1%~D 10_0603_1% 10_0603_1%
@ VGA@

2
PC220
1000P_0402_50V7K~D PR267

1
PR266 18.2K_0402_1%~D
1000P_0402_50V7K~D 2.2K_0402_5%~D PR268 PC219 22K_0402_1%~D VGA@
45.3K_0402_1%~D 1000P_0402_50V7K~D
PR269

1
PC221 VGA@
2 1 1 2

1
PR270

1
2 1
29

PGOOD1

FSET1

VIN1

VCC1

VCC2

VIN2

FSET2
68K_0402_1% GND_T

2
PR271 PR273 3.3K_0402_5%~D
1 2 8 28 80.6K_0402_1%~D 1000P_0402_50V7K~D
FB1 PGOOD2 VGA_PWGOD 36 PR274
PC222
17.8K_0402_1%~D VGA@ VGA@ VGA@
2 1 1 2

1
PR304 VGA@
ISL6228_B++ PR275 0_0603_5%~D
9 VO1 FB2 27 1 2 1 2 GPU_VDD_SENSE 33
40.2K_0402_1%~D
4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
1

1
PC225

PC223

VGA@
8
7
6
5

PC224
6800P_0402_25V7K~D 10 26 1 2
2

OCSET1 VO2

2
1 2
PQ70 PR276 PR277
AO4466_SO8 19.6K_0402_1%~D 10_0402_5%~D
2

4 VGA@ VGA@
C PR278 1.5V_EN 11 25 C

1
17.8K_0402_1%~D PR279 EN1 PU17 OCSET2 PR280
1 2 0_0402_5%~D
ISL6228HRTZ-T_QFN28_4X4 1 2 ISL6228_B++
1

1
2
3

PL23 0_0603_5%~D VGA@ VGA_ON 27

+1.5VSP 1 2 LX_1.5V 12 24
PHASE1 EN2 PC228 PC230

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
DCR 10m ohm(max)
1

5
6
7
8

1
PC229

PC226
1.5UH_MPL73-1R5_9A_20% 1 2 6800P_0402_25V7K~D
8
7
6
5
220U_D2_4VM

PR281
1 1 2 +VGA (1.15V)

D
D
D
D
4.7_1206_5%~D VGA@ 0.01U_0402_25V7K~D VGA@

2
+ Imax=11A
PC227

PQ71 UG_1.5V 13 23
UGATE1 PHASE2

2
AO4712_SO8 PR282
680P_0603_50V8J~D
2

4 PQ72 19.6K_0402_1%~D
2 PR284 G
4 VGA@ Iocp=15.08A
1

PC231

0_0603_5%~D FDS6294_NL_SO8

S
S
S
2 1 2 1BST_1.5V 14 22 UG_VGA 1 2 VGA@ VGA@ VGA@

1
BOOT1 UGATE2 VGA@ PL24
2

3
2
1
LGATE1

LGATE2
PC232 PR283 LX_VGA 1 2
PGND1

PGND2

BOOT2
PVCC1

PVCC2
+VGA_COREP
1
2
3

1
0.1U_0402_16V7K~D
0_0603_5%~D
DCR 15m ohm(max) PR285 1UH_MPL73-1R0_11A_20%

470U_D2E_2.5VM_R7M
1.5VP VGA@ 4.7_1206_5%~D VGA@ 1

5
6
7
8
15

16

17

18

19

20

21
Imax=5A +

VGA@
PC233
680P_0603_50V8J~D
D
D
D
D

2
PC234
PR286

1
2

PC237
Iocp=9.13A +5VALWP +5VALWP BST_VGA 2 1 1 2 VGA@

G
S
S
S
2

2
2.2_0603_5%~D 0.1U_0402_16V7K~D PQ73

4
3
2
1

2
PC235 PC236 VGA@ VGA@ FDS6676AS_SO8
1U_0402_6.3V6K~D 1U_0402_6.3V6K~D VGA@
1

1
VGA@

LG_1.5V LG_VGA

PR287

1
0_0402_5%~D
B B
2 1 1.5V_EN PR344
26,27,36,41,43 SUSP#

1
200K_0402_1%~D
PR349
0.01U_0402_25V7K~D
1

100K_0402_1%~D
PC238

VGA@

2
@ VGA@
2

2
1
PC294

1
820P_0402_50V7K~D

2
1

1
+3VS VGA@ PC297
820P_0402_50V7K~D

2
VGA@
PR343 PR348
2

+3VS

2
PR340 100K_0402_1%~D 27K_0402_1%~D
VGA@ 10K_0402_5%~D
VGA@ VGA@
1

2
VGA@ D VGA@
2 1 2 PQ80 PR345
31 GPU_VID0
G BSS138W-7-F_SOT323 10K_0402_5%~D

0.01U_0402_16V7K~D
100K_0402_5%~D
PR341 S VGA@

3
10K_0402_5%~D

1
1

1
D
PR342 1

PC295
2 1 2 PQ81
31 GPU_VID1
G BSS138W-7-F_SOT323

0.01U_0402_16V7K~D
100K_0402_5%~D
VGA@ VGA@ PR346 S VGA@

3
2 10K_0402_5%~D
0.90V 1.09V 1.17V
2

1
VGA@ 1
GPU_VID_0 0 0 1

PR347

PC296
GPU_VID_1 0 1 1
2 VGA@

2
VGA@
A A

output voltage adjustable network

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/10/1 Deciphered Date 2007/5/01 Title
SCHEMATIC, M/B LA-4232P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 42 of 48
5 4 3 2 1
5 4 3 2 1

+5VALW +1.5VS

PJP16
VGA@

2
@ JUMP_43X118

1U_0603_10V6K~D

2
1

PC263

1
D +1.8V D

1U_0603_10V6K~D
1

PC264

1
VGA@
PJP17

1
2
@ JUMP_43X118

6
PU19

2
5

VCNTL
VIN
7

2
POK
VOUT 3 +1.1V_GFX_PCIEP
PU20

1K_0402_1%~D

1U_0603_10V6K~D

1U_0603_10V6K~D
VOUT 4 1 VIN VCNTL 6 +3VALW
PR315

1
PC266

PC267

4.7U_0805_6.3V6K~D
1 2 8 EN FB 2 2 GND NC 5

1
26,27,36,41,42 SUSP#

VGA@

PR316

PC268
PC265

GND

1
0_0402_5%~D 9 VGA@ 3 7

2
VIN VREF NC

2
VGA@ APL5913-KAC-TRL_SO8 PR317 4 8

2
VGA@ 0.01U_0402_25V7K~D 1K_0402_1%~D VOUT NC
VGA@ 9

2
TP
1

PC269 APL5331KAC-TRL_SO8

2.61K_0402_1%~D
0.1U_0402_16V7K~D PR318
2

@ +0.9VSP

1
D

PR319
0_0402_5%~D

1U_0603_10V6K~D
VGA@ 1 2 2

1
29,30,36 SUSP

PC271
G PR320 PC270

2
S

2
1
PQ78

2
PC272
@

2
C 0.1U_0402_16V7K~D C
RHU002N06_SOT323-3 0.1U_0402_16V7K~D
1K_0402_1%~D

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/10/1 Deciphered Date 2007/05/30 Title
SCHEMATIC, M/B LA-4232P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 43 of 48
5 4 3 2 1 hexainf@hotmail.com
5 4 3 2 1

+5VS

2
5

5
PC112

CPU_VID6

CPU_VID5

CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0
PR142 +CPU_B+
PL13

27
VR_ON
2 1 1_0603_5%~D
FBMA-L18-453215-900LMA90T_1812
@ 1 2 +B+

1
5600P_0402_25V7K~D
1 1

100U_25V_M

100U_25V_M
10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D
1U_0603_10V6K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
D D

1
+ +

PC114

PC115

PC116

PC113

PC155
PR143 499_0402_1%~D

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D
1

1
PC118

PC119

PC311

PC312
1U_0603_10V6K~D
7,19 DPRSLPVR 1 2

1
PC117

PC120

2
PR144 0_0402_5%~D @ 2 2

2
5,7,18 H_DPRSTP# 1 2

5
PR1460_0402_5%~D

PR1470_0402_5%~D

PR1480_0402_5%~D

PR1490_0402_5%~D

PR1500_0402_5%~D

PR1510_0402_5%~D

PR1520_0402_5%~D
PR145 0_0402_5%~D

1
CLK_EN# 1 2

1
0_0402_5%~D
+3VS PR154 0_0402_5%~D PQ43

PR153
1 2 4 SI7686DP-T1-E3_SO8

2
+3VS

1U_0603_10V6K~D
PC122

2
1.91K_0402_1%~D
PL14 0.36UH +-20% SF-I104-R36 23A

1
PC121
PR155 0.22U_0603_10V7K~D

3
2
1
1 BOOT_CPU1 1 2 1 2 4 1 +CPU_CORE
2

PR156

4.7_1206_5%~D
PR157

5
6
7
8

5
6
7
8

3.65K_1206_1%
2.2_0603_5%~D 3 2

1
PR158
499_0402_1%~D

49

48

47

46

45

44

43

42

41

40

39

38

37

D
D
D
D

D
D
D
D

1
10K_0402_1%~D
PR159
PR161
2

PR160
1_0402_5%~D

3V3

CLK_EN#
GND

DPRSTP#

DPRSLPVR

VID6

VID5

VID4

VID3

VID2

VID1

VID0
VR_ON
1

680P_0603_50V8J~D
PQ44 PQ45

1 2

2
G

G
S
S
S

S
S
S
7,19,27 VGATE 1 36 FDS6676AS_SO8 PR162 @ 0_0402_5%~D

2
PGOOD BOOT1

PC123
5 H_PSI# 1 2

4
3
2
1

4
3
2
1

2
2 35 UGATE_CPU1 VSUM PC124
1U_0603_10V6K~D PC147 PR181 10K_0402_1%~D PSI# UGATE1
1 2

2
POW_MON 27 1 2 1 2 3 34 PHASE_CPU1 VCC_PRM
PMON PHASE1 ISEN1
C PR164 147K_0402_1%~D 4 33 0.22U_0603_16V7K~D C
RBIAS PGND1 FDS6676AS_SO8
1 2
VR_TT# 5 32 LGATE_CPU1 +CPU_B+
VR_TT# LGATE1

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D
PR165 @ 4.22K_0402_1% PH2

1
1 2 1 2 6 NTC PVCC 31

PC125

PC126

PC127
@ 100K_0603_1%_TH11-4H104FT 7 30 LGATE_CPU2

2
SOFT LGATE2 PQ46
1 2
@ 0.015U_0402_16V7K PC128 8 29 SI7686DP-T1-E3_SO8 @
0.068U_0603_50V7K~D PC129 OCSET ISL6266ACRZ-T_QFN48_7X7 PGND2
4
1 2 9 28 PHASE_CPU2
VW PHASE2
PR166 11.5K_0402_1%~D 10 27 UGATE_CPU2 PL15 0.36UH +-20% SF-I104-R36 23A
COMP UGATE2 PR167 PC130
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 4 1
PC131 FB BOOT2
1 2

5
6
7
8

5
6
7
8

1
DROOP

1000P_0402_50V7K~D 12 25 2.2_0603_5%~D
0.22U_0603_10V7K~D 3 2
FB2 NC
VDIFF

VSUM

ISEN2

ISEN1
VSEN

PR169 8.25K_0402_1%~D PR168


GND

D
D
D
D

D
D
D
D
VDD
RTN

DFB

1
VIN

4.7_1206_5%~D

3.65K_1206_1%
VO

1 2

1
10K_0402_1%~D
PR171
PR172

PR170
1 2 PU11 PQ47 PQ48
13

14

15

16

17

18

19

20

21

22

23

24

1 2
G

G
S
S
S

S
S
S
1_0402_5%~D
PC132 1000P_0402_50V7K~D

4
3
2
1

4
3
2
1

2
ISEN1 PC133 PR173 @ 0_0402_5%~D

2
ISEN2 680P_0603_50V8J~D 1 2

2
PR175 97.6K_0402_1%~D PC134 270P_0402_50V7K~D 1 2 +5VS
1

1 2 2 1 VSUM PC135
1

PR174 1_0603_5%~D 1 2
PR176 PC136
B 1K_0402_1%~D 1U_0603_10V6K~D 0.22U_0603_16V7K~D B
1 2
2

FDS6676AS_SO8 FDS6676AS_SO8
2

PC137 100P_0402_50V8J~D VCC_PRM


1

ISEN2
PR178
PR184 PR177 PC138 2200P_0402_50V7K~D
100K_0402_1%~D 1 2 1 2 1 2 +CPU_B+
1

@ 100_0402_1%~D
1 2 10_0603_5%~D
2

PC139
2

PR179 1K_0402_1%~D 0.1U_0603_25V7K~D


PC140 330P_0402_50V7K~D
5 VCCSENSE 1 2 1 2
VSUM
1

PR180 0_0402_5%~D
1

2.61K_0402_1%~D

PC141 PC142
330P_0402_50V7K~D
PR182

0.01U_0603_25V7K~D
2

1 2
5 VSSSENSE PR183 0_0402_5%~D
2
1

11K_0402_1%~D

PC143 180P_0402_50V8J~D
PR185

1 2
2

1 2 1 2 PH3
2

PR186 1K_0402_1%~D PR187 3.24K_0402_1%~D 10KB_0603_ERTJ1VR103J


PC144 0.068U_0603_50V7K~D
1

VCC_PRM 1 2
PC146 0.22U_0603_10V7K~D
A A
PC145 2 1 2 1
0.22U_0603_16V7K~D

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401593
Date: Saturday, June 06, 2009 Sheet 44 of 48
5 4 3 2 1
5 4 3 2 1

1
PD12 PD13
PJSOT24C_SOT23-3 PJSOT24C_SOT23-3
D BATT+ @ @ D
BATT++

3
PL28 Battery Connect/OTP
BATT+

SMB3025500YA_2P

1 2 BATT++
+3VALWP

100P_0402_50V8J~D
1

1
100P_0402_50V8J~D
1

PC289
PC279
PC288

PC278 1000P_0402_50V7K~D
2

2
0.01U_0402_25V7K~D
2

PR324 Place clsoe to EC pin


47K_0402_5%~D
1 2 BATT_TEMP
BATT_TEMP 27

1
PJPB1 battery connector PR325

2
1K_0402_5%~D
PC280
0.1U_0402_16V7K~D

1
SMART PJP19

@
1 PR326
Battery: 1
2 2
3 3cell/4cell# 1K_0402_5%~D
3 3cell/4cell# 39
4 2 1
1.BAT+
4
5 5 1 2 +3VALWP
@
2.BAT+ 6 6
7 PR327
7
3.ID 10 GND 8 8 6.49K_0402_1%~D
11 9
4.B/I GND 9

C 5.TS SUYIN_200275MR009G186ZL 1 2 EC_SMB_DA1 27 C


6.SMD PR328
100_0402_5%~D
7.SMC
8.GND CPU
9.GND 1 2 EC_SMB_CK1 27 PH1 under CPU botten side :
PR329
100_0402_5%~D
CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

VL VS
BATT+
1

2
PR330

1
453K_0402_1%~D PC281
0.1U_0603_25V7K~D
CPU

1
VS
2

PR331
10.7K_0402_1%~D VL

2
1
0.01U_0402_25V7K~D

PR333
PR332 147K_0402_1%~D

2
499K_0402_1%~D 1 2
1

PC282

PR334
B 205K_0402_1%~D B
2
2

PR335

1
8
61.9K_0402_1%~D
1 2 3 PD11

P
+
8

PR353 1 1 2
5 1 2 2
0 MAINPWON 40
P

+ VL -

G
2 1 7 1SS355_SOD323-2
0 PR336 PU22A
6

4
-
G

1
27 BATT_OVP 10K_0402_1%~D 150K_0402_1%~D LM358ADR_SO8
1

PH4
4

1
PU22B 100K_0603_1%_TH11-4H104FT

1
PR337
LM358ADR_SO8 86.6K_0402_1% PC283 PR338

2
1000P_0402_50V7K~D 150K_0402_1%~D
2

2
2
PC284
1U_0603_10V6K~D

LI-3S :13.5V----BATT-OVP=1.5V
BATT-OVP=0.111*BATT+

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/10/1 Deciphered Date 2007/05/30 Title
SCHEMATIC, M/B LA-4232P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 45 of 48
5 4 3 2 1 hexainf@hotmail.com
5 4 3 2 1

Version Change List ( P. I. R. List ) Page 1/1


Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 29 P29-EC KB926/REED SW/TPM1.2 07/10/30 compal board rev update to 0.2 R231 change to 15K & R232 pop 0.2

D 2 40 P40-OZ129_Card Reader/1394 07/10/30 compal CardBus vendor change CardBus R5C833 change to OZ129 0.2 D

3 29 P29-EC KB926/REED SW/TPM1.2 07/10/30 compal Change pull up resistance Change EC pin17,18 pull up to 4.7Kohm 0.2

4 29 P29-EC KB926/REED SW/TPM1.2 07/10/30 compal Need pull up NET MIC_DIAG pull up R to 10Kohm 3VS 0.2

5 13,14 DDR2 SODIMM-I,II Socket 07/10/30 compal Change Capacitance Change C84,C189 to SGA00002680 330U 0.2

6 29 P29-EC KB926/REED SW/TPM1.2 07/10/30 compal EC update rev EC change to 926C 0.2

7 28 P28-Express card 07/10/30 compal Express card can't detect POWER IC(U11) ADD PIN10 CPUSB# PIN9 EXPR_CPUSB#S 0.2

8 32 P32-USB/ BlueTooth/ 07/10/30 compal Bluetooth can't detect BLUETOOTH CONN USB+- change 0.2
FP/ Felica
9 42 P42-Screws 07/10/30 compal FIDUCAL no enough ADD FIDUCAL*4 0.2

10 41 P41-DC/DC Interface 07/10/30 compal Need pull down SYSON pull down 10K ohm 0.2

11 41 P41-DC/DC Interface 07/11/12 compal USB can't detect SUSP change to 5VALW(Q32) 0.2

12 06 P06-Merom(3/3)-GND/Bypass 07/11/12 compal Change CPU High Frequence Decoupling Capacitance C195 change to C1150~C1181 0.2
C C
13 41 P41-DC/DC Interface 07/11/13 compal +1.8VS Discharge error +1.8VS Discharge circuit Q65 net change to VGA_PWGOD# 0.2

14 41 P41-DC/DC Interface 07/11/16 compal Delete Remove SIM card connector 0.2

15 42 P42-Screws 07/11/16 compal Change Holea size Change Holea size 2.5 to 2.8, change 3.5 to 3.8 0.2

16 31 P31-PWR_OK/ BTN/ KB / 07/11/21 compal Change Touch PAD/B connector Touch PAD/B connector change net 0.2
TouchPad
17 15 P15-CRT Conn.& LCD Conn. 07/11/21 compal Add LCD control pin Add LCD control pin LCD_CBL_DET# & LCD_TST & LCD_VCC_TEST_EN 0.2

18 20 P20-ICH9(4/4)_POWER&GND 08/04/22 compal +5VS & +3VS have leakage Change VCCCL3[1] [2] & VCCLAN3_3[1] [2] power source to +LAN_IO

19 20 P09-Cantiga(3/6)-VGA/LVDS/TV 08/04/22 compal Can't boot to OS Add BOM Structure @

20

21

22

B 23 B

24

25

26

27

28

29

30

31

32

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 46 of 48
5 4 3 2 1
5 4 3 2 1

Version Change List ( P. I. R. List ) Page 1/1


Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 41 1.8VP/+VCCPP 08/10/22 COMPAL adjust +VCCP OCP set Change PC248 from 0.033u to 0.068u 0.2

D 2 42 1.5VSP/+VGA_CORE 08/10/22 COMPAL ripple voltage fail Change PC227 from SF22001M300 to SGA20221150 0.2 D

3 42 1.5VSP/+VGA_CORE 08/10/22 COMPAL convenient test Add PR304 0.2

4 44 CPU_CORE 08/10/22 COMPAL load line fail Change PR187 from 2.21K to 3.24K 0.2

5 38 DCIN / Precharge 08/10/22 COMPAL modify MLCC part number change part number N0 to 8L 0.2

6 39 Charger 08/10/22 COMPAL modify MLCC part number change part number N0 to 8L 0.2

7 40 +3VALWP/+5VALWP 08/10/22 COMPAL modify MLCC part number change part number N0 to 8L 0.2

8 41 1.8VP/+VCCPP 08/10/22 COMPAL modify MLCC part number change part number N0 to 8L 0.2

9 42 1.5VSP/+VGA_CORE 08/10/22 COMPAL modify MLCC part number change part number N0 to 8L 0.2

10 43 +0.9VSP/+1.1V_GFX_PCIEP 08/10/22 COMPAL modify MLCC part number change part number N0 to 8L 0.2

11 44 CPU_CORE 08/10/22 COMPAL modify MLCC part number change part number N0 to 8L 0.2

12 45 BATTERY CONN 08/10/22 COMPAL modify MLCC part number change part number N0 to 8L 0.2
C C
13 40 +3VALWP/+5VALWP 08/10/24 COMPAL boost choke current rating change PL20 PL21 from SH000006380 to SH00000AY00 0.2

14 45 BATTERY CONN 08/10/30 COMPAL delete diode for EMD request del PD14 PD15 0.2

15 45 BATTERY CONN 08/10/30 COMPAL change diode for EMD request change PD12 PD13 from SC1A204U00L to SCA00000E00 0.2

16 39 Charger 08/10/31 COMPAL design modify add PR372 PR373 0.2

17 41 1.8VP/+VCCPP 08/11/03 COMPAL dynamic fail change PC233 from SGA20221150 to SGA00001U80 0.2

18 44 CPU_CORE 08/12/08 COMPAL cost down change PU11 from SA00001HU80 to SA000031W00 and interrelated components 0.3

19 38 DCIN / Precharge 08/12/08 COMPAL common circuit design modify change PR203 from 33 to 68 and add PR204 to 68 0.3

20 39 Charger 08/12/08 COMPAL vendor FAE suggest change PR272 PR339 from 1 to 3.3 0.3

21 38 DCIN / Precharge 08/12/08 COMPAL design modify change PL17 from SM010018880 to SM010008E10 0.3

22 45 BATTERY CONN 08/12/08 COMPAL design modify change PL28 from SM010018210 to SM010008E10 0.3

23 39 Charger 08/12/15 COMPAL change component for EMD request change PJP15 to PL19 SM010016410 0.3
B B

24 39 Charger 08/12/15 COMPAL add capacitor for EMD request add PC274 0.1u 0.3

25 42 1.5VSP/+VGA_CORE 09/01/19 COMPAL adjust VGA_CORE OCP set change PQ72 from SB00000CG00 to SB562940080 0.4

26 change PQ73 from SB00000AJ00 to SB000003W00 0.4

27 change PL24 from SH000008700 to SH000005400 0.4

28 change PR276 PR282 from 24K to 19.6K 0.4

29 change PC230 from 0.022u to 6800p 0.4

30 consumption adjust change PR269 from 3.3K to 2.2K 0.4

31 44 CPU_CORE 09/01/19 COMPAL vendor FAE suggest add PC141 330p 0.4

32 45 BATTERY CONN 09/02/18 COMPAL delete diode for ESD request del PD12 PD13 0.4

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-4232P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401593 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Saturday, June 06, 2009 Sheet 47 of 48
5 4 3 2 1 hexainf@hotmail.com
A

KAL80 POWER UP SEQUENCE

ACIN/BATT-IN
51ON#
(only BATT-IN)

← 126ms →
5VALW/3VALW
644ms
RSMRST# ←→
Suspend Clock (32KHz) SUSCLK

→ ←←→
ICH9 internal clock 864us 244ms
ON/OFF#

EC_ON 360ms

PWRBTN_OUT# ←→
1.59ms ←
→ 2.74ms
SYSON#

1.8V ←250ms

SLP_S5# ← → 30.6us
SLP_S4# ←→30us
SLP_S3# ←→
SUSP# ← 3.88s → 888us
+5VS ←→ 104us
+3VS
←→ ←→ 112us

+1.5VS
2.02ms
+0.9VS →1.46ms

VCCP ←→ 24.1ms
VR_ON ← → 1.20ms
CPU_CORE ←→ 5.26ms
This signal is
VGATE ←→
asserted high when
A both SLP_S3# and A
VRMPWRGD are high CK_PWRGD
1.03ns
CLK_MCH_BCLK ←

ICH_PWROK ←114ms→ 1.20ms
PCI_RST# ←→
1.06ms ←→
H_PWRGOOD

H_RESET# ←2.20ms→

Compal Electronics, Inc.


Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL,INC. AND CONTAINS CONFIDENTIAL AND TRADE SCHEMATIC, M/B LA-4232P
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF COMPETENT DIVISION OF R&D DEPARTMENT Size Document Number Rev
EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR Custom C
DISCLOSED TO ANY THIRD PARTY WITHOUTPRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401593
Date: Saturday, June 06, 2009 Sheet 48 of 48
A

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