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Kahng Ansys Dacbreakfast Talk Distributed2
Kahng Ansys Dacbreakfast Talk Distributed2
Andrew B. Kahng
CSE and ECE Department
UC San Diego
http://vlsicad.ucsd.edu/~abk/
abk@ucsd.edu
(105, 130)
QOR (%) #1 #2
FUTURE (130, 120)
(30, 100)
#3
100 (50, 110) TODAY (130, 100)
90 (30, 90)
Design time
30 130 (weeks)
#3. Optimized back-end “Magic” synthesis, place, route, optimization; PG + Clock; Tech)
#2. Modeling, signoff criteria Reduced corners and guardbands; Targeting
#1. Bespoke, design-specific flow (+ Moore) Predictive, one-pass flow; Opt tool usage
• Intentionally
• By miscorrelating -0.1
-0.2
-0.3
-0.4
123 ps
-0.5
-0.6
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1
Artificial Real
Circuits Designs ONE-TIME
-0.2
-0.3 ML 31 ps
Modeling
-0.4 123 ps ~4 reduction
-0.5
-0.6
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1
T1 Path Slack (ns) T1 Path Slack (ns)
Andrew B. Kahng ANSYS Breakfast June 20, 2017 8
[SLIP15]
Harder: Non-SI to SI Calibration
• Complex interplay of electrical,
Post P & R Database
logic structure, and layout
.db, .lib .spef .v .sdc parameters
• Black-box code in STA tools
• Slack diverges by 81ps (clock
period = 1.0ns)
• ~4 stages of logic at 28nm
Non-SI Timing FDSOI
Non-SIReport
Timing Report
($)
Non-SI Path Slack (ns)
Calibration: Recipe to Convert
Non-SI Timing Report to SI
Timing Report
81ps
SI Timing
SI Report
Timing
Report
SI Timing Report
Standard cells
Route-DRC
False-negative
Extraction
windows
Non-buried net
Detailed route
eg1 8478 1964 -76.83% 1742804 1747685 0.3% -153.43 -158.4 3.2% 7289 7352 0.86%
eg2 1502 927 -38.28% 1750698 1753047 0.1% -168.23 -163.5 -2.8% 7406 7374 -0.43%
eg3 2017 1819 -9.82% 1772889 1773701 0.0% -215.75 -213.6 -1.0% 7817 7751 -0.84%
eg4 2026 1780 -12.14% 1735185 1735227 0.0% -151.36 -149.6 -1.2% 7195 7143 -0.72%
eg5 4252 4255 0.07% 1831492 1836060 0.2% -264.34 -275.6 4.3% 7865 7975 1.40%
eg6 3440 3891 13.11% 1790059 1794184 0.2% -195.65 -203.5 4.0% 7587 7562 -0.33%
Sim Results
Tech files, signoff (Dyn.) Activity Functional
Sim vectors
Sim
criteria, corners Factor (Static) Benchmark
RTL
IR Drop Power
Map Thermal
AVS Trace Analysis
Task
Timing/ Mapping/
P&R + Noise Migration/
Reliability (DVFS)
Optimization
Report
MTTF &
Aging
Andrew B. Kahng ANSYS Breakfast June 20, 2017 19
[ASPDAC16]
Closing Multiphysics Analysis Loops
Sim Results
Tech files, signoff Workload-Thermal
(Dyn.) Activity Functional loopSim vectors
Sim
criteria, corners Factor (Static) Benchmark
STA-IR loop RTL
IR Drop Power
Map Thermal
AVS Trace Analysis
29ps
25ps
SRAM #1 SRAM #5
Implementation Index
Ground Truth
31 384
False negatives
Recall Recall
Andrew B. Kahng ANSYS Breakfast June 20, 2017 25
Agenda
• Correlation
• SI for Free
• Learning Model-Guided Optimization of Routability
• Prediction
• Risk of Timing Failure at Floorplan Stage
• Bump Inductance in Die-Package PDN Design
• Optimization
• Design and Schedule Resources
• Conclusions
A2 A5 A3
(3) (1) (3) Datacenter capacity
A2 A4 A5
Usage (Across Three
Post Route Area vs Synthesis Frequency for AES in 28nm Post Route Area vs Synthesis Frequency for PULPino in
FDSOI 14nm finFET
Sampling Distribution
1.2
Frequency Sampled (GHz)
0.8
0.6
0.4
0.2
0
1 3 5 7 9 11 13
Sample Index
MAB sampling applied to synthesis runs on ARM CortexM0 using XXX cells
Andrew B. Kahng ANSYS Breakfast June 20, 2017 37
Agenda
• Correlation
• SI for Free
• Learning Model-Guided Optimization of Routability
• CTS ECO Route Prediction and Optimization
• Prediction
• Risk of Timing Failure at Floorplan Stage
• Bump Inductance in Die-Package PDN Design
• (3D Power Estimation from Golden 2D Implementation)
• Optimization
• Design and Schedule Resources
• Conclusions
abk@ucsd.edu