Tripoli University

Faculty of Engineering
Computer Engineering Department

Course: Digital systems (EC381)

LAB5 REPORT

Mohammed Altoumi
ID: 022171408

Instructor:
Dr.Yusra Mohammed Maatug
Lab Date: 10/05/2021
Experiment 1( Latches)

Connect each of the circuits shown below and fill the Corresponding truth table. In the truth
tables Qp stands for present Q and Qn stands for next Q .

1.1 Analyzing the problem.

 As we can see, the circuit combined with NOR implementation that means when one of the
inputs is high the output is necessarily to be low
 Since the NOR gate depends on the present state, when R and S is low the present state will
remain the same.
 When either R or S is high, the next state will be RESET or SET.
 When R and S are both high a new condition is generated.
 The new condition is undefined because we got both SET and RESET conditions.

1.2 List of components that we will use:

NOR 2
INPUTS 2
OUTPUTS 2
Table 1 List of the circuit components

1.3 Implementation:
Figure 1 (Circuit Implementation using LOGISIM for R=1, S=0, Q=0 and Q`=1)

R S Q Q`
1 0 0 1

Figure 2 (Circuit Implementation using LOGISIM for R=0, S=1, Q=1 and Q`=0)

R S Q Q`
0 1 1 0
 Figure 3 (Circuit Implementation using LOGISIM for R=1, S=1, Q=0 and Q`=0)

R S Q Q`
1 1 0 0

1.4 Driving troth table depending on simulation Results:

S R QP QN Q`N
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 0 1
1 0 0 1 0
1 0 1 1 0
1 1 0 0 0
1 1 1 0 0

TABLE 2 (Truth table for experiment1 results)

 S R QN Q`N

0 0 NO CHANGE
0 1 RESET
1 0 SET
1 1 UNDEFINED

TABLE 3 (Truth table for experiment1 results)

D Latch with Enable

Connect the circuit shown below and fill the Corresponding truth table. In the
truth tables Qp stands for present Q and Qn stands for next Q .

1.2.1 Analyzing the problem:

 D –latch is primarily made for elimination the unknown state (undefined state)
 Instead of NOR gates, D-latch is combined from NAND implementation.
 NAND implementation means that when one of the input is low, the output will set in
high
 . The unknown state will not be fulfilled because the D is high in one gate and low in the
other gate.
 When EN is low the present state will remain the same.
 The value of D is the control of the SET and RESET states.
1.2.2 List of components that we will use:

NAND 4
NOT 1
INPUTS 2
OUTPUTS 2
Table 4 List of the circuit components

1.2.3 Implementation:

Figure 4 (Circuit Implementation using LOGISIM for EN=1, D=0, Q=0 and Q`=1)

EN D Q Q`
1 0 0 1
Figure 5 (Circuit Implementation using LOGISIM for EN=1, D=1, Q=1 and Q`=0)

EN D Q Q`
1 1 1 0

Figure 6 (Circuit Implementation using LOGISIM for EN=0, D=1, Q=0 and Q`=1)

EN D Q Q`
0 1 0 1
 Figure 7 (Circuit Implementation using LOGISIM for EN=0, D=0, Q=0 and Q`=1)

EN D Q Q`
0 0 0 1

 From previous two implementations we can conclude the next:

EN D Q Q`
0 x No change

1.2.4 Driving troth table depending on simulation Results:

En D QP QN Q`N
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 1
1 1 0 1 0
1 1 1 1 0
 En D QN Q`N

0 X NO CHANGE
1 0 RESET
1 1 SET

Experiment 2 (Sequence detector)

The following state diagram of a sequential circuit that recognizes the sequence
1101 on input X. The output y goes 1 once the sequence is detected, Complete the
circuit design using jk Flip flop.

2.1 Driving state table depending on state diagram:

Present state input Next state

output
A B X A B JA KA JB KB Y
0 0 0 0 0 0 x 0 x 0
0 0 1 0 1 0 x 1 x 0
0 1 0 0 0 0 x x 1 0
 0 1 1 1 0 1 x x 1 0
1 0 0 1 1 x 0 1 x 0
1 0 1 1 0 x 0 0 x 0
1 1 0 0 0 x 1 x 1 0
1 1 1 0 1 x 1 x 0 1
TABLE4 (state table for experiment 2)

2.2 Solving for JK-FF inputs:

From the truth table, the FF inputs can be expressed as sum of minterms as follows:

JA= ∑m(3), d= ∑m(4, 5, 6, 7)

JB= ∑m(1, 4), d= ∑m(2, 3, 6, 7)
KA= ∑m(0, 1, 2, 3), d= ∑m(6, 7)
KB= ∑m(0, 1, 4, 5), d= ∑m(2, 3, 6)
Y= ∑m(7)

 Now to simplify k-map is used.

A \BX 00 01 11 10
0 0 0 1 0

1 X X X X

Figure 8 (k-map for JA)

JA = BX

A \BX 00 01 11 10
 0 X X X X

1 0 0 1 1

Figure 9 (k-map for KA)

KA = B

A \BX 00 01 11 10
0 0 1 X X

1 1 0 X X

Figure 10 (k-map for JB)

JB = A`X + AX`

JB = A ⊕ X

A \BX 00 01 11 10
0 X X 1 1

1 X X 0 1

Figure 11 (k-map for KB)

KB = A` + X`

A \BX 00 01 11 10
 0 0 0 0 0

1 0 0 1 0

Figure 12 (k-map for Y)

Y= ABX

2.3 List of components that we will use:

VCC 1
GROUND 1
AND 2
OR 1
XOR 1
SWITCH 4
PROBE 1
LOGIC ANALYSER 1
DECODED SEVEN-SEGMENT DISPLAY 1
J-K FF 2
CLOCK 1
NOT (7408) 1
Table 5 List of the circuit components
2.4 Implementation:
 The design was implemented to recognize the sequence 1101 on input X by using JK FF
 elements were replaced as all previous experiment and there is nothing new.
 This time we add logic analyzer and seven segment display to detect the change in
sequence.
 The clock was added and connected to the ground and ff`s.
 Figure 12 (Circuit Implementation using EWB)

2.5 Simulation Results:

 In figure the logic analyzer detect the change in a, b, x and y.

 The deference between T1 and T2 is after T1 x set in low witch led to drag the sequence
to state 1, and in T2 x set in high witch led to drag the sequence to state 0, and in

Figure 13 (Circuit result using LOGIC ANALYZER in EWB for A, B, x and Y)

Experiment 3 (Counter with unused states)

Design, construct, and test a counter that goes through the following sequence of binary states: 0,
1,2, 3, 6, 7, 10, 11, 12, 13, 14, 15, and back to 0 to repeat. Note that binary states 4, 5, 8, and 9
are not used. The counter must be self‐starting; that is, if the circuit starts from any one of the
four invalid states, the count pulses must transfer the circuit to one of the valid states to continue
the count correctly (Use T flip flop).

Check the circuit’s operation for the required count sequence. Verify that the counter is self‐
starting. This is done by initializing the circuit to each unused state by means of the preset and
clear inputs and then applying pulses to see whether the counter reaches one of the valid states.

3.1 designing state diagram:

Figure 14 (state diagram for experiment 3)

3.2 deriving the state table:

Present state Next state

A B C D A B C D TA TB TC TD
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 1
0 0 1 1 0 1 1 0 0 1 0 1
0 1 0 0 X X X X X X X X
0 1 0 1 X X X X X X X X
0 1 1 0 0 1 1 1 0 0 0 1
0 1 1 1 1 0 1 0 1 1 0 1
1 0 0 0 X X X X X X X X
1 0 0 1 X X X X X X X X
1 0 1 0 1 0 1 1 0 0 0 1
1 0 1 1 1 1 0 0 0 1 1 1
1 1 0 0 1 1 0 1 0 0 0 1
1 1 0 1 1 1 1 0 0 0 1 1
1 1 1 0 1 1 1 1 0 0 0 1
1 1 1 1 0 0 0 0 1 1 1 1
TABLE 6 (State table for experiment 3)

3.3 Solving for T FF inputs:

From the truth table, the FF inputs can be expressed as sum of minterms as follows:

TA= ∑m(7, 15), d= ∑m(4, 5, 8, 9)

TB= ∑m(3, 7, 11, 15), d= ∑m(4, 5, 8, 9)
TC= ∑m(1, 11, 13, 15), d= ∑m(4, 5, 8, 9)
TD= ∑m(0, 1, 2, 3, 6, 7, 10, 11, 12, 13, 14, 15), d= ∑m(4, 5, 8, 9)

 Now to simplify k-map is used.

AB\CD 00 01 11 10

00 0 0 0 0

01 X X 1 0

11 0 0 1 0

10 X X 0 0

Figure 15 (k-map for TA)

TA = BCD

AB\CD 00 01 11 10
00 0 0 1 0

01 X X 1 0

11 0 0 1 0

10 X X 1 0

Figure 16 (k-map for TB)

TB = CD

AB\CD 00 01 11 10
00 0 1 0 0
 01 X X 0 0

11 0 1 1 0

10 X X 1 0

Figure 17 (k-map for TC)

TC=AD + C`D

AB\CD 00 01 11 10
00 1 1 1 1

01 X X 1 1

11 1 1 1 1

10 X X 1 1

Figure 18 (k-map for TD)

TD = 1

 After solving the equations using k-map the following was observed:

Present state Next state

A B C D A B C D TA TB TC TD
0 1 0 0 0 1 0 1 0 0 0 1
0 1 0 1 0 1 1 0 0 0 1 1
1 0 0 0 1 0 0 1 0 0 0 1
1 0 0 1 1 0 1 0 0 0 1 1

 That means the circuit is self-correcting after 0101, 1001 to be in valid state.
3.4 List of components that we will use:

AND 4
OR 1
XOR 4
LOGIC ANALYSER 1
DECODED SEVEN-SEGMENT DISPLAY 1
D FF 4
CLOCK 1
GROUND 1
Table 7 List of the circuit components

3.5 Implementation:
 The design was implemented to move insequence from 0 to 15 and skipping 4, 5, 8 and 9
then repeats by using T FF
 I had to design T FF from D FF because I didn't find it in EWB.
 elements were replaced as previous experiment.

Figure 19 (Circuit Implementation using EWB )

3.6 Simulation Results:

 We can notice that after the counter reached 3 at T1, the counter passed 4 and 5, and
after it reached 7 at T2, it skipped 8 and 9.

Figure 20 (Circuit result using LOGIC ANALYZER in EWB for TA, TB, TC AND TD)

3.7 invalid states test:

Figure 21 shows the initial invalid state 1001
 Figure 22 shows how the invalid state 1001 moves to valid state 1010

Experiment 4

Design a sequential circuit with two D flip-flops A and B and one input X. When X=0, the state of
the circuit remains the same. When X=1, the circuit goes through the state transition from 00 to
01 to 11 to 10, back to 00, and then repeats.

4.1 designing state diagram:

Figure 21 (state diagram for experiment 4)

4.2 deriving the state table:
Present Next state
state
A B X A B DA DB
0 0 0 0 0 0 0
0 0 1 0 1 0 1
0 1 0 0 1 0 1
0 1 1 1 1 1 1
1 0 0 1 0 1 0
1 0 1 0 0 0 0
1 1 0 1 1 1 1
1 1 1 1 0 1 0
TABLE 8 (State table for experiment 3)

4.3 Solving for T FF inputs:

From the truth table, the FF inputs can be expressed as sum of minterms as follows:

DA= ∑m(3, 4, 6, 7)
DB= ∑m(1, 2, 3, 6)

 Now to simplify k-map is used.

A \BX 00 01 11 10
0 0 0 1 0

1 1 0 1 1

Figure 22 (k-map for DA)

DA = AX` + BX

A \BX 00 01 11 10
0 0 1 1 1

1 0 0 0 1

Figure 23 (k-map for DB)

DB = A`X + BX`

4.4 List of components that we will use:

AND 4
OR 2
NOT 1
LOGIC ANALYSER 1
DECODED SEVEN-SEGMENT DISPLAY 1
D FF 2
CLOCK 1
GROUND 1
Table 7 List of the circuit components

4.5 Implementation:
 The design was implemented for when X=0, the state of the circuit remains the same.
When X=1, the circuit goes through the state transition from 00 to 01 to 11 to 10, back
to 00, and then repeats.
 elements were replaced as previous experiment.
 Figure 23 (Circuit Implementation using EWB )

4.6 Simulation Results:

 We can notice that the circuit goes in sequence 00, 01, 11, 10 between the T1 and T2
and it`s still repeating.

Figure 20 (Circuit result using LOGIC ANALYZER in EWB for DA. DB)