ADDIS ABABA UNIVERSITY

SCHOOL OF INFORMATION TECHNOLOGY AND

ENGINEERING
COMPUTER ARCHITECTURE & ORGANIZATION
BUS DESIGN
SOFTWARE ENGINEERING – SECTION 2

Compiled by
1. Abenezer Sleshi ATR/7940/11
2. Aymen Mohammednur ATR/5985/11
3. Bethlehem Teshibelay ETR/9292/11
4. Semere Habtu ATR/2583/11
5. Semere Tereffe ATR/4113/11

Instructor: Mr. Abebe

September, 2021
 Table of Contents
Table of Figures ........................................................................................................ i
Introduction ..............................................................................................................1
1st Bus Design ............................................................................................................2
Bus Type - Multiplexed ...........................................................................................2
Method of Arbitration – Centralized ......................................................................2
Timing – Synchronous ............................................................................................2
Bus Width – Data ....................................................................................................3
Data Transfer Type - Block ....................................................................................3
2nd Bus Design ...........................................................................................................5
Bus Type – Dedicated .............................................................................................5
Method of Arbitration – Distributed .......................................................................5
Timing – Asynchronous ..........................................................................................5
Data Width – Address .............................................................................................5
Data Transfer Type – Block ....................................................................................6
Comparing Bus 1 and Bus 2 Designs .....................................................................6
Reference...................................................................................................................7
 Table of Figures
Figure 1: Elements of Bus Design .............................................................................1
Figure 2: Data Transfer Type: READ ........................................................................3
Figure 3: Data Transfer Type: WRITE ......................................................................3
Figure 4: Data Transfer Type: READ-MODIFY-WRITE ........................................4
Figure 5: Data Transfer Type: READ-AFTER-WRITE ...........................................4
Figure 6: Data Transfer Type: BLOCK .....................................................................4

i
Introduction
There are a wide variety of different bus implementations that are based on different parameters
or design elements. The basic parameters used to classify and differentiate buses are outlined in
the figure below;

Figure 1: Elements of Bus Design

In this document we will be designing two different buses based on the parameters above. Our
thought process going into this was let’s design two buses which will be geared towards two
different tasks. The objectives or both buses are the following;

➢ Objectives of 1st Bus:

• Faster performance
• General-Purposed
• Relatively lower cost
➢ Objectives of 2nd Bus:
• Higher performance (more efficient)
• Geared towards a specific purpose
• High Maintainability

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1st Bus Design
Bus Type - Multiplexed

The use of the same lines for multiple purposes is known as Multiplexing. A multiplexed bus is a
type of bus structure in which the number of signal lines comprising the bus is less than the number
of bits of data, address, and/or control information being transferred between elements of the
system. The information is transferred sequentially, i.e., time-domain multiplexed, with additional
control lines being used for sequencing the transfer.

We chose multiplexed bus over dedicated bus because it reduces the number of address and data
pins and dedicates those pins for other several microprocessor functions. This means the use of
fewer lines, which saves space, hence cost.

Method of Arbitration – Centralized

In a centralized scheme, a single hardware device, referred to as a bus controller or arbiter, is
responsible for allocating time on the bus. Centralized bus arbitration requires hardware that will
grant the bus to one of the requesting devices. This hardware can be part of the CPU or it can be a
separate device on the motherboard.

Our main reason to choose Centralized arbitration method for this bus design is due to the increased
speed and lower costs.

Timing – Synchronous

In synchronous timing, the timing of transactions on the bus is under the control of a synchronizing
clock signal. The bus includes a clock line upon which a clock transmits a regular sequence of
alternating 1s and 0s of equal duration.

We chose Synchronous timing mainly to take advantage of the high transmission speed it provides.
This choice also helps us avoid timing errors which are bound to happen in an asynchronous
system.

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Bus Width – Data

The data bus is used to transfer the data bits between the CPU and memory in contrast to the
address bus which is used to send the address information to memory. Each bit of the data must be
transferred on a different wire of the data bus. Width of the data bus is equivalent to the number
of wires used in the data bus.

Although both the data and address buses are integral parts of the architecture, for the system we’re
designing we’re choosing more data bus width. Since the width of the data bus determines the
amount of data transferred per memory transfer operation, the wider the data bus, the more data
can be transferred per unit of time, resulting in a faster running computer.

Data Transfer Type - Block

A bus provides several data transfer types as described below. All buses provide both write and
read assigns.

Read: In this operation address is put on the address bus and after sufficient access time data is
available on the data bus.

Figure 2: Data Transfer Type: READ

Write: Address is put on the multiplexed bus and then immediately after latching period data is
put on the multiplexed bus.

Figure 3: Data Transfer Type: WRITE

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Read-Modify-Write: A read followed immediately by a write to the same address.

Figure 4: Data Transfer Type: READ-MODIFY-WRITE

Read-After-Write: Consisting of a write followed immediately by a read from the same address
(for error checking purposes).

Figure 5: Data Transfer Type: READ-AFTER-WRITE

Block: One address cycle followed by n data cycles. The first data item is transferred to or from
the specified address; the remaining data items are transferred to or from subsequent addresses.

Figure 6: Data Transfer Type: BLOCK

For our bus design, we will be implementing a Block Data Transfer because we want a continuous
stream of data transfer as opposed the other data transfer types which have time delays.

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2nd Bus Design
Bus Type – Dedicated

A dedicated bus line is permanently assigned either to one function or to physical subset of
computer components (e.g., I/O bus connects all I/O modules). A store operation can put both the
address and the data on the bus at the same time.

We chose dedicated bus for this case because it was really important for us to focus on performance
and dedicated bus protects the various bus lines from traffic congestion and delays and improves
the reliability of services. Having separate data and address lines also simplifies the bus.

Method of Arbitration – Distributed

As opposed to a centralized method of arbitration, in a distributed scheme, there is no central

controller. Rather, each module contains access control logic and the modules act together to share
the bus. Each device on the bus is assigned a 4bit identification number. The priority of the device
will be determined by the generated ID.

The main reason we chose a distributed method of arbitration is because we wanted to design a
fault-tolerant system where it is critical that single point failures don’t cause the complete system
to fail. Other reasons include flexibility which means it’s easy to implement and add new services.

Timing – Asynchronous

Asynchronous timing does not involve a clock and, the occurrence of one event on a bus follows
and depends on the occurrence of a previous event.

We chose asynchronous because it is more flexible than synchronous timing which is tied to a
fixed clock rate. Moreover, asynchronous bus systems can take advantage of advances in device
performance.

Data Width – Address

The address bus is used to send the address information to memory. Each wire of the address bus
can convey 1 bit of the address. Each memory byte is identified by a unique memory address. The
width of the address bus determines the size of the memory that the computer can use.

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For this specific design, we’re choosing more address bus width because the wider the address
bus, the more memory a computer can use and more memory allows the computer to store more
data and solve larger and specialized problems such as sorting big amount of data.

Data Transfer Type – Block

We’re choosing block again for the said benefit it has which is providing a continuous stream of
data without any time delays.

Comparing Bus 1 and Bus 2 Designs

We will be comparing the designs of the two buses based on the following three criteria’s.

Performance
• While Bus 1 is geared towards increased speed of transmission, Bus 2 is generally more
robust and efficient.
Cost
• The use of multiplexing and centralized schemes in the general design specifications of
Bus 1 makes it cost effective when compared to Bus 2 which uses the more expensive
schemes.
Flexibility
• Bus 1 is more flexible in the sense that it’s designed to be general purposed while Bus 2 is
flexible in its internal design which makes it more maintainable.

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Reference
• https://www.mvorganizing.org/what-is-the-difference-between-synchronous-and-
asynchronous-bus/
• https://www.tutorialspoint.com/what-are-the-elements-of-bus-design-in-computer-
architecture
• http://www.mathcs.emory.edu/~cheung/Courses/255/Syl-ARM/4-intro/bus-
width.html
• https://youtu.be/iQdu0AzauOo

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