SCE 100nm

Angsuman Sarkar Short-Channel Effects in sub-100nm MOSFETs: A Review
SHORT-CHANNEL EFFECTS (SCEs)
2 IN SUB-100nm MOSFETs: A
REVIEW
2.1 Introduction to scaling and Moore’s law
Integrated-circuits (IC) technology has undergone through unmatched technological and

economical progress, truly improving people’s lives. Electronics as we know it today is
characterized by the reliability, the low power consumption, extremely low weight and
the volume, and low cost, coupled with an ability to cope easily with a high degree of
sophistication and complexity. The primary engine that powered the ascent of
electronics is “miniaturization”. Since the invention of the first calculation machines,
miniaturization has been a constant challenge to increase the speed and the complexity
in the microelectronics industry. The most ubiquitous circuitry used for digital logic
applications is CMOS, the complementary metal-oxide semiconductor field effect
transistor. The principal component of a CMOS integrated circuit is the MOSFET, the
fundamental switching element used to produce digital logic in integrated circuits.
MOSFET switching speed (in turn circuit speed) and device densities increases with
miniaturization. Down-scaling has dominated microelectronics device research, resulting
in the rapid progress of CMOS-based electronics in the past decades.
Linear scaling of device dimensions to a quasi-nanometer level allows building a
complex system integrated on a chip which reduces drastically their volume and power
consumption per function, whilst tremendously increasing their speed [1-4].
Functionality per chip has grown in accordance with the Moore’s law, an
historical observation made by Intel executive Gordon Moore. Moore’s law [1] states that
functionality as measured by the number of transistors doubles every 1.5 years.
With the continued downscaling of MOS transistors to the deca-nanometer regime,
several secondary issues related to the transistor device physics, hitherto considered to
be insignificant are found to play significant roles in IC performances. The IC designers
therefore, need proper understanding of the various parameters related to the
19
geometry, insight to device physics as well as performance of a single MOS transistor

and the effect of these on the performance of the overall VLSI circuit.
This chapter begins with the description of different scaling methods and how
they influence device parameters. Several second-order effects known as the short-
channel effects associated with scaling are then discussed. Various techniques employed
to alleviate SCEs are then reviewed in detail.
The objective of this chapter is to present i) a detailed review of the existing
study on the short-channel effects in deep-submicron MOSFETs ii) to discuss about the
recent issues and trends of deep sub-micron MOSFETs especially with the gate-length
below 100nm iii) to present the different technology aspects and the various engineering
techniques utilized to obtain future generation MOSFETs.
2.1.1 Benefits of scaling
Increased device packing density

Improved frequency response
Improved current drive (transconductance gm)
2.1.2 Types of scaling
Two types of scaling are common:

The constant field scaling
The constant voltage scaling
Constant field scaling requires a reduction in the power supply voltage as one decreases
the minimum feature size but it yields the largest reduction in the power-delay product
of a single transistor. In contrast power supply voltage is not reduced in the constant
voltage scaling and is therefore the preferred scaling method since it provides voltage
compatibility with older circuit technologies. The disadvantage of the constant voltage
scaling is that the electric field increases as the minimum feature length is reduced. This
leads to the many second-order effects like velocity saturation, the mobility degradation,
increased leakage currents and the lowering of breakdown voltages.
2.1.2.1 Constant Field Scaling
There are a number of different scenarios to scale CMOS transistors to improve circuit
performance and packing density. One of the most widely used approaches is the
constant electric field scaling scenario proposed by Dennard et. al. [3-7] (Figure 2.1), in
which all linear dimensions of the transistor (e.g., the gate length LG, the gate
20
oxide thickness tOX, etc.) and the operating voltage VDD are reduced by the same factor K
(<1).
Figure 2.1: Illustration of the principles of constant electric field scaling by

Dennard’s et al. [5]
The principle of constant field scaling is that the device dimension and the
device voltages are to be scaled in such a way so that the electric fields (vertical and
horizontal) remain essentially constant. To ensure the reliability of the scale device is
not compromised, the electric field in the scale device must not increase. This scaling
attempts to preserve the magnitude of internal electric fields in the MOSFET, while the
dimensions are scaled down. To achieve this, all voltages must be scaled down in
proportion as the device dimension.
2.1.2.2 Constant Voltage Scaling
In the constant voltage scaling, all dimensions of the MOSFET are reduced by a factor of
K as in constant field scaling. The power supply voltage and the terminal voltages, on
the other hand remain constant or unchanged.
In the constant field scaling, the scaling of voltages will not be practical in many
cases. In particular, the peripheral and interface circuitry may require certain voltage
levels for all input and output voltages. To accommodate the different voltage levels, the
multiple power supply arrangement is necessary and the complicated level shifters are
21
required. To get rid of these external voltage level constraints, the constant voltage
scaling is preferred, knowing that it can cause the serious device reliability issue.
2.2 ITRS roadmap for semiconductors

Due to the significant resources and investments required to develop the next
generation of CMOS technologies, it has been necessary to identify clear goals and
put collective efforts towards developing new equipment and technologies. Since
the early 1990’s semiconductor companies and academia have teamed up to predict
more precisely the future of the industry. The semiconductor roadmap represents a
consensus among industry leaders and gives projected needs based on past
trends. The “International Technology Roadmap for Semiconductors” (ITRS) [8] is
the standard accepted roadmap. Every year, the ITRS releases a report that serves as a
benchmark for the semiconductor industry. These reports describe the type of
technology, design tools, equipment and metrology tools that have to be developed in
order to keep pace with the exponential progress of semiconductor devices predicted by
“Moore’s law”.
In summary, the scaling improves the cost, the speed, and the power per
function with every new technology generation. All of these attributes have been
improved by 10 to 100 million times in four decades. This is an engineering achievement
unmatched in human history. Table 2.1 shows that the scaling is expected to continue
(HP: High Performance technology, LSTP: Low Standby Power technology for portable
Applications, EOT: Equivalent Oxide Thickness).
Table 2.1: Excerpt of 2009 ITRS technology scaling

Year of production 2009 2011 2013 2015 2017
HP printed gate length 47 35 28 22 17.7
(nm)
HP physical gate 29 24 20 17 14
length Lg(nm)
EOT for metal gate in 1.0/1.3 0.88/1.2 0.65/1.0 0.53/
nm(HP/LSTP)
VDD(HP/LSTP) 1.0/1.05 0.93/1.05 0.87/0.95 0.81/0.95 0.76/0.85
ION/W,HP(mA/µm) 1676 1812 2414 3003 2639
ION/W,LSTP(mA/µm) 0.54 0.58 0.51 1.02 0.97
22
2.3 MOSFET models

During the early 1980s, CMOS became the technology of choice for general-purpose
integrated circuit applications due to mainly its low static power consumption [9].
Recently, the CMOS technology has proven to be useful not only for digital circuits but
also for analog and RF circuits [10].
In other words, MOSFET models are defined as the bridge between the physical
world (technology, manufacturing issues etc.) on one end and the design world (device
simulation, timing simulation etc.). A CAD tool plays an essential role in today’s circuit
design. The productivity of circuit designers is intimately associated with the efficiency
of the available arsenal of CAD tools. However, the chip design productivity and
accuracy of the result depends mainly on the quality of the device models used [11-12].
There are three categories of device models a) numerical models b) look-up table
models and c) analytical or compact models [13-15]. Numerical models uses numerical
solution of partial differential equations related to carrier transport, doping and
geometry. Although they provide accurate results, they are computationally inefficient,
which prevent them from being used for circuit simulation. Typically, a numerical model
finds its use in the exploration of properties of a novel device structure. On the other
hand, table look up models, in the form of tables containing device data for different
bias points are typically used when the good physical model of any device are not
available. In contrast, the compact models or equivalent circuit models describe the
terminal properties of the device by means of a simplified set of equations or by an
equivalent circuit model. The purpose of a compact model is to obtain simple, fast, and
accurate representations of the device behavior. Compact transistor models are needed
to evaluate the performance of integrated circuits containing a large quantity of
transistors. There are two categories of MOSFET compact models: a) Physical models,
relies on device physics and b) Empirical models, which represent the device
characteristics through equations that fit data. Physical models are considered to be the
best as the model can be applied to different generation technologies by simply
changing parameters.
From 1970 onward, SPICE ((Simulation Program with Integrated Circuit
Emphasis)) and its variants (HSPICE from Synopsis, SPECTRE from Cadence and ELDO
from Mentor Graphics) have been used as an invaluable resource in evaluating IC
performance prior to its integration [16-17]. The Level 1 model also known as Shichman-
Hodges model [18] is the first MOSFET model to be used in the SPICE circuit simulator is
consider a simplified first order model suitable for long-channel transistors only. Unlike
level-1 model, where the subthreshold current is assumed to be zero and the terminal
23
capacitances described by Meyer model [19] are not charge conserving, a more complex
level-2 model addresses secondary effects related with small geometry MOSFETs. The
capacitive model can be the Meyer model [19] or the Ward-Dutton model [20], the latter
conserving charges. To address the drawbacks of level-2 model described in [11], a
semi-empirical level-3 model was introduced. It also suffers from the poor subthershold
current modeling and the output conductance variations. The massive evolution in
1980’s clearly suggests the inadequacy of level 1, 2 and 3 models to simulate circuits
with a large number of ever-smaller transistors efficiently. A different modeling
philosophy to that employed for first generation models was then adopted. BSIM
(Berkeley Short-Channel IGFET Model) [21] inaugurated a second generation of MOS
transistor modeling, which put less effort into developing the physical models but
instead concentrated on mathematics for faster and more robust circuit simulation [11].
Convergence problems and negative output conductance were some of the problems
that inhibited the use of BSIM for the analog designs. Later, BSIM2 and second
generation simulator HSPICE Level 28, stands suitable for analog circuit design. BSIM3
and its extension BSIM4 [22] based upon physical models and smoothing functions
introduced by Philips began the third generation approach [23].Other than BSIM, there
are more than 100 models already reported. Out of which, PSP (Pensylvania state
universities Surface Potential model) [24], HiSIM (Hiroshima University STARC IGFET
Model) [25], EKV (Enz-Krummenacher-Vitoz) model [26] are widely used in popular
commercial circuit simulators. The generations of compact models have evolved to
include more and more physical effects to bring higher accuracy.
2.4 Gate oxide scaling

Although the principle of the MOSFET was recognized in the late 1920s, it was
not until the 1960s that the device was successfully realized by Kahng and Atalla
[27]. That realization was critically dependent on the development of a passivation
technique to stabilize the silicon surface using silicon dioxide. The properly processed
Si/SiO2 interface exhibits a degree of perfection that is difficult to match. This materials
system has sustained the microelectronics industry since 1960. The existence of an
ideal insulator SiO2, in addition to other factors such as silicon’s mechanical strength
and abundance, has given silicon a dominant status in the IC industry. Ever since the
invention of the transistor and integrated circuits, the gate oxide has been
continually scaled down [28]. A thinner gate oxide gives a higher gate capacitance so
more inversion charge is induced at the same operating voltage. More inversion charge,
in turn, results in a higher drive current. At the same time, a thinner gate oxide allows
24
the gate to have better control of the potential in the channel region via stronger
capacitive coupling, suppressing short-channel effects (SCEs). As the devices are
shrinking, getting faster and using less power, the SiO2 gate oxide has been successfully
reduced to 15 Å thick, or about 6 atomic layers [14, 29-33].
2.4.1 Problems with ultra-thin gate oxides
Gate oxide scaling is not limited by manufacturing control. It is feasible to manufacture

sub-15Å SiO2 layers on 8-inch wafers with current technology. The real challenge comes
from gate leakage current through the thin oxide. Typically, the conduction band offset
between Si and SiO2 is 3.2eV and the valence band offset is 3.7eV, and holes have a
much lower tunneling probability in oxide than electrons. As a result, the leakage
current limit will be reached first for n-type MOSFETs [29-33].
Reduction of gate oxide thickness results in an increase in the field across the
oxide. The high electric field coupled with low oxide thickness results in tunneling of
electrons from substrate to gate and also from gate to substrate through the gate oxide,
resulting in the gate oxide tunneling current. To understand the phenomenon of
tunneling, let us consider an MOS capacitor with a heavily doped n+ type polysilicon gate
and a p-type substrate.
Due to the small oxide thickness, which results in a small width of the potential
barrier, the electrons at the strongly inverted surface can tunnel into or through the SiO2
layer and hence give rise to the gate current.
2.4.2 Gate tunnel currents
Quantum mechanical tunneling of carriers through the energy barriers becomes more
important as the dimensions of the transistors are scaled down to the nanometer range.
GIDL (Gate Induced Drain Leakage) is a leakage current which is related to the decrease
of gate oxide thickness. The source of leakage current is the tunneling current through
the gate oxide. The interface between silicon and silicon dioxide is still considered
perfect in terms of abruptness and in terms of electrical properties. One way to decrease
GIDL is to by decreasing Vds. GIDL is independent of temperature.
Based on the scaling laws, the gate oxide thickness must be reduced. This law
implies that oxides thinner than 1.0–1.5nm must be employed for 35-nm gate lengths.
These thicknesses comprise only a few layers of atoms and approach the fundamental
limits. With such thicknesses, the direct tunneling currents become very large. This
25
current is an exponential function of the gate oxide thickness and the applied voltage.
As gate oxide decreases rapidly with the new upcoming technologies, the gate leakage
current will become larger than the required leakage current of the transistor.
2.4.3 Diminishing Returns from gate oxide scaling
Although it is becoming progressively more difficult to scale down the gate oxide
thickness, the extra performance we gain is unfortunately diminishing [29] as discussed
in this section because Supply & threshold voltage is not scaled in same proportion as
gate oxide.
Figure 2.2: Scaling trends for the supply voltage and the gate oxide thickness. Due
to the non-scaling nature of the threshold voltage, the electric field across the gate
oxide has steadily increased [34]
The major problem comes from the ever-increasing electric field in the transistor.
Figure 2.2 shows the trends in the voltage scaling along with the trend in gate oxide
scaling. The gate oxide thickness has been scaled down faster than the supply voltage,
giving rise to the increased electric field. An increased surface electric field can severely
degrade the carrier mobility and consequently reduce the drive current. We know that in
the low Electric Field regime, Coulomb scattering is the dominant scattering mechanism.
However, if the surface vertical electric field approaches about 1 MV/cm, the mobility
rapidly drops due to the increased surface scattering. This effect is applicable to high-
k gate dielectrics to be discussed in the next section also. Perhaps the roughness
scattering will be even more devastating in that case, since the interface quality of the
high-k material systems may not match that of the Si/SiO2 interface.
26
2.5 Gate length scaling and Short-Channel Effects

The gate length has been one of the most important parameters directly related to
CMOS scaling. Smaller gate lengths, driven by an advanced lithographic capability,
allow the higher drive current and, consequently, the faster circuits, assuming that the
parasitic capacitances are scaled down simultaneously. This performance headroom
allows operation at the lower voltages. At the same time, the higher packing density is
also achieved, due to the ability to pattern finer structures. Traditionally, more demands
for gate length scaling have come from the DRAM industry, where the cost
(reduced by the packing density) has been crucial. Logic circuits have benefited
from these advances in lithography.
Many complications arise as MOSFET devices are miniaturized. As the channel
length decreases, many effects alter MOSFET device performance. These effects can be
sorted into four different categories attributing to their physical origins: a) the electric
field profile becomes two-dimensional b) the electric-field strength becomes very high c)
the limitation imposed on electron drift characteristics in the channel d) the decrease of
physical separation between the source and the drain.
The most important features that arise in short-channel MOSFETs are:
1. Two-dimensional potential profile
Reduction in the threshold voltage.
Drain-induced barrier lowering
2. Very high electric field in the channel
Hot carrier effect, gate oxide tunneling & impact ionization
Avalanche breakdown and parasitic bipolar effect
3. Limitation imposed on electron drift characteristics
Mobility degradation
Carrier velocity saturation
4. Decrease in physical separation
Channel length modulation and Punch-through
A MOSFET device is considered to be short when the channel length is the same order of
magnitude as the depletion-layer widths (XdD, XdS) of the source and drain junction as the
channel length L is reduced to increase both the operation speed and the number of
components per chip, the so-called short-channel effects arise.
The short channel effects are neglected in case of long channel devices but in
short-channel devices these effects controls much of the device performance.
27
2.5.1 Reduction of effective threshold voltage
In a long channel n-channel MOSFET with zero source and drain voltage applied, the
space charge regions at the source and drain extend into channel region, but occupy
any a small portion of the channel region. The channel depletion region was assumed to
be created only by the applied gate voltage, and the depletion regions associated with
the drain and the source p-n junctions were neglected. The shape of the gate-induced
bulk (channel) depletion region was assumed to be rectangular. However, when the
channel length is reduced to dimensions compatible to the edge-affected regions, the
threshold voltage experiences dependences on the channel length. Figure 2.3 below
illustrates the edge effects by the electric field lines appearing in the MOSFET depletion
layer. It can be seen that the electric field lines at the end of the channel originate from
the source/drain regions and not from the gate. Consequently, some charges at the
edges of the depletion layer is linked to the source and the drain charge, and not to the
gate charge.
In a long channel device, the channel formation is controlled by the gate and the
substrate. The gate voltage will control essentially all the space charge induced in the
channel region. As the channel length decreases, the potential profile becomes
gradually two-dimensional from a one-dimensional profile. Therefore, in case of short
channel devices, the charge control of the channel is shared by the four terminals (gate,
substrate, source and drain), called charge sharing.
The total charge below the gate controlled by the gate voltage in a short-channel device
is correspondingly less than that controlled by the gate in a long-channel device.
Consequently, a lower gate voltage is required to attain threshold in a short-channel
device. Now as the drain voltage increases the reversed biased space charge region at
the drain extends further into channel area and the gate will control even less bulk
charge. I.e., in a short channel device the n+ type source and the drain induce a
significant amount of the depletion charge that cannot be neglected. The depletion
regions of the source and the drain are very close to one another. Through a charge
sharing argument (Figure 2.3), this phenomenon can be explained. Unlike the long
channel device, in a short channel device, a significant portion of the field lines
emanating from the bulk charge terminate in the source and drain regions instead of at
the gate. As a result, it is easier for the gate to deplete the lower amount of channel
charge, lowering the threshold voltage of the device. The expression for the threshold
voltage in long channel MOSFET thus overestimates the depletion charge supported by
the gate voltage. Thus, the amount of the gate voltage required to offset the depletion
charge will be less. Thus, the estimated threshold voltage value from the threshold
28
voltage expression of a long channel MOSFET will be larger than the actual threshold
voltage value of short channel MOSFET.
Figure 2.3: Illustration of the threshold voltage related short-channel effects and
Charge sharing between the source /drain depletion regions and the channel
depletion region. A part of the depletion-layer charges under the channel is
created by the source and the drain electric field (note the origin of the arrows).
The effect is insignificant is long channel devices (a) but prominent is short-
channel devices (b). In addition, the deep depletion region formed in the short
channel device (b) due to the closeness of the source and the drain depletion
regions.
The deeper depletion region is accompanied by larger surface potential, which makes
the channel more attractive for electrons. Thus, the device can conduct more current.
This effect can be considered as the reduction of VTh as drain current is the function of
(Vgs-VTh). Increase in Vds and reduction of channel length will decrease the effective
threshold voltage as shown in figure 2.4. Curve representing the reduction of VTh with
decreasing effective channel length is known as VTh roll off. This adverse roll-off effect is
perhaps the most daunting roadblock in future MOSFET design [35]. The minimum
acceptable channel length is primarily determined by this roll-off.
29
Figure 2.4: Effective threshold voltage as a function of Vds taking L as parameter

for an n-channel MOSFET
2.5.2 DIBL (Drain Induced Barrier Lowering)
The population of channel carriers in the long channel devices is controlled by the gate
voltage through the vertical electric field, whereas the horizontal field controls the
current between the drain and the source. The current flow in the channel depends on
creating and sustaining an inversion layer on the surface. If the gate bias voltage is not
sufficient to invert the surface (VG< VTh), the carriers (electrons) in the channel face a
potential barrier that blocks the flow. Increasing then the gate voltage reduces this
potential barrier and eventually allows the flow of carriers under the influence of the
channel electric field.
In small geometry MOSFETs, the potential barrier faced by the source carriers is
controlled by both the gate- to-source voltage Vgs and the drain-to-source voltage Vds. If
the drain voltage is increased, the potential barrier in the channel decreases, leading to
DIBL. The reduction of the potential barrier eventually allows electron flow between
source and drain, even if the gate- to-source voltage is less than threshold voltage. The
channel current flows under this condition (Vgs <VTh) is known as subthreshold current.
In devices with long channel lengths, the gate is completely responsible for depleting
the semiconductor (QB).
In very short channel devices, part of the depletion is accomplished by the drain
and the source bias. Since less gate voltage is required to deplete QB, the barrier for
electron injection from the source to the drain decreases as shown in figure 2.5 below.
This is known as the drain induced barrier lowering (DIBL). DIBL results in an increase in
drain current at a given VG. Therefore, VTh decreases as L decreases. Similarly, as VD
30
increases, more QB is depleted by the drain bias, and hence Ids increases and VTh
decreases as shown in figure 2.6.
Figure 2.5: the DIBL effect
Figure 2.6: Effect of DIBL on current characteristics
2.5.3 Hot Carrier effects
The longitudinal electric field in the channel increases from the source to the drain. For
the abrupt source and drain junctions, the peak field is at the drain-to-channel junction,
and its value depends on Vds and channel length L [36].
The carriers crossing from the inverted channel pinch-off point to the drain travel
at their maximum saturated speed, and so gain their maximum kinetic energy in
saturation. These carries have high energy and are called hot carriers. These electrons
traveling from the source to the drain along the channel gains the kinetic energy at the
expense of electrostatic potential energy in the pinch off region, and behaves as a hot
31
electron. Some of them acquire enough energy to create impact ionization with silicon
lattice atoms, wherever new electrons and holes are created: this effect is referred as the
weak avalanche. The normal depletion field pushes the holes into substrate, where they
give rise to the drain-to-substrate current. The new electrons created from the avalanche
joins the stream of the channel electrons and move towards the drain. Another
important consequence of the high carrier heating associated with high electric field is
the concomitant transfer of carrier from semiconductor channel to gate oxide. Some
hot-carriers, though small in numbers, can acquire enough energy to surmount the Si-
SiO2, interface barrier and thus move (get injected) into the gate oxide (see figure 2.7
below). Most of the injected carriers will be collected by the gate electrode resulting in a
so called the gate current IG, reducing the input impedance. Since the energy barrier for
this process is very high, the number of hot-carriers injected into the gate will be much
smaller compared to those which cause impact ionization. Therefore, the gate current
will be smaller than the substrate current by a few orders of magnitude. It should be
pointed out that carriers can also enter the gate oxide by tunneling (see figure 2.7
below). For direct tunneling, the oxide has to be very thin and the field is to be high.
Even for the thicker oxide, the carrier with energy close to but less than the energy
barrier can tunnel through the barrier. This effect is called field assisted or Fowler-
Nordheim tunneling. In other words, increasing voltage across oxide may result in field-
induced (Fowler–Nordheim) tunneling of carriers [37], even with larger values of tox. This
“high-voltage” leakage current is exploited to charge or discharge an isolated gate in
EPROM [38] and E2PROM [39] nonvolatile memories. Now when tox is reduced below 2nm
in the state-of-the art deep submicron devices, a gate leakage current still occur even at
lower values of voltage across the oxide as the result of direct tunneling across the
oxide. [40-41] provides a suitable formulation of the current density.
Figure 2.7: Three different types of carrier injection into the gate resulting in hot-
carrier effects
32
Of those very energetic carriers, a small fraction create damage at the silicon-
oxide interface which manifests itself as an increase in the interface state density , and
yet another fraction becomes trapped in the oxide. The damage (traps) in the oxide
significantly affects reliability by leading to an ageing of the oxide. This is the most
important consequence of hot carrier injection into the oxide is the deterioration of the
device over time. This is often referred to as hot-electron aging. Although some of the
electrons injected into the oxide contribute to the gate leakage current, some of the
electrons injected become trapped within the oxide. As a result, the electric field
beneath the oxide changes as a function of the amount of trapped injected charge. Over
time with repeated hot electron stressing, the oxide charge can become appreciable,
resulting in a significant change in the threshold voltage of the device. This has severe
consequences for long-term device reliability. The accumulation of such traps behaves
as a fixed oxide charge, can cause a change (increase in nMOS) in the threshold voltage
of the device, and affect the gate’s control, giving rise to oxide wear-out and oxide
breakdown.
2.5.4 Avalanche breakdown and parasitic bipolar action
As the electric field in the channel is increased, due to high energetic hot
electrons, the avalanche breakdown occurs in the channel at the drain. This avalanche
breakdown increases the current as in a p-n diode. The electrons are attracted by the
drain, while the holes enter the substrate to form part of the parasitic substrate current.
Figure 2.8: Steps explaining impact ionization and parasitic bipolar action in a short
channel MOSFET
33
In addition, there is parasitic bipolar action taking place. The region between the
source and the drain can act like the base of an n-p-n transistor, with the source playing
the role of the emitter and the drain that of the collector. The positive feedback between
the avalanche breakdown and the parasitic bipolar action results in breakdown at lower
drain voltage. The whole process is depicted in figure 2.8. The substrate current
resulting from electron–hole pair generation may overload substrate- bias generators,
introduce snapback breakdown, cause CMOS latch-up, and generate a significant
increase in the subthreshold drain current [42-43]. A complete model for the substrate
current is too complex for use in circuit level simulation [44]. Therefore an approximate,
analytical expression is widely used [45].
2.5.5 Mobility Degradation
There are two reasons for mobility reduction in MOSFET

Mobility reduction with the gate voltage due to the vertical electric field
Mobility reduction with the drain voltage due to the horizontal electric field
2.5.5.1 Mobility reduction with the gate voltage due to the vertical electric field
In a MOS transistor, the current flows very close to the silicon surface. As a
consequence, the mobility of current carriers is lower than deep inside the substrate
(typically two to three times lower), due to various scattering mechanisms [46].
This second order effect can rarely be neglected. The effect is related to the gate
voltage and appears at the smallest drain-to-source voltage. A vertical electric field
exists in MOSFET due to the applied gate voltage, which creates the conduction channel.
When carriers move within the channel under the effect of horizontal electric field, they
feel the effect of gate induced vertical electric field, pushing carriers towards the gate
oxide as shown in figure 2.9 below. This provokes carriers to make the collision with the
oxide channel interface. The oxide –channel interface is rough and imperfect, thus
carriers loses mobility. This effect is known as surface scattering. The surface mobility
depends on how much the electrons interact with the interface, and therefore, on the
vertical electric field which "pushes" the electrons against the interface. We will note as
the surface mobility in absence of such an electric field. The higher the electric field, the
lower is the surface mobility. The reduction in the surface mobility can be modeled as
[15]
µ0
µ= (2.1)
1+ θ (Vgs - VTh )
34
Where µ0 is the mobility at threshold voltage and θ is the mobility reduction

factor.
Figure 2.9: Vertical electric field in a short channel MOSFET and due to that surface
scattering
2.5.5.2 Horizontal electric field Mobility Degradation
Channel carrier mobility can also be reduced by a high lateral electric field in the
channel. This mobility degradation due the lateral field Ey (drain voltage) has a more
significant effect on the device current equations than does the normal field Ex (gate
voltage). This is because an increase in the lateral field eventually causes velocity
saturation of the carriers. For a given normal field, the velocity v of a carrier is
proportional to Ey, at low lateral fields, and the proportionality constant is the surface
mobility µ s. However, as Ey increases, the carrier velocity tends to saturate.
Carriers in the short channel devices reach the velocity saturation at lower values
of Vds than for the long channel devices. This effect is due to the channel length
reduction that implies the higher horizontal electric fields for the equivalent drain to-
source voltages than the long channel MOSFETs. The horizontal electric field within the
channel is due to the voltage applied to the drain terminal. Due to this horizontal
electric field Horizontal mobility also reduces. There are several models of mobility
versus electric field. Equation 2.2 below shows one such simple commonly used
experimental model of the horizontal mobility reduction where the horizontal mobility
µH is related with the drain voltages as
35
µ0 µ0
µH = = (2.2)
Vds 1+ θ2Vds
1+
Leff Ecrit
1/LeffEcrtit is referred as drain bias mobility reduction parameter and in some texts denoted
as θ2. Ecrit is the electric field shown in figure 2.10. For large transistor θ2 is smaller than
1 thus µH= µ0. when LEff decreases, θ2increases and θ2Vds becomes important, lowering the
mobility below µ0.
2.5.6 Velocity Saturation
Velocity saturation occurs in any general solid state device when charged carriers move
in a solid under the force of an electric field, they acquire a velocity proportional to the
magnitude of this electric field. This applied electric field (E) and the carrier velocity (v)
are related through the mobility parameter µ.
v= µE (2.3)
For small electric field, µ is constant and independent of the applied electric field.
µ=µ0 (constant) (2.4)
As a result when carrier velocity is plotted versus the applied electric field, the result is a
straight line (low electric field of figure 2.10).
Electron scattering is linear with the small electric filed. If the electric field
further increases, the carrier velocity enters a region in which it is said to move at
velocity saturation. As device dimensions scale down, the electric fields within the
transistor increases, making the velocity saturation more important.
If equation (2.3) holds for carriers moving in the small electric fields and carriers
moving at the velocity saturation, then the mobility µ must change with the electric field
(Figure 2.10). Velocity saturation typically occurs because at higher fields the rate of
phonon emission increases and the rate of energy gained form the electric field equal
the rate of energy loss to the crystal primarily through phonons.
The performance of short channeled devices is also affected by the velocity
saturation, which reduces the trans-conductance in the saturation mode. At low electric
field, the electron drift velocity Vd in the channel varies linearly with the electric field
intensity. However as the electric field increases above 104 V/cm, the drift velocity tends
to increase more slowly, and approaches a saturation value of Vd(sat)= 107 cm/s around
the electric field =105 v/cm at 300k.
36
Figure 2.10: Electric field versus Carrier velocity in a solid
Both the electron and hole drift velocities saturate at applied electric fields in excess of
about 100 kV/cm. In short-channel devices, the electric field near the drain can attain
values in excess to 400kV/cm. The velocity–field relationship for the carriers takes the
form [47]
µ0 Ey
v= 1/ α
(2.5)
1 + ( E / E )α 
 y c 
Where EC is the critical electric field, EY is the channel field, α has a value close to 2 for
electrons and 1 for holes.
Velocity saturation will yield an Ids(sat) value smaller than that predicted is ideal
relation ,and it will yield a smaller Vds(sat) value that predicted . In a short channel
MOSFET before attaining pinch off carrier drift velocity saturates and thus the current
saturation occurs at a low value of Vds. Ids will be linear with Vgs. Thus the short-channel
devices therefore experience an extended saturation region, and tend to operate more
often in saturation conditions than their long-channel counterparts.
2.5.7 Channel Length Modulation and punch-through
As the drain voltage is increased, the effective channel length of the transistor shortens
because of the increase in the drain depletion region. In large devices, the amount of
decrease of channel length compared to total channel length is negligible, but in the
short channel devices it becomes important. The resulting channel length is simply
equal to the metallurgical channel length minus the source and drain depletion region
37
widths. The channel-length-modulation (CLM) effect typically increases in the small

devices with low-doped substrates [48]. The CLM effect manifests itself as a finite output
conductance in saturation, which tends to remain constant over a wide range of drain
biases. CLM is tightly linked to the effect of Velocity Saturation (VS) since carriers enter
into velocity in the high longitudinal field region close to the drain. This effect can be
explained simply by splitting the source to drain region into a non-saturated region (the
channel region) and a velocity saturation region (VSR) close to the drain using Gauss’s
law [49-50]. An extreme case of channel length modulation is punch through where the
channel length reduces to zero. Under this condition, the source and drain depletion
regions can touch, resulting in a large increase in the drain current.
2.5.8 Output impedance variation with drain-source voltage
The ideal MOSFET produces horizontal Ids-Vds characteristics in the saturation region,
which means it assumes infinitely large output resistance of the MOSFET. But in reality,
output impedance r0 is not constant in saturation region, it varies with Vds. There are at
least two effects that cause an increase in the drain current in the saturation region a)
channel length modulation b) drain-induced barrier lowering (DIBL). Channel length
modulation occurs as Vds increases, the pinch off point shifts towards the source, the
rate at which the depletion region around the source becomes wider decreases,
resulting in higher incremental impedance.
Figure 2.11: variation of output impedance r0 as a function of Vds
In short-channel devices, as Vds increases further, the DIBL become significant

which reduces threshold voltage and increase the drain current. This effect cancels
almost channel length modulation, resulting in almost constant output impedance. At
higher drain voltage, impact ionization produces a large current flowing from the drain
to the substrate, making the output impedance low. This region is also known as
38
substrate current induced body effect (SCBE) region. The SCBE results in a dramatic
decrease in output resistance in the high drain bias region. The variation of output
impedance r0 is plotted in figure 2.11.
2.5.9 Parameter fluctuation
A concomitant problem associated with device miniaturization is parameter fluctuation.

As device dimensions continue to shrink, random fluctuations in device parameters
become more important in dictating device performance. The random fluctuations of the
dopant concentration can be considered as a most vivid example. In many nanoscale
state-of-the-art MOSFET devices, the number of dopant atoms within the channel is only
in the order of hundreds. Therefore, small changes in the number and location of the
dopant atoms can result in significant performance fluctuations. Threshold voltage is
one of the most sensitive parameter to dopant fluctuation. Hence, within the chip there
can be a significant fluctuation in the device threshold voltage, which under most
situations is considered intolerable in circuit design.
2.5.10 Source/drain resistances and parasitic capacitances
As the device is scaled down to ultra-submicron dimensions, the source/drain

resistance and various parasitic capacitances increases appreciably. As a result, the
current drive and speed of the device is degraded [51]. For advanced short channel
structures, such as a Lightly Doped Drain (LDD) meant to reduce the hot electron effects
in scaled transistors, the parasitic resistance further increases due to the lower levels of
doping near the diffused junction forming the source and drain. The characteristics
length of lateral electric field in the channel of a short-channel MOSFET is given by [52]
ε Si tOX X D
LT = (2.6)
ε oxη
Where εSi, and εOX are permitivities of Silicon and SiO2 respectively, tOX is the gate oxide
thickness, Xdep is the depletion width and η is a fitting parameter [53]. According to an
empirical expression given by Brews et. al. [6] the minimum channel length Lmin should
be minimum 5lT.
Lmin = 5lT ∝ ( X jtOX X D2 )

1/3
(2.7)
Where junction depth Xj, Xdep and Lmin are in nm and tOX is in angstroms.
From [54], it may be concluded that the characteristic length may be considered
to be an indicator of the rate of decay of lateral electric field along the channel. Hence,
39
the magnitude of L is a measure of the severity of short channel effects on the threshold
voltage. From the expression of the characteristic length given by Equation (2.6), it is
noted that the characteristic length, L, has a square root dependence on gate oxide
thickness (tox) and depletion thickness (Wdm). While Wdm is assumed constant in the
analysis, it depends on channel length, drain voltage, and junction depth Xj. The
junction depth determines the effective channel length through its contribution to
lateral diffusion in mask defined polysilicon gate length [55-56]. Therefore, in order to
reduce immunity against SCEs, source/drain junction depth must be reduced. Therefore,
shallow source/drain junction is provided between deep drain/source and channel. To
further minimize dopant diffusion, doping concentration in the shallow junction is kept
low. This shallow source/drain extensions thus provides higher parasitic resistance,
which affects the MOSFET performances. The various components contributing to the
parasitic resistances are given in [57]. To minimize this parasitic resistance sillicides
are employed.
2.5.11 Subthreshold Conduction
While we care a lot about the "ON" behavior of MOS devices, it is equally important to
know their "OFF" characteristics. Subthreshold behavior of MOSFET affects the operation
of the dynamic circuits and it has become a significant contributor to power dissipation
in high performance microprocessors (~30%). The Speed ∝ (VDD-VTh) (Speed is
proportional to (VDD-VTh)). As the device dimensions are shrunk below 50 nm the
behavior of the device below the threshold or in the subthreshold regime become
critical. It is not true that that the device turns on abruptly at a gate voltage above the
threshold or that no current flows at the gate voltages below VTh. In subthreshold
conduction, there is a need to account for the current that flows through the channel in
the region below strong inversion i.e. the weak inversion regime which is defined as the
region where the surface band bending ΦS is in the range, Φ F < Φ S < 2Φ F .
The transition from the conducting to the non-conducting state is not sharp, but
continuous. This means that when the gate-source voltage increases, the charge in the
channel is not created abruptly, but appears gradually with Vgs. There is a range of gate
voltages lower than VTh for which there are carriers in the inversion layer that contribute
to the drain current. The actual subthreshold current is not zero but reduces
exponentially below the threshold voltage. Due to subthreshold current
• Ids leakage increases
• Static power increases
• Circuit instability increases
40
Figure 2.12: Energy band diagram of MOSFET in weak inversion
The subthreshold current is diffusion current. By definition the subthreshold

slope S is given by:
ln(10)
dVgs d ln( I ds )
S= = (2.8)
d log( I ds ) dVgs
 qVgs 
Since I ds ∝ exp   , it is possible to write
 nKT 
nkT
S= ln(10) (2.9)
q
Substituting n=1 in (2.9) gives S=60mV/decade (ideal BJT).
2.6 Bulk CMOS Design Solutions for Subthreshold Leakage

Scaling planar MOSFET devices has been the dominant technology option for the past
three decades and it is likely that this trend will continue for another decade. The
“showstoppers” include the gate insulator scaling, the shallow junction technology, the
short channel effects and off-state leakage current in devices with the scaled threshold
and power supply voltages [58]. However, several alternative techniques mentioned in
this section provides tighter control of subthreshold leakage currents. The sub-sections
discuss different technological methods and issues to extend scaling of bulk MOSFET
structure in to the sub-100nm regime.
Triple well or equivalent insulating technologies, are allowing an individual
biasing of each independent p-well and n-well. Therefore, it is possible to tune the N-
channel MOSFET and P-channel MOSFET substrate potentials to the required activity: a
41
positive substrate potential (for an nMOS) will lower the threshold voltage of the
transistors, therefore increasing its dynamic characteristics; on the contrary, a negative
substrate voltage will increase the threshold voltage, consequently minimizing the
subthreshold leakage. This technique, sometimes called variable threshold CMOS
(VTCMOS) [59]. Innovative solutions such as dynamic threshold voltage MOSFETs
(DTMOS) have been successfully used to reduce the leakage power consumption of
analog and digital circuits [60-62].
For a given technology, there is an optimum in reverse body bias, as the
improvement in the subthreshold leakage is compensated by an increase in
source/drain to body junction leakage. Unfortunately, this technique is getting less
effective with technologies scaling down. With high-VTh and low-VTh transistors
simultaneously available, other techniques are proposed: using low-VTh transistors only
in critical paths, or in multi-threshold CMOS (MTCMOS), introducing high-VTh power
switches to limit the leakage current in standby mode. A further level of optimization
introduces multiple VDD in a design.
2.6.1 Polysilicon Gate stack
The gate stack consists of the gate dielectric and the gate contact material. In present
day MOS technology, the gate electrode is invariably made of degenerate polysilicon
(doping concentration > 5 x 1019/cc). Typical thickness of the polysilicon gate is about
0.35 µm. The polysilicon gate technology has many advantages over the aluminum (Al)
gate technology. Some of their advantages are
The polysilicon functions as a gate mask during the high temperature source /
drain diffusion step so as to avoid the alignment difficulties
The stability of the polysilicon-SiO2, interface, and
The threshold voltage of MOSFETs can be changed by varying polysilicon doping.
A disadvantage of the polysilicon gate is its high resistivity compared to the A1 gate.
The problem of high resistivity has been solved by using a combination of polysilicon
with refractory metal silicides (such as CoSi,). The combination is called polycide and
has a lower resistance. For submicron technology, gates are generally polycides. In fact,
self-aligned silicides (called salicides) have become essential ingredients in present day
submicron VLSI technology [63-67].
Metal S/D Schottkybarrier (SB) MOSFET devices replace S/D impurity doping with metal,
typically silicide. There are numerous motivations for replacing doping with metal in the
S/D regions, including low parasitic S/D resistance, low-temperature processing for S/D
42
formation, elimination of parasitic bipolar action, and inherent physical scalability to

sub-10-nm gate-length dimensions [68]. In this process, Titanium (Ti) or Cobalt (Co) film
is first deposited on the wafer after the formation of source/drain and polysilicon gate.
The metal is then reacted with silicon at 600°C to form TiSi2, CoSi2. The silicide is formed
only on the silicon surface (source/drain and polysilicon gate) and not on the oxide. In
this way the silicide has become the metal contact because the contact resistance
between the metal and the silicide is very small.
2.6.2 Source-Drain Structures
High channel electric field is the main culprit for the hot carrier effect in the short
channel devices. To reduce this high channel electric field, deep sub-micron VLSI devices
uses graded drain /source structure instead of the abrupt n+ drain and source to
substrate junctions. Lightly doped junctions are introduced to linearize the junction that
is to reduce the maximum doping level at the junctions.
Lightly doped drain (LDD) structure shown in figure 2.13 is a kind of graded
structure which is the most commonly used source/drain structure used in deep-
submicron devices. By introducing an n- region between the drain and the channel, the
peak channel field is not only shifted towards the drain, but is also reduced to about
80% of the value for a conventional device. Since the peak field is now reduced and
shifted inside the drain region carrier injection into the oxide is reduced resulting in a
more reliable device. This structure results in a higher breakdown voltage and the
substrate current is reduced considerably. Note that the overlap capacitance is also
reduced resulting in a lower gate capacitance and hence higher speed.
In LDD structure additional fabrication steps are required as compared to the
standard source drain structure. Due to the higher series resistance of the n- region,
performance is slightly reduced (4-8%). As the junction depths are scaled down, the
resistivity of the source/drain diffusion region becomes higher which again results in
the higher source/drain resistance and hence the lower transconductance. The channel
length reduction also leads to an undesirable increase in the resistance of the gate line.
To minimize this effect, the MOSFET structure is further modified by creating a silicide
layer at the top of the gate and source/drain to reduce the contact resistance. Therefore,
low resistivity materials such as refractory metal silicides are often used to reduce this
resistance in a LDD structure.
43
Figure 2.13: Deep-submicron MOSFET structure with Lightly Doped Drain (LDD) and
silicided gate and source/drain contacts
2.7 Introduction to SiGe or Strained Si MOSFET for

Higher Mobility
Beyond 100nm, it is difficult to reduce dimensions like the gate oxide thickness,
alternative methods of improving transistor performance are also being employed. One
important approach is to increase the electron and hole mobility. The carrier mobility in
a semiconductor derives from the band structure of the material; thus a modification of
the semiconductor band structure usually changes the mobility of one or both charge
carriers. Electron mobility in Si augments when the crystal lattice is subjected to tensile
stress, whereas compressive stress tends to improve hole mobility. Stress can be applied
mechanically as part of the packaging process.
Stress can also be built right into the semiconductor crystal by incorporating
comparatively large Ge atoms into the narrower Si lattice or by combining two layers of
materials with distinct lattice spacing. The epitaxial growth of the strained SiGe
compounds on the Si substrates allows the strain in the Si and SiGe layers to be tuned.
In Si under tensile strain and in SiGe under compressive strain, the electron and hole
motilities, respectively, are enhanced [69-71]. Carrier mobility’s higher than those of
conventional Si MOSFETs have been reported in SiGe or strained silicon channel MOSFET
[72]. The approaches involving local uniaxial strain through the use of stressed nitride
films as the source of tensile strain and strained SiGe layers in the source and the drain
region for applying the compressive strain are employed in current products. For
example, Intel utilizes local uniaxial tensile strain for nMOS devices and local uniaxial
44
compressive strain for pMOS devices in 90 nm and 65 nm high-performance single and

dual core microprocessors [73]. The technology is mature and is being ramped into high
volume manufacturing to fabricate next generation Pentium® and Intel® Centrino™
processor families [74]. IBM and AMD have introduced strained Si with SOI technology in
their 90 nm high performance microprocessors including IBM’s PowerPC chips and the
multi-core AMD64 processors [75-76].
2.8 Introduction to Novel MOSFET structures
Conventional scaling based on the reduction of feature sizes obviously cannot continue
forever [77]. According to the conventional scaling theory, if all the dimensions and
voltages of a MOSFET are scaled by a scaling factor α, the circuit speed increases in
proportion to the factor α and circuit density increases by α2 [78]. However, this scaling
trend has hit roadblocks due to the various second order effects and the fundamental
physical limitations.
There are several constraints to continued scaling of conventional MOSFETs,
mainly the minimum gate oxide thickness needed to control the gate leakage current,
the solid solubility limit for the channel doping concentration, and a minimum voltage
supply to manage the noise margin of the device. These effects arise due to the velocity
saturation, non-scaling of the subthreshold slope and built-in potential of source/drain
to the body junctions, quantum effects [79], poly depletion effects [80-81], and high-
field effects etc. [82-85].
It is likely that scaling of the conventional planar MOSFET may hit the physical
barriers within this decade. If the bulk planar MOSFET cannot improve the circuit
performance, different materials systems or alternative device architectures may be
required to continue the CMOS scaling. There exists other alternative technologies that
may succeed the conventional CMOS devices in the future ultrashort-channel devices.
Therefore, The industry is pursuing two fundamentally distinct approaches to managing
these scaling challenges—bulk transistors enhanced using new materials for the gate
stack, etc., and new transistor structures.
In this chapter, the status of research or more precisely a literature review on the
prospects of promising material systems and alternative device architectures is
presented to circumvent detrimental short-channel effects (SCEs). Among the different
material systems, metal gate technology as the gate material and the physics of High-K
dielectric as the gate insulator will be discussed. In the midst of many interesting
structures proposed so far, we choose to analyze the HALO doped CMOS technology,
45
the Silicon-On-Insulator (SOI) MOSFET, the double-gate (DG) MOSFET, the FinFETs and the
surrounding-gate MOSFETs.
2.9 High-K gate Materials
The down-scaling rules require a simultaneous reduction in the gate-oxide thickness and
increase in the substrate doping to eliminate the drain influence in the gate region. Also,
to achieve a large current drive in a MOSFET, a large Cox (or small tox) is desirable. A
problem here is that the oxide thickness needs to be about 1nm. Even if an almost
perfect oxide of 1nm thickness was technologically available, the electrons would tunnel
through the 1-nm barrier. High gate tunnel current can flow between the gate and the
substrate as the thickness of the gate oxide is reduced below a few nanometers (10-20
Å). Therefore, SiO2 gate dielectric scaling has stopped at the thicknesses close to 10 Å,
as the gate leakage currents due to the “quantum mechanical tunneling” through this
“insulator” have reached values of >100A/cm2 in transistors aimed at high performance
applications. With such a high gate-current, the problem with power dissipation would
re-appear in another form.
For control over the channel region by the gate voltage, it does not matter
whether the oxide thickness is reduced or the permittivity is increased. Fortunately,
there are dielectric materials with permittivity hundreds and even more than the
permittivity of the silicon dioxide. Obviously, by using them the same field strength
could be achieved with much thicker dielectric layers. Therefore, to sustain the
continued density and performance increases, much of the attention has turned to the
modified device structures and to new materials, among them high-permittivity (“high-
k”) gate dielectrics such as hafnium oxide (HfO2) to replace SiO2.
The gate capacitance of a MOS transistor using an arbitrary dielectric material
with thickness Td is given by
ε 0kd A
COX = (2.10)
Td
where ε0 is the permittivity of free space, kd is the relative permittivity of dielectric
material, A is the area of the conducting plates and Td is the thickness of the arbitrary
gate dielectric material. From the above relationship, the thickness of the high-k
dielectric insulator is expressed as
kSiO2
tOX = Effective Oxide Thickness (EOT) = Td (2.11)
kd
46
HfO2 has a relative permittivity of k HfO2 ≈24, six times larger than that of SiO2
( k SiO2 ≈3.9). Therefore, a 6nm HfO2 film has EOT of 1nm, in the sense both films produce
the same oxide capacitance. Materials such as hafnium oxide (HfO2), aluminum
oxide (Al2O3), and many others are being studied as possible candidates (kSiO2 =
3.9; kHfO2≈ 20–25) to continue gate dielectric scaling [86-87] as shown in figure 2.14.
However, there are significant challenges for all of them to succeed the Si/SiO2
material system, which has been dominant in manufacturing over the last three
decades. The biggest disadvantage with high-k gate dielectric materials has always been
the issue of much poorer interface between these films and silicon, as compared to
native silicon-silicon dioxide interface. Materials with a higher dielectric constant
show a tendency to be associated with a lower band-gap, which reduces the
effectiveness of these materials in suppressing gate leakage current. The excellent
property offered by silicon dioxide outweighs the comparative disadvantage of low
dielectric permittivity. In recent years, some work has been done on the use of high-k
materials in the oxide region was suggested [88-90].
Figure 2.14: a) schematic cross section of bulk n-channel MOSFET with a) silicon
dioxide as gate dielectric b) High K Gate Dielectric to Reduce Direct Tunneling c)
gate stack of thin silicon dioxide and thick high-K material layer
High dielectric constants (Κ = 50) are sometimes not preferred due to two-
dimensional (2-D) effects and since on increase of dielectric constant the capacitance
(CV/I) is adversely affected, hence, many researchers have restricted their analysis with
high dielectric constant of 20 only where they do not need to include the CV/I effect
[91]. However, to get rid of hot-carrier effects advancing innovative techniques and
novel architectures involving gate-oxide-engineered structures using stack of a thin SiO2
and thick high-k layer are now given extensive consideration [92]. There has been work
47
dedicated to the gate-stack structure with a gate oxide of SiO2 as an interfacial buffer
between the bulk silicon and the high-k dielectrics can screen the effect of phonon
scattering and improve the carrier mobility [93-94].
2.10 Channel Engineering and Gate engineering

technology
In addition to gate oxide thickness scaling, another technique to improve short-channel

characteristics is well/channel engineering. By changing the doping profile in the
channel region, the distribution of the electric field and potential contours can be
changed. The goal is to optimize the channel profile to minimize the OFF-state leakage
[95] while maximizing the linear and saturated drive currents. Advanced MOSFETs are
non-uniformly doped because of complex process flow both in lateral and vertical
directions as shown in figure 2.15. Basically, non-uniform doping profiles can be
categorized into vertical and lateral direction, collectively referred as channel
engineering. The vertical non-uniformity can be due to additional implantation for
threshold voltage adjustment or for punchthrough prevention. On the other hand,
lateral non-uniformity may be due to the intended pocket implantation. Therefore, one
of the key factors to model threshold voltage accurately is to model its non-uniform
doping profile [96]. Currently, there are many VTh models [97-99] that are able to model
the vertical non-uniform doping profile of a MOSFET.
Figure 2.15: MOSFET with both vertical and horizontal non-uniform doping profiles
Retrograde doping: The surface at the oxide interface contains a low doping with the
highest doping is slightly below the semiconductor surface. Such a profile is achieved
with ion implantation, known as the retrograde profile. Just below the Si-SiO2 interface,
48
the lower doping is used to take advantage of the higher mobility due to reduced field,
which also lowers the threshold voltage. The high peak concentration below the surface
is to control the punch-through and other short-channel effects. A lighter doping at the
deeper region reduces drain-substrate capacitance and also the substrate-bias effect.
Figure 2.16 below shows MOSFET structure with the retrograde channel doping profile.
On the other hand, the device drive current degradation is usually observed with the
retrograde channel profiles [100]. Recently, the conventional and the retrograde n
channel MOSFET have been compared using the simulation in the literature for 0.1µm
generation [101] and 50 nm [102].
Figure 2.16: MOSFET planar structure with a retrograde channel doping profile, LDD
source/drain junction, and self-aligned silicide source/drain contact
2.10.1 Reverse short-channel effect (RSCE) & HALO doping
To reduce the DIBL effect in a short-channel MOSFET, the substrate doping

concentration can be increased at the edges of the source and the drain junctions.
These regions with increased doping concentration are commonly called “HALO” (figure
2.18 below). When the channel length is reduced in halo devices the average channel
doping concentration (per gate unit length) increases. This causes the threshold voltage
to increase when gate length is reduced. This phenomenon is called the “reverse short-
channel effect” as shown in figure 2.17 below. At shorter gate lengths, however, the
regular short-channel effect becomes dominant and the threshold voltage drops. The VTh
roll-off can be reduced or even reversed, i.e., the VTh increases with decreasing channel
length, by locally raising the channel doping next to the drain or drain/source junctions.
In the past few years, the locally high doping concentration in the channel near
source/drain junctions has been implemented via lateral channel engineering, e.g.,
49
HALO or pocket implants. The two terms are used interchangeably here although a
HALO may connote a pocket that is deeper than the drain. The implant can be either
symmetrical or asymmetrical with respect to the source and the drain. It is found that VTh
of all devices decrease as VDS increases, but the amount of VTh drop because of DIBL
effect is remarkably reduced in the pocket-implanted devices. When the RSCE is present,
VTh is a more nonlinear function of VDS in the pocket-implanted devices than in uniformly
doped devices [103]. A simple equation to consider the lateral nonuniform doping has
been derived in BSIM3v3 [104]. The body effect is affected by the pocket implant due to
heavier p-type doping concentration near the S/D region. For a MOSFET with a given
pocket implant, the body effect is expected to be worse when channel length becomes
shorter [103]. In summary, the improvement of short channel immunity is traded-off
with the degradation of current drive, the junction capacitance, and the body effect. An
optimum design of pocket implant should be determined using the requirements (or
tolerance) set by the both the VTh roll-off and all the other electrical parameters.
Threshold voltage in [V]
Figure 2.17: Reverse short channel Effect
The so-called Reverse Short-Channel Effect (RSCE) [105-108] was originally

observed in MOSFET’s due to oxidation-enhanced-diffusion or implant-damage-enhanced
diffusion [109] which are very difficult to control.
In the past few years, the locally high doping concentration in the channel near
source/drain junctions has been implemented via lateral channel engineering, e.g., halo
[110] or pocket implants [111]. The two terms are used interchangeably here although a
halo may connote a pocket that is deeper than the drain. The implant can be either
symmetrical [111-112] or asymmetrical [113] with respect to source and drain.
50
Figure 2.18: a) n-channel MOSFET with HALO structure b) Threshold voltage

variation
In the past few years, the local high doping concentration in the channel near
source/drain junctions has been implemented via lateral channel engineering, e.g. halo
[114] or pocket implants [111]. Single halo MOSFET structures have been introduced for
bulk [115] as well as for SOI MOSFETs [116] to adjust the threshold voltage and improve
the device SCEs. Halo implantation devices show excellent output characteristics with
low DIBL, no kink, higher drive currents, flatter saturation characteristics, and slightly
higher breakdown voltages compared to the conventional MOSFET.
In this doped devices, under the edges of the gate, in the vicinity of what will
eventually become the end of the channel, point defects are injected during sidewall
oxidation. These point defects gather doping impurities from the substrate, thereby
increasing the doping concentration near the source and drain end of the channel [117-
120]. More highly doped p-type substrate near the edges of the channel reduces the
charge-sharing effects from the source and drain fields, thus reducing the width of the
depletion region in the drain-substrate and source-substrate regions. As the channel
length is reduced, these highly doped regions consume a larger fraction of the total
channel charge. Reduction of charge-sharing effects reduces the threshold voltage
degradation due to the channel length reduction. Thus, threshold voltage dependence
on channel length becomes more flat as shown in figure. 2.17. Hence, the off-current
becomes less sensitive to channel length variation. The reduction in the drain and the
source junction depletion region width also reduces the barrier lowering in the channel,
thus reducing DIBL. Since the channel edges are more heavily doped and junction
depletion widths are smaller, the distance between the source and the drain depletion
regions is larger. This reduces the punch through possibility.
51
2.10.2 Gate Engineering Technology
In order to minimize hot electron effect and to give more control of the gate over the
conductance of the channel [34] so as to increase gate transport efficiency a dual
material gate structure has been proposed. In 1999, Long et al. [121] proposed a new
gate structure called the dual material gate struture uses two different metal gates with
different work functions amalgameted together causing a step in surface potential
profile. In the DMG-MOSFET, the work function of metal gate1 (M1) is greater than metal
gate2 (M2) i.e., ФM1> ФM2 and hence, threshold voltage which has the inherent advantage
of improving the gate transport efficiency by modifying the electric field pattern and the
surface potential profile along the channel. A dual-material gate MOSFET structure can
provide improvent in the reduction of SCE since the step-shape in the surface potential
profile screens the effects of drain on the device channel, also resulting in an increase
the carrier transport efficiency by increasing the average Electrid Field [122-130].
Beyond saturation, M2 absorbs any additional drain-source (D/S) voltage and hence the
M1region is screened from the drain potential variations. To enhance the immunity
against the short channel effects and therefore improve the device reliability in high
performance circuit applications, a new device structure triple material (TM) double-gate
(DG) MOSFET is proposed [131]. Models for the surface potential and the electric field
distribution in the dual-/tri-material gate devices [132] and the fully depleted (FD) DMG
silicon-on-insulator (SOI) devices [133] are proposed. Chen et. al. [134] suggested a new
variant of triple material device structure known as the tri-material gate-stack (TRIMGAS)
MOSFET to reduce gate leakage current.
2.11 Silicon-on-Insulator (SOI) Technologies
SOI structures are considered as the most attractive alternative to conventional bulk
CMOS technology. For several years, silicon-on-insulator (SOI) technologies have been
developed to improve the performance of bulk technologies [135-137].
Conventional bulk CMOS and that SOI uses the same basic technology.
Therefore, SOI devices can leverage the great technological strides that have been
realized in Si-based integrated circuits.
The main difference between bulk and SOI substrates is the buried oxide layer
located below the active silicon layer (i.e., layer where the MOSFET devices are
processed). A cross-section of an SOI MOSFET is shown in figure 2.19.
52
Figure 2.19: a) planar bulk b) fully depleted SOI MOSFET
Due to the presence of the buried oxide, however, the parasitic capacitances are
reduced, and this allows switching characteristics that are faster than those of bulk
MOSFETs [138-139]. SOI CMOS technology is likely to be an alternative for deep sub-
micron CMOS. It appears to be the best option for low-power electronics. SOI MOSFETs
provide the reduced capacitance, the low body effect, the sharp subthreshold slope and
the high current driving capability. Therefore, they offer excellent the low-power and
low-voltage performance. SOI technology has attracted many major IC companies.
2.11.1 SOI CMOS Design Solutions for Subthreshold Leakage
Each SOI transistor has its own individual substrate usually called the “body.” In fully
depleted SOI technologies, the body potential roughly follows the source potential. The
advantage of this technology will be directly related to the better subthreshold swing of
the devices [140-141].
2.11.2 Partially depleted SOI (PD- SOI)
If the thickness of silicon film tSi is larger than the strong inversion depletion width, then
the channel region is partially depleted during device operation. In many respects, the
device characteristics of PD-SOI are similar to those of conventional bulk devices.
Partially depleted silicon MOSFETs are the successors of earlier SOS (Silicon-On-Sapphire)
devices, which is the first of the SOI technology realized [29-31]. PDSOI MOSFETs were
first used in applications like radiation-hardened or high-temperature electronics [142-
146].
53
Figure 2.20: a) Fully depleted b) Partially depleted SOI MOSFET
2.11.3 Fully Depleted SOI (FD-SOI)
Thus, the scaling scenario for PD-SOI may not go beyond the 70-nm technology node
where the gate length is about 30 nm. One possible solution to the problem of how to
scale devices beyond this limit is a FD-SOI. If the SOI layer is very thin so that the
depletion region extends to the bottom Si/SiO2 interface, the device channel is fully
depleted. FD-SOI provides better control of SCEs as compared to PD-SOI. However, to
take full advantage of FD operation, a very thin silicon channel (~10 nm) is required to
reduce the effective junction depth, which may not be easily manufactured. In addition,
the series resistance of the thin channel and shallow source/drain regions in thin SOI
films will degrade device performance.
As a result, to take the advantage of the good short-channel
characteristics of FD-SOI, an extremely thin silicon channel is required to reduce
the influence of electric fields from S/D. However, there are problems with making
SOI MOSFETs with extremely thin channels. First, the series resistance in the thin SDE
region degrades ION. We may solve this issue by using raised source drain extensions.
Second, as we saw in the previous section, with current SOI fabrication methods, it is
very difficult to control the silicon channel thickness with the accuracy required for fully-
depleted SOI. Overall, FD-SOI may not be a more attractive choice than PD-SOI [147].
54
2.12 Multiple Gate MOSFET
The classical CMOS structure is reaching its scaling limits and “end-of-roadmap”
alternative devices are being investigated. In a continuous effort to increase the current
drive and better control of short-channel effect, multiple gate SOI MOSFET has evolved
from conventional bulk planar single-gate MOSFETs [148-149].
This multiple-gate (MuG) or ultra-thin-body (UTB) silicon-on-insulator (SOI)
MOSFETs, are very promising in terms of its SCE suppression capability without any high
channel doping concentrations, resulting in enhanced carrier mobilities. In recent years,
non-classical CMOS devices such as such as FinFETs and its variants have received
considerable attention owing to their capability of suppression of short channel effects,
the reduced drain-induced barrier lowering and excellent scalability to provide a path to
scaling CMOS to the end of the roadmap.
2.12.1 Double Gate MOSFET
A double-gate transistor is one having surface conduction channels on two opposite

horizontal surfaces and having current flow in the horizontal direction [150]. The
channel length is given by the horizontal separation between source and drain and is
defined by a lithographic step combined with an etch process [8].
In 1984, T. Sekigawa et. al. showed that it is possible to obtain significant
reduction in short-channel effect by using a FDSOI structure sandwiched between two
gates [151]. The double gate (DG) structure termed as XMOS exhibits a better control of
the channel depletion region due to the reduction of the drain electric field on the
channel. Later Frank et. al. claimed that ultimate silicon device is a DG device [152].
The concept has been gradually explored both experimentally and theoretically by many
groups. The Monte Carlo and drift-diffusion modeling clearly showed that a DG FET can
be scaled to a very short channel length (25 to 30 nm) while achieving the expected
performance derived from scaling.
All recent studies indicate that the ultra-thin body double gate (DG) SOI MOSFET
is the ideal device structure for ultimate scaling [153-158]. There is a very thin Si layer
for a channel, with two gates, one on the each side of the channel [159]. The two gates
are electrically connected so that they both serve to modulate the channel. Short
channel effects are greatly suppressed in such a structure because the two gates very
effectively terminate the drain field lines, preventing the drain potential from being felt
at the source end of the channel as shown in figure 2.21 below. Consequently, the
variation of the threshold with drain voltage and with gate length of a double-gated FET
55
is much smaller than that of a conventional single-gated structure of the same channel
length [160-161].
It should be also noticed that high body doping is not needed here, so the band-
to-band tunneling junction leakage is no longer a big concern. Moreover, the use of
ultra-thin bodies will result in reduced metallurgical junction perimeter, therefore low
junction capacitance.
Advantage of double gate MOSFET
a) Enhanced scalability b) Lower junction capacitance c) Light doping is possible
d) Larger drive current e) Improved subthreshold slope f) Improved SCE
Scaling issues of double gate MOSFET:
a) Gate alignment b) Higher series source and drain resistance. Raised source to
drain structure is required to lower it c) Difficult to fabricate, particularly in this
SOI configuration d) Integrability and process complexity
Figure 2.21: Field lines for Single gate and double gate SOI MOSFETs
2.12.2 FINFET
The FinFET, another form of double-gate structure, consists of a channel formed in a

vertical si fin controlled by a self-aligned double-gate as shown in the figure 2.22 below
[162]. It captured the attention and fascination of the scientific community, and in
recent years an explosion in research and development efforts into FinFETs [163-170] is
observed. The fin is made thin enough when viewed from the above such that the two
gates control the entire fully-depleted channel film. Although it is a double-gate
56
structure, the FinFET is similar to the conventional planar MOSFET in the layout and the
fabrication. It provides a range of channel lengths, CMOS compatibility and large
packing density compared to other double-gate structures. N-channel FinFETs have been
reported to show good short-channel performance down to a gate-length of 17nm. The
top view of a FinFET is shown in figure 2.23 below. As the single-Gate CMOS scaling is
approaching the limit imposed by “gate oxide tunneling”, multiple-gate structures are
getting high importance. The objective of these structures is to achieve an additional
gate control over the channel and prevent fringing fields from penetrating into the
silicon body [171].
To prevent encroachment of electric field lines from the drain on the channel region,
variant of FiNFETs with special gate structures can be used. Figure 2.24 shows some
multiple gate devices termed as the double-gate transistors, the triple gate devices, the
FinFET, the Π gate, Gate All Around( GAA) devices. The best performance is obtained
from the GAA and Π gate is close second.
Figure 2.22: Perspective view of FinFET
Figure 2.23: top view of FinFET with arrow indicates current flow
57
Figure 2.24: Types of Multiple-Gate Devices 1) Single gate 2) Double gate 3) Triple
gate 4) Quadruple gate/gate all around (GAA) 5) Π gate
2.12.3 Surrounding Gate MOSFETs
Among various multiple gate structures, in theory, the SG MOSFETs can provide the best
electrostatic integrity. When the gate completely surrounds a channel as in the
cylindrical, surrounding–gate (Cyl) MOSFET, the electrostatic control is superior.
The surrounding gate MOSFET is a type of the vertical DG MOSFET in which the
cross-section of the silicon channel has a cylindrical shape and the gate electrode
completely surrounds the device channel region. A schematic cross-section diagram of a
cylindrical MOSFET is shown in figure 2.25. With the downscaling of MOSFETs, the
silicon nanowire (NW) transistor (SNWT) with the gate-all-around (GAA) structure is
considered one of the most promising candidates in the deca-nanometer regime due to
its excellent electrostatics, quasi-ballistic transport properties and CMOS compatibility
[171-172]. The first surrounding-gate MOSFETs were fabricated by wrapping a gate
electrode around a vertical silicon pillar. The device can be circular section [173] or
square section [174]. Recently, fully functional planar surrounding gate devices has been
reported [174-177].
Figure 2.25: Cross section of a surrounding gate MOSFET
58
Summary
In this chapter, a comprehensive literature review of the potential difficulties associated
with scaling and its remedies are presented. The motivation behind scaling is presented
first, then the classification of scaling and their relative merits and demerits are
discussed. The cause and effect of most of the several short channel effects discussed
next. A review of existing and upcoming technology developments to provide better
immunity to short channel effects is discussed. Different technologies like gate material
engineering, channel engineering employed to alleviate SCEs are discussed. The
evolution of SOI technology from bulk CMOS is traced. This is followed by looking at the
evolution of FinFET technologies; the main flavors (variants) of multigate MOSFETs; and
their advantages/disadvantages. The RF/analog performance of advanced device
structures has also been reviewed. The various aspects and challenges associated with
advanced SOI MOSFETs are also discussed. In conclusion, the rigorous gate length
scaling capability that has been the distinguishing feature of the CMOS technology is
facing severe challenges due to the undesirable SCEs. Therefore, it is mandatory to hunt
for alternative approach so as to gain immunity against SCEs as discussed in this
chapter. In this respect, multiple gate MOSFETs and its variants evolves as the most
promising choice to sustain scaling of CMOS into the deca-nanometer era and thus
founds its suitability for SoC applications.
References
[1] Gordon Moore, (1965) Cramming more Components onto Integrated Circuits, Electronics,
vol. 38, pp. 114–117, April 19, 1965
[2] Claudio Fiegna, “The Effect of Scaling on the Performance of Small-signal MOS Amplifiers,”
Proc ISCAS 2000, pp. 733-736, May. 2000
[3] R.H. Dennard, F.H. Gaensslen, L. Kuhn and H.N. Yu, “Design of micron MOS switching
devices” IEDM Dig. Techn. Pap. , pp. 344, 1972
[4] R.H. Dennard, F.H. Gaensslen, H.N. Yu, Yu.V.I. Rideout, E. Bassous and A.R. Leblanc,
“Design of ion-implanted MOSFET's with very small physical dimensions. “ IEEE J. Solid-
State Circuits 9 , pp. 256, 1974
[5] R.H. Dennard, F.H. Gaensslen, E.J. Walker and P.W. Cook, “1µm MOSFET VLSI technology:
Part II — Device design and characteristics for high-performance logic applications.” IEEE J.
Solid-State Circuits 14, pp. 247, 1979
[6] Brews J. R., Fichtner W., Nicollian E. H., and Sze S. M. (1980) Generalized guide for
MOSFET miniaturization, IEEE Electron Device Lett., EDL-1, 2
[7] D. J. Frank et. al., “Device scaling limits of Si MOSFETs and their application
dependencies,” Proc. IEEE, vol. 89, pp. 259–288, Feb. 2001
[8] International Technology Roadmaps for Semiconductor (ITRS), 1999 and 2005,2009,2011
edition [available on http://www.itrs.net]
[9] Chih-Tang Sah, “Evolution of the MOS transistor – From conception to VLSI,”Proc. IEEE, vol.
76, no. 10, pp. 1280-1326, Oct. 1988
[10] D. Buss, Device issues in the integration of analog/RF functions in deep submicron digital
CMOS," Tech. Digest IEDM, pp. 423{426, 1999
[11] Daniel P. Foty, MOSFET Modeling with SPICE - Principles and Practice, Prentice Hall, Upper
Saddle River, NJ, 1997
59
[12] Lee K, Shur M, Fjeldly TA, Ytterdal T. Semico nductor device modeling for VLSI. Engle
wood Cliffs, NJ: Prentice Hall; 1993
[13] Henk C. de Graaff and François M. Klaassen, Compact Transistor Modelling for Circuit
Design, Springer-Verlag, Wien, 1990,
[14] Narain Arora, MOSFET Models for VLSI Circuit Simulation Theory and Practice, Springer-
Verlag, Wien, 1993
[15] Yannis Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed. , McGraw- Hill,
Boston, 1999
[16] Andrei Vladimirescu, The SPICE Book, John Wiley & Sons, New York, 1994
[17] Kenneth S. Kundert, The Designer’s Guide to SPICE & SPECTRE, Kluwer Academic
Publishers, Boston, 1995
[18] Harold Shichman and David A. Hodges, “Modeling and simulation of insulated-gate field-
effect transistor switching circuits,” IEEE J. Solid-State Circuits, vol. 3, no. 5, pp. 285-289,
Sep. 1968
[19] John E. Meyer, “MOS models and circuit simulation,” RCA Review, vol. 32, pp. 42-63, Mar.
1971
[20] Donald E. Ward and Robert W. Dutton, “A charge-oriented model for MOS transistor
capacitances,” IEEE J. Solid-State Circuits, vol. 13, no. 5, pp. 703-708, Oct. 1978
[21] Bing J. Sheu, Donald L. Scharfetter, Ping-Keung Ko, and Min-Chie Jen, “BSIM: Berkeley
Short-Channel IGFET Model for MOS transistors,” IEEE J. Solid-State Circuits, vol. 22, no. 4,
pp. 558-566, Aug. 1987
[22] BSIM4.0.0 MOSFET Model, User's Manual, Department of Electrical Engineering and
Computer Science, University of California, Berkeley CA, 2000
[23] William Liu, MOSFET Models for SPICE Simulation, Including BSIM3v3 and BSIM4, John
Wiley & Sons, New York, 2001
[24] G. Gildenblat et. al., “PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit
Simulation,” IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 1979-1993, Sept. 2006
[25] M. Suetake et. al., HiSIM: A drift-diffusion-based advanced MOSFET model for circuit
simulation with easy parameter extraction," Proc. SISPAD, pp. 261-264, 2000
[26] Christian C. Enz, François Krummenacher, and Eric A. Vittoz, “An analytical MOS transistor
model valid in all regions of operation and dedicated to low-voltage and low-current
applications,” J. Analog Integr. Circuits Signal Process., vol. 8, pp. 83-114, July 1995
[27] Kahng, D. "A historical perspective on the development of MOS transistors and related
devices," Electron Devices, IEEE Transactions on , vol.23, no.7, pp. 655- 657, Jul 1976
[28] Fonstad C. G. (1994) Microelectronic Devices and Circuits, McGraw-Hill, New York.
[29] E. Rosenbaum, Oxide Reliability, 1996 IEEE International Reliability Physics Symposium,
Tutorial Notes, Topic 6a, pp. 6a.1-6a.27
[30] R. Degraeve, Oxide Reliability, 1997 IEEE International Reliability Physics Symposium,
Tutorial Notes, Topic 7, pp. 7.1-7.71
[31] D. J. DiMaria, E. Cartier, Mechanism for Stress-Induced Leakage Currents in Thin Silicon
Dioxide Films, J. Appl. Phys. Vol. 78, 1995, pp. 3883-3894
[32] S. Wolf, “Silicon Processing for the VLSI Era – Volume III – The Submicron MOSFET”, Lattice
Press, California, 1995
[33] Brews, J. R. (1990). The submicron MOSFET, in High Speed semiconductorDevices, edited
by S. M. Sze. New York:Wiley
[34] Yuan Taur and Edward J. Nowak, “CMOS devices below 0.1 µm: How high will performance
go?” IEDM Tech. Dig., pp. 215-218, 1997
[35] Bin Yu; Wann, C.H.J.; Nowak, E.D.; Noda, K.; Chenming Hu; , "Short-channel effect
improved by lateral channel-engineering in deep-submicronmeter MOSFET's," Electron
Devices, IEEE Transactions on , vol.44, no.4, pp.627-634, Apr 1997
[36] Shur M. (1990) Physics of Semiconductor Devices, Prentice Hall, Englewood Cliffs, NJ
[37] M. Lenzlinger and E. H. Snow, “Fowler-Nordheim Tunnelling in Thermally Grown SiO2,” J.
Appl. Phys., vol. 40, pp. 278–283, Jan. 1969
[38] E. Harari, L. Schmitz, B. Troutman, and S. Wang, “A 256-Bit Nonvolatile Static RAM,” in IEEE
Int. Solid-State Circ. Conf. Dig., pp. 108–109, Feb. 1978
[39] W. S. Johnson, G. Perlegos, A. Renninger, G. Kuhn, and T. R. Ranganath, “A 16 kB Electri-
cally Erasable Nonvolatile Memory,” in IEEE Int. Solid-State Circ. Conf. Dig., pp. 152–153,
Feb. 1980
[40] R. V. Langevelde, A. J. Scholten, R. Duffy, F. N. Cubaynes, M. J. Knitel, and D. B. M.
Klaassen, “Gate Current: Modeling, L Extraction and Impact on RF Performance,” in Proc.
Int. Electron.Device Meet., pp. 13.2.1–13.2.4, Dec. 2001
60
[41] R. v. Langevelde, “MOS Model 11,” Nat. Lab.Unclassified Report, vol. NL-UR 2001/813,
Apr. 2001
[42] Ytterdal T., Kim S. H., Lee K., and Fjeldly T. A. (1995) A new approach for modeling of
current degradation in hot-electron damaged LDD NMOSFETs, IEEE Trans. Electron
Devices, ED-42, 362–364 (1995)
[43] Stathis J. H. (2002) Reliability limits of the gate insulator in CMOS technology, IBM J. Res.
Dev., 46(2/3), 265–286
[44] Fjeldly T. A., Ytterdal T., and Shur M. (1998) Introduction to Device Modeling and Circuit
Simulation, John Wiley & Sons, New York
[45] I˜niguez B. and Fjeldly T. A. (1997) Unified substrate current model for MOSFETs, Solid-
State Electron., 41, 87–94
[46] S. M. Sze, Semiconductor Devices: Physics and Technology, 2nd ed. John Wiley & Sons,
1981.
[47] Selberherr, S. (1984). Analysis and Simulation of Semiconductor Devices. Vienna: Springer-
Verlag
[48] Lee K., Shur M., Fjeldly T. A., and Ytterdal T. (1993) Semiconductor Device Modeling for
VLSI ,Prentice Hall, Englewood Cliffs, NJ
[49] P. K. Ko, “Approaches to Scaling,” in Advanced MOS Device Physics, ser. VLSI Electronics
Microstructure Science
[50] N. G. Einspruch and G. S. Gildenblat, Eds. Academic Press, 1989, vol. 18, pp. 1–37
[51] K.K. Ng andW.T. Lynch, The Impact of Intrinsic Series Resistance on MOSFET Scaling, IEEE
Trans. Electron Dev., 34(3), 503–511, 1987.
[52] Liu, Z.-H.; Hu, C.; Huang, J.-H.; Chan, T.-Y.; Jeng, M.-C.; Ko, P.K.; Cheng, Y.C.; , "Threshold
voltage model for deep-submicrometer MOSFETs," Electron Devices, IEEE Transactions on ,
vol.40, no.1, pp.86-95, Jan 1993
[53] K.W. Terril, C. Hu and P.K. Ko, An Analytical Model for the Channel Electric Field in
MOSFETs with Graded-Drain Structures, IEEE Electron Dev. Lett., 5(11), 440–442, 1984
[54] Compact MOSFET models for VLSI design by Bhattacharyya, A, Wiley-IEEE Press, 2009
[55] H. Kurata and T. Sugii, Impact of Shallow Source/Drain on the Short Channel
Characteristics of pMOSFETs, IEEE Electron Dev. Lett., 20(2), 95–96, 1999
[56] K. Suzuki, Short Channel MOSFET Models Using a Universal Channel Depletion Width
Parameter, IEEE Trans. Electron Dev., 47(6), 1202–1208, 2000
[57] E. Gondro, P. Klein and F. Schuler, An Analytical Source-and-Drain Series Resistance Model
of Quarter Micron MOSFETs and its Influence on Circuit Simulation, in Proceedings of the
IEEE International Symposium on Circuits and Systems, Vol. 6, pp. 206–209, June 1999
[58] Plummer, J.D.; , "Silicon MOSFETs (conventional and non-traditional) at the scaling limit,"
Device Research Conference, 2000. Conference Digest. 58th DRC , vol., no., pp.3-6, 2000
[59] Hyunsik Im; Inukai, T.; Gomyo, H.; Hiramoto, T.; Sakurai, T.; , "VTCMOS characteristics
and its optimum conditions predicted by a compact analytical model," Very Large Scale
Integration (VLSI) Systems, IEEE Transactions on , vol.11, no.5, pp.755-761, Oct. 2003
[60] F. Assaderaghi et. al.. "A dynamic threshold voltage MOSFET (DTMOS) for very low voltage
operation," IEEE Electron Device Lett., vol. 15, no. 12, pp. 510-2, Dec. 1994
[61] M.J. Chen et. al. "Back-gate forward bias method for low-voltage CMOS digital circuits,"
IEEE Trans. Electron Devices, vol. 43, no. 6, pp. 904-10, Jun. 1996
[62] S. Chatterjee, Y. Tsividis, and P. Kinget. "0.5-V analog circuit techniques and their
application in OTA and filter design," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2373-
87, Dec. 2005
[63] S. Zhu et. al. “N-type Schottky barrier S/D MOSFET using Ytterbium silicide,” IEEE Electron
Device Lett., vol. 25, no. 8, pp. 565–567, Aug. 2004
[64] J. Kedzierski et. al. “Complementary silicide S/D thin-body MOSFETs for the 20 nm gate
length regime,” in IEDM Tech. Dig., 2000, pp. 57–60
[65] B.-Y. Tsui and C.-P. Lin, “A novel 25-nm modified Schottky-barrier FinFET with high
performance,” IEEE Electron Device Lett., vol. 25, no. 6, pp. 430–432, Jun. 2004
[66] D. Connelly, C. Faulkner, and D. E. Grupp, “Optimizing Schottky S/D offset for 25-nm
dual-gate CMOS performance,” IEEE Electron Device Lett., vol. 24, no. 6, pp. 411–413, Jun.
2003
[67] A. Itoh, M. Saitoh, and M. Asada, “A 25-nm-long channel metal-gate p-type Schottky S/D
metal-oxide-semiconductor field effect transistor on separation-by-implanted-oxygen
substrate,” Jpn. J. Appl. Phys., vol. 39, no. 8, pp. 4757–4758, Aug. 2000
61
[68] Larson, J.M.; Snyder, J.P. "Overview and status of metal S/D Schottky-barrier MOSFET
technology," Electron Devices, IEEE Transactions on , vol.53, no.5, pp. 1048- 1058, May
2006
[69] R. Hartmann et. al. “Si/SiGeC Heterostructures: A path towards high mobility channels”, in:
S. Luryi, J. Xu, and A. Zaslavsky (Eds.), Future Trends in Microelectronics (1999 John Wiley
& Sons, Inc), pp. 133-141
[70] J. Alieu et. al., “Potential of SiGe-Channel MOSFETs for a submicron CMOS technology”, in:
S. Luryi, J. Xu, and A. Zaslavsky (Eds.), Future Trends in Microelectronics (1999 John Wiley
& Sons, Inc), pp. 143-153
[71] S. Takagi, T. Mizuno, N. Sugiyama, T. Tezuka, A. Kurobe, “Strained-Si-on-insulator
(strained-SOI) MOSFETs – Concept, structures and device characteristics”, IEICE Trans.
Electronics E84C (2001) 1043-1050
[72] Ismail, K., Meyerson, B. S., and Wang, P. J. (1991) High electron mobility in modulation-
doped Si/SiGe. Appl. Phys. Lett., 58, 2117–19.
[73] Giles, M.D. et. la.; "Understanding stress enhanced performance in Intel 90nm CMOS
technology," VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on ,
vol., no., pp. 118- 119, 15-17 June 2004
[74] Ghani, T. et. al. "A 90nm high volume manufacturing logic technology featuring novel
45nm gate length strained silicon CMOS transistors," Electron Devices Meeting, 2003.
IEDM '03 Technical Digest. IEEE International , vol., no., pp. 11.6.1- 11.6.3, 8-10 Dec.
2003
[75] Jotwani, R. et. al. , "An x86-64 Core in 32 nm SOI CMOS," Solid-State Circuits, IEEE Journal
of , vol.46, no.1, pp.162-172, Jan. 2011
[76] Feudel, Thomas; Horstmann, Manfred, "Recent advances in stress and activation
engineering for high-performance logic transistors," Advanced Thermal Processing of
Semiconductors, 2008. RTP 2008. 16th IEEE International Conference on , vol., no., pp.1-
34, Sept. 30 2008-Oct. 3 2008
[77] Wu E. Y. et al. (2002) CMOS scaling beyond the 100-nm node with silicon-dioxide-based
gate dielectrics, IBM J. Res. Dev., 46(2/3), 287–298.
[78] S. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, Analysis and Design, TMH
Edition
[79] F. Stern, “Quantum Properties of Surface Space-Charge Layers,” Solid-State Electron., pp.
499–514, 1974, crit. Rev. Solid State Sci.
[80] C. Lallement et. al., “Accounting for Quantum Effects and Polysilicon Depletion From Weak
to Strong Inversion in a Charge-Based Design-Oriented MOSFET Model,” IEEE Trans.
Electron. Devices, vol. 50, no. 2, pp. 406–417, Feb.2003,
[81] M. Bucher et. al. “Accounting for Quantum Effects and Polysilicon Depletion in an
Analytical Design-Oriented MOSFET Model,” in Simulation of Semiconductor Processes and
Devices, C. T. D. Tsoukalas, Ed. Springer, 2001, pp. 296–299
[82] S. Borkar, “Design challenges of technology scaling,” IEEE Micro, vol.19, no.4, P.23-29,
July-Aug. 1999
[83] M. Koh et. al. “Limit of gate oxide thickness scaling in MOSFET due to apparent threshold
voltage fluctuation induced by tunnel leakage current,” IEEE Trans. Electron Devices, vol.
48, pp. 259–264, Feb. 2001
[84] D. A. Antoniadis, “MOSFET scalability limits and “New frontier devices,” in Proc. Symp. VLSI
Technology, 2002, pp. 2–5
[85] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, “Scaling
challenges and device design requirements for high performance sub-50 nm gate length
planar CMOS transistors,” in Proc. Symp. VLSI Technology, 2000, pp. 174–175
[86] M. Chudzik et al., “High-performance high-κ/metal gates for 45 nmCMOS and beyond with
gate-first processing,” in VLSI Symp. Tech. Dig.,2007, pp. 194–195
[87] R. Ranjan et. al., “A New Breakdown Failure Mechanism in HfO2 gate dielectric”, IEEE proc.
IRPS, 2004, pp. 347-352
[88] Y.-C. Yeo, T.-J. King, and C. Hu, “Mosfet gate leakage modeling and selection guide for
alternative gate dielectrics based on leakage considerations,” IEEE Trans. Electron Devices,
vol. 50, no. 4, pp. 1027–1035, Apr. 2003
[89] B. Cheng et. al. “Design considerations of high-K gate dielectrics for sub-0.1-µm
MOSFET’s,” IEEE Trans. Electron Devices, vol. 46, no. 1, pp. 261–262, Jan. 1999
[90] A. Inani et. al. “Gate stack architecture analysis and channel engineering in deep sub-
micron MOSFETs,” Jpn.J. Appl. Phys., vol. 38, no. 4B, pp. 2266–2271, Apr. 1999.
62
[91] D. J. Frank, Y. Taur, and H.-S. P.Wong, “Generalized scale length for two dimensional
effects in MOSFET’s,” IEEE Electron Device Lett., vol. 19, no. 10, pp. 385–387, Oct. 1998
[92] R. Kaur et. al. “Performance investigation of 50 nm insulated shallow extension gate stack
(ISEGaS) MOSFET for mixed mode applications,” IEEE Trans. Electron Devices, vol. 54, no.
2, pp. 365–368, Feb. 2007
[93] B. H. Lee et. al.," Metal electrode/high-k dielectric gate-stack technology for power
management," IEEE Trans. Electron Devices, vol. 55, no. 1, pp. 8-20, January, 2008
[94] Chau, R. et. al., "High-κ/metal-gate stack and its MOSFET characteristics," Electron Device
Letters, IEEE , vol.25, no.6, pp. 408- 410, June 2004
[95] K Roy et. al. “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-
Submicrometer CMOS Circuits”, Proc. Of the IEEE, vol. 91, no. 2, 2003
[96] C. Lallement, M. Bucher, and C. Enz, "Modelling and characterization of non-uniform
substrate doping," Solid-State Electron., vol. 41, pp. 1857-1861, 1997
[97] K. Y. Lim, X. Zhou, "Modeling of Threshold Voltage with Non-uniform Substrate Doping,"
Proc. of the 1998 IEEE International Conference on Semiconductor Electronics (ICSE'98),
Malaysia, 1998, pp. 27-31
[98] P. Ratnam, C. Andre, and T. Salama, "A new approach to the modelling of non-uniformly
doped short channel MOSFET's," IEEE Trans. Electron Devices, vol. 31, pp. 1289-1298,
1984
[99] D. A. Antoniadis, "Calculation of threshold voltage in non-uniformly doped MOSFET's,"
IEEE Trans. Electron Devices, vol. 31, pp. 303-307, 1984
[100] S. Venkatesan et al, “Device drive current degradation observed with retrograde channel
profiles”, Proc. IEDM 1995, pp. 419-422
[101] Sean T. Ma, John R. Brews, “Comparison of Deep-Submicrometer Conventional and
Retrograde n-MOSFET’s”, IEEE TED, Vol. 47, No 8, August 2000, pp. 1573-1579
[102] Indranil De and Carlton M. Osburn, “Impact of Super-Steep-Retrograde Channel Doping
Profiles on the Performance of Scaled Devices”, IEEE TED, Vol. 46, No 8, August 1999, pp.
1711-1717
[103] Y. Taur et. al. “CMOS Scaling into the Nanometer Regime,” Proc. IEEE 85, 486 –504 (1997)
[104] Cheng Y. et. al. (1997b) Modeling of small size MOSFETs with reverse short channel and
narrow width effects for circuit simulations, Solid-State Electron., 41(9), 1227–1231
[105] H.I. Hanafi et. al., A model for anomalous short-channel behavior in submicron MOSFET’s,
IEEE Electron Dev. Lett. 14 (12) (1993) 575–577
[106] J. Tanaka et. al., Reverse short-channel effect of threshold voltage in LOCOS parasitic
MOSFET’s, Solid State Electron 38 (3) (1995) 567–572
[107] S.T. Hsu, I.H. Kalish, K. Suzuki, R. Kawabata, H. Shibayama, Physical mechanism of the
reverse short-channel effect in MOS transistors, Solid State Electron 34 (6) (1991) 605–608
[108] N.D. Arora, M.S. Sharma, Modeling the anomalous threshold voltage behavior of
submicrometer MOSFET’s, IEEE Electron Dev. Lett. 13 (2) (1992) 92–94
[109] M. Nishida and H. Onodera, “An anomalous increase of threshold voltage with shortening
the channel lengths for deeply boron-implanted n-channel MOSFET’s,” IEEE Trans. Electron
Devices, vol. ED-28, p.1101, 1981
[110] Y. Okumura et. al. “A novel source-to-drain nonuniformity doped channel (NUDC) MOSFET
for high-current drivability and threshold voltage controllability,” in IEEE IEDM Tech. Dig.,
1990
[111] T. Hori, “A 0.1-_m CMOS technology with tilt-implanted punchthrough stopper (TIPS),” in
IEEE IEDM Tech. Dig., 1994, p. 75
[112] J. Tanaka et. al., “A sub-0.1-_m grooved gate MOSFET with high immunity to short-channel
effects,” in IEEE IEDM Tech. Dig., 1993, p. 537
[113] T. N. Buti et. al., “Asymmetrical halo source GOLD drain (HS-GOLD) deep-half micron n-
MOSFET design for reliability and performance,” in IEEE IEDM Tech. Dig., 1989, p. 617
[114] C.F. Codella, S. Ogura, Halo doping effects in submicron DI-LDD device design, IEDM
(1985) 230–231
[115] S. Odanaka, A. Hiroki,, Potential design and transport property of 0.1 mm MOSFET with
asymmetric channel profile, IEEE Trans. Electron Dev. 44 (4) (1997) 595–600
[116] B. Cheng et. al., Sub 0.18 mm SOI MOSFETs using lateral symmetric channel profile and
Ge preamorphization salicide technology, Proc. IEEE 18 (1998) 113–114
[117] B. Yu et. al., “Short—Channel effect improved by lateral channel-engineering in deep-
submicrometer MOSFETs,” IEEE Trans. Electron Devices, vol. 44, pp. 627–634, Apr. 1997
[118] T. N. Buti et. al., “Asymmetrical halo source GOLD drain (HS-GOLD) deep half micron n-
MOSFET design for reliability and performance,” in IEDM Tech. Dig., 1989, pp. 617–620
63
[119] K. Narasimhulu, D. K. Sharma and V. R. Rao, “Impact of lateral asymmetric channel doping
on deep submicrometer mixed-signal device and circuit performance,” IEEE Trans. Electron
Devices, vol.50, pp.2481-2489, Dec2003
[120] C. Wann et. al. “Channel profile optimization and device design for low power high –
performance dynamic threshold MOSFET,” in IEDM Tech. Dig., pp. 113-116, 1996
[121] W. Long, H. Ou, J.-M. Kuo, and K. K. Chen, “Dual material gate (DMG) field-effect
transistor,” IEEE Trans. Electron Devices, vol. 46, pp. 865–870, May 1999
[122] Baishya S, Mallik A, Sarkar CK. A subthreshold surface potential model for short-channel
MOSFET taking into account the varying depth of channel depletion layer due to source
and drain junctions, IEEE Trans. Electron Devices 2006;53:507-514
[123] Baishya S, Mallik A, Sarkar CK. A subthreshold surface potential and drain current model
for lateral asymmetric channel(LAC) MOSFETs, IETE Journal of Research 2006; 52:379-390
[124] Baishya S, Mallik A, Sarkar CK. Subthreshold surface potential and drain current models
for short-channel pocket implanted MOSFETs, Microelectronics Engineering
2007;84(4):653-662
[125] Saxena M, Haldar S, Gupta M. Design considerations for novel device architecture: hetero-
material double-gate (HEM-DG) MOSFET with sub-100 nm gate length, Solid- State
Electronics 2004;48(7):1167-1174
[126] Zhou X, Long W. A novel hetero-material gate (HMG) MOSFET for deep-submicron ULSI
technology, IEEE Trans. Electron Devices 1998;45(11):2546-2548
[127] Chaudhry A, Kumar MJ. Investigation of the novel attributes of a fully depleted dual-
material gate SOI MOSFET, IEEE Trans. Electron Devices 2004;51(9):1463-1467
[128] Baishya S, Mallik A, Sarkar CK. A Pseudo Two-Dimensional Subthreshold surface potential
model for Dual-Material Gate MOSFETs, IEEE Trans. Electron Devices 2007;54:2520-2525
[129] Saxena M, Haldar S, Gupta M. Physics-Based Analytical Modeling of Potential and Electrical
Field Distribution in Dual Material Gate (DMG) – MOSFET for Improved Hot Electron Effect
and Carrier Transport Efficiency, IEEE Trans. Electron Devices 2002;49(11):1928-1938
[130] Kumar MJ, Chaudhry A. Two-dimensional analytical modeling of fully depleted SHDMG SOI
MOSFET and evidence for diminished SCEs, IEEE Trans. Electron Devices 2004;51(4):569-
674
[131] Razavi, P.; Orouji, A.A.; , "Nanoscale Triple Material Double Gate (TM-DG) MOSFET for
Improving Short Channel Effects," Advances in Electronics and Micro-electronics, 2008.
ENICS '08. International Conference on , vol., no., pp.11-14, Sept. 29 2008-Oct. 4 2008
[132] K. Goel, M. Saxena, M. Gupta, and R. S. Gupta, “Modeling and simulation of a nanoscale
three-region tri-material gate stack (TRIMGAS) MOSFET for improved carrier transport
efficiency and reduced hotelectron effects,” IEEE Trans. Electron Devices, vol. 53, no. 7,
pp. 1623–1633, Jul. 2006
[133] K. Goel, M. Saxena, M. Gupta, and R. S. Gupta, “Two-dimensional analytical threshold
voltage model for DMG Epi-MOSFET,” IEEE Trans. Electron Devices, vol. 52, no. 1, pp. 23–
29, Jan. 2005
[134] Mei-Li Chen et. al. A New Two-Dimensional Analytical Model for Nanoscale Symmetrical
Tri-Material Gate Stack Double Gate Metal–Oxide–Semiconductor Field Effect Transistors
Jpn. J. Appl. Phys. 48 (2009) 104503
[135] J.P. Colinge: Silicon-on-Insulator Technology: Materials to VLSI (3rd Ed.) (Springer, New
York, 2004)
[136] S. Cristoloveanu, S. Li: Electrical Characterization of Silicon-on-Insulator Materials and
Devices. (Springer, New York, 1995)
[137] J.B. Kuo, Ker-Wei Su: CMOS VLSI Engineering. (Springer, New York,1998)
[138] C. Hu, “Silicon-on-insulator for high speed ultra large scale integration,” Jpn. J. Appl. Phys.,
vol. 33, pp. 365–369, Jan. 1994
[139] R.-H. Yan et al., “Scaling the Si MOSFET: From bulk to SOI to bulk,” IEEE Trans. Electron
Devices, vol. 39, no. 7, pp. 1704–1710, Jul. 1992
[140] T. Sakurai, A. Matsuzawa, T. Douseki: Fully-Depleted SOI CMOS Circuits and Technology
for Ultralow-Power Applications. (Springer, New York,2006)
[141] A. Marshall, S. Natarajan: SOI Design: Analog, Memory and Digital Techniques. (Springer,
New York, 2002)
[142] T. Douseki, S. Shigematsu, J. Yamada, M. Harada, H. Inokawa, T. Tsuchiya: A 0.5-V
MTCMOS/SIMOX logic gate. IEEE Journal of Solid-State Circuits, 32, 1604 (1997)
[143] Z. Xia, Y. Ge, Y. Zhao: A study of varied threshold voltage MOSFET (VTMOS) performance
and principle. Proceedings 22nd International Conference on Microelectronics (MIEL), 1,
159 (2000)
64
[144] V. Ferlet-Cavrois et. al. High frequency characterization of SOI dynamic threshold voltage
MOS (DTMOS) transistors. Proceedings IEEE Intl. SOI Conference, 24 (1999)
[145] A. Yagishita, T. Saito, S. Inumiya, K. Matsuo, Y. Tsunashima, K. Suguro: Dynamic threshold
voltage damascene metal gate MOSFET (DT-DMGMOS) technology for very low voltage
operation of under 0.7 V. IEEE Transactions on Electron Devices 49-3, 422 (2002)
[146] J.P. Colinge, J.T. Park: Application of the EKV model to the DTMOS SOI transistor. Journal
of Semiconductor Technology and Science, 3-4, 223, (2003)
[147] K. Bernstein, N. Rohrer: SOI Circuit Design Concepts. (Springer, New York, 2000)
[148] J. T. Park and J. P. Colinge, “Multiple-gate SOI MOSFETs: Device design guidelines,” IEEE
Trans. Electron Devices, vol. 49, no. 12, pp. 2222–2229, Dec. 2002
[149] Y. Omura, S. Horiguchi, M. Tabe, and K. Kishi, “Quantum-mechanical effects on the
threshold voltage of ultrathin-SOI NMOSFETs,” IEEE Electron Device Lett., vol. 14, no. 12,
pp. 569–571, Dec. 1993
[150] F. Allibert et. al., “From SOI materials to innovative devices”,Solid State Electron. 45 (2001)
559-566
[151] T. Sekigawa and Y. Hayashi: Calculated threshold-voltage characteristics of an XMOS
transistor having an additional bottom gate. Solid-State Electronics 27, 827 (1984)
[152] D.J. Frank, S.E. Laux, M.V. Fischetti: Monte Carlo simulation of a 30 nm dual-gate MOSFET:
how short can Si go? Technical Digest of IEDM, 553 (1992)
[153] F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, “Double-gate silicon-on-
insulator transistor with volume inversion: A new device with greatly enhanced
performance,” IEEE Electron Device Lett., vol. EDL-8, p. 410, 1987
[154] T. Tanaka, K. Suzuki, H. Horie, and T. Sugii, “Ultra fast low-power operation of p -n
double-gate SOI MOSFETs,” in Proc. VLSI Technol. Symp. Tech. Dig., 1994, p. 11
[155] Y. Taur et al., “An analytical solution to a double-gate MOSFET with undoped body,” IEEE
Electron Device Lett., vol. 21, pp. 245–247, July 2000
[156] H. Lu and Y. Taur, “An analytic potential model for symmetric and asymmetric double gate
MOSFETs,” IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1161–1168, May 2006
[157] B. Yu, W.-Y. Lu, H. Lu, and Y. Taur, “Analytic charge model for surrounding-gate MOSFETs,”
IEEE Trans. Electron Devices, vol. 54, no. 3, pp. 492–496, Mar. 2007
[158] H.-S. P. Wong, D. J. Frank, and P. M. Solomon, “Device design considerations for double-
gate, ground-plane, and single-gated ultra-thin SOI MOSFET’s at the 25 nm channel length
generation,” in IEDM Tech. Dig., 1998, pp. 407–410
[159] X. Lin, C. Feng, S. Zhang, W. H. Ho, and M. Chan, “Double-gate SOI MOSFET fabrication
from bulk silicon wafer,” in Proc. IEEE Int. SOI Conf., 2001, pp. 93–94
[160] S. Venkatesan, G.W. Neudeck, R.F. Pierret, Dual gate operation and volume inversion in n-
channel SOI MOSFET’s, IEEE Electron Dev. Lett. 13 (1) (1992) 44–46
[161] K. Suzuki, Y. Tosaka, T. Tanaka, H. Horie, Y. Arimoto, Scaling theory of double-gate SOI
MOSFET’s, IEEE Trans. Electron Dev. 40, (12) (1993) 2326–2329
[162] D. Hisamoto et al. "FinFET: A self-aligned double-gate MOSFET scalable to 20 nm," IEEE
Trans. Electron Devices, vol. 47, no. 12, pp. 2320-5, Dec. 2000
[163] B. Yu et al. "FinFET scaling to 10 nmgate length," in Proc. International Electron Devices
Meeting (IEDM), pp. 251-4, 8-11 Dec. 2002
[164] F.L. Yang et al. "25 nm CMOS Omega FETs," in Proc. International Electron Devices
Meeting (IEDM), pp. 255-8, 2002
[165] D. Hisamoto. "FD/DG-SOI MOSFET: A viable approach to overcoming the device scaling
limit," in Proc. International Electron Devices Meeting (IEDM), pp. 19.3.1-19.3.4, 2-5 Dec.
2001
[166] Y.K. Choi, T.J. King, and C. Hu. "Nanoscale CMOS spacer FinFET for the terabit era," IEEE
Electron Device Lett., vol. 23, no. 1, pp. 25-27, Jan. 2002
[167] J. Kedzierski et al. "Extension and source/drain design for high performance FinFET
devices," IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 952-8, Apr. 2003
[168] E. Nowak et al. "Scaling beyond the 65 nm node with FinFET-DGCMOS," in Proc. Custom
Integrated Circuits Conference (CICC), pp. 339-42, 21-24 Sept. 2003
[169] A. Dixit et al. "Minimization of the MuGFET contact resistance by integration of NiSi
contacts on epitaxially raised source/drain regions," in Proc. European Solid State Device
Research Conference (ESSDERC), pp. 445-8, 12-16 Sept. 2005
[170] A. Dixit et. al. "Analysis of the parasitic S/D resistance in multiple-gate FETs," IEEE Trans.
Electron Devices, vol. 52, no. 6, pp. 1132-40, Jun. 2005
[171] Xuejue Huang et. al.; , "Sub-50 nm P-channel FinFET," Electron Devices, IEEE Transactions
on , vol.48, no.5, pp.880-886, May 2001
65
[172] Yi Cui et. al., High Performance Silicon Nanowire Field Effect Transistors, Nano Letters
2003 3 (2), 149-152
[173] S. Miyano, M. Hirose, F. Masuoka: Numerical analysis of a cylindrical thinpillar transistor
(CYNTHIA). IEEE Transactions on Electron Devices 39-8, 1876 (1992)
[174] A. Nitayama et. al.: Multi-pillar surrounding gate transistor (M-SGT) for compact and high-
speed circuits. IEEE Transactions on Electron Devices 38-3, 579 (1991)
[175] N. Singh et. al.: Highperformance fully depleted silicon nanowire (diameter<5 nm) gate-
allaround CMOS devices", IEEE Electron Device Letters 27-5, 383 (2006)
[176] N. Singh et. al.: Ultra-narrow silicon nanowire gate-allaround CMOS device: impact of
diameter, channel-orientation and low temperature on device performance. Technical
Digest of IEDM, paper 20.4 (2006)
[177] Y. Cui, Z. Zhong, D. Wang, W. U. Wang, and C. M. Lieber, “High performance silicon
nanowire field effect transistors,” Nano Lett., vol. 3, pp. 149–152, 2003
pp.1021-1024, Nov. 2007
66

SCE 100nm

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

SCE 100nm

Uploaded by

Copyright:

Available Formats

Angsuman Sarkar Short-Channel Effects in sub-100nm MOSFETs: A Review

SHORT-CHANNEL EFFECTS (SCEs)

2.1 Introduction to scaling and Moore’s law

Integrated-circuits (IC) technology has undergone through unmatched technological and

geometry, insight to device physics as well as performance of a single MOS transistor

2.1.1 Benefits of scaling

Increased device packing density

2.1.2 Types of scaling

Two types of scaling are common:

2.1.2.1 Constant Field Scaling

Figure 2.1: Illustration of the principles of constant electric field scaling by

2.1.2.2 Constant Voltage Scaling

2.2 ITRS roadmap for semiconductors

Table 2.1: Excerpt of 2009 ITRS technology scaling

2.3 MOSFET models

2.4 Gate oxide scaling

2.4.1 Problems with ultra-thin gate oxides

Gate oxide scaling is not limited by manufacturing control. It is feasible to manufacture

2.4.2 Gate tunnel currents

2.4.3 Diminishing Returns from gate oxide scaling

2.5 Gate length scaling and Short-Channel Effects

2.5.1 Reduction of effective threshold voltage

Figure 2.4: Effective threshold voltage as a function of Vds taking L as parameter

2.5.2 DIBL (Drain Induced Barrier Lowering)

Figure 2.5: the DIBL effect

Figure 2.6: Effect of DIBL on current characteristics

2.5.3 Hot Carrier effects

2.5.4 Avalanche breakdown and parasitic bipolar action

2.5.5 Mobility Degradation

There are two reasons for mobility reduction in MOSFET

Where µ0 is the mobility at threshold voltage and θ is the mobility reduction

2.5.5.2 Horizontal electric field Mobility Degradation

2.5.6 Velocity Saturation

Figure 2.10: Electric field versus Carrier velocity in a solid

2.5.7 Channel Length Modulation and punch-through

widths. The channel-length-modulation (CLM) effect typically increases in the small

2.5.8 Output impedance variation with drain-source voltage

Figure 2.11: variation of output impedance r0 as a function of Vds

In short-channel devices, as Vds increases further, the DIBL become significant

2.5.9 Parameter fluctuation

A concomitant problem associated with device miniaturization is parameter fluctuation.

2.5.10 Source/drain resistances and parasitic capacitances

As the device is scaled down to ultra-submicron dimensions, the source/drain

Lmin = 5lT ∝ ( X jtOX X D2 )

2.5.11 Subthreshold Conduction

Figure 2.12: Energy band diagram of MOSFET in weak inversion

The subthreshold current is diffusion current. By definition the subthreshold

2.6 Bulk CMOS Design Solutions for Subthreshold Leakage

2.6.1 Polysilicon Gate stack

formation, elimination of parasitic bipolar action, and inherent physical scalability to

2.6.2 Source-Drain Structures

2.7 Introduction to SiGe or Strained Si MOSFET for

compressive strain for pMOS devices in 90 nm and 65 nm high-performance single and

2.8 Introduction to Novel MOSFET structures

2.9 High-K gate Materials

2.10 Channel Engineering and Gate engineering

In addition to gate oxide thickness scaling, another technique to improve short-channel

2.10.1 Reverse short-channel effect (RSCE) & HALO doping

To reduce the DIBL effect in a short-channel MOSFET, the substrate doping

Figure 2.17: Reverse short channel Effect

The so-called Reverse Short-Channel Effect (RSCE) [105-108] was originally

Figure 2.18: a) n-channel MOSFET with HALO structure b) Threshold voltage

2.10.2 Gate Engineering Technology