LAB REPORT FORMAT

The report must be neatly typed by any work processing methodology. The first page of
the report is the Title Sheet. A typical format of the report shall contain:

1) Objective: Briefly state the purpose of the experiment. What does the experiment
intend to prove?
2) Equipment and Parts: List all instruments used in the experiment and record all
the integrated circuits needed to perform the experiment.
3) Circuit Diagrams: Draw all logic circuits electronically. Professional circuits with
Logic Work, Electronics Workbench, or any other equivalent software must be
drawn and simulated.
4) Data: Tabulate neatly your data from the original data sheet (see#7).
5) Calculations: Answer all questions, show all calculations and simplifications used
to obtain the results outlined in your objectives.
6) Conclusions: Discuss your results and highlight any differences with the theory (if
any). Discuss all the reasons behind those differences.
7) Data Sheet: The sheet must show the original data taken in the lab. This sheet
must be reviewed and signed by your instructor before you leave the lab.

NOTE: Every student shall prepare his/her own lab report. The lab report is due on the
following week. Late reports shall be marked down.
ALSO:
Proper pre-lab preparation is essential in this laboratory course. Review the data sheet for
the devices specified and/or review an online tutorial for the circuits
 Experiment One
Introduction to Number Systems

Before attending the lab section, simulate the circuits involved in this experiment using
LogicWorks or equivalent software packages. Provide a copy of the simulation run and
the circuits diagrams to the lab instructor, at the beginning of each meeting.

Part list/Equipment/Software

7493
7447
Seven-segment LED( comm.anode)
Trainer board
LEDs

Objective:
In this experiment you will learn to use light emitting diodes (LED), and seven-segment
LEDs to display binary and decimal numbers.
PART 1, LEDs:
In this section, you will learn to properly utilize a light emitting diode (LED) to display
binary numbers. The symbol for the LED is shown in figure 1. The positive terminal of
the LED is referred to as the anode and negative terminal is called the cathode.

+ Resistor
-

Cathode
+ VR -
+ Vled -

To turn on the LED, anode side should be connected to a higher potential than the
cathode side. TO avoid damage to the LED, the current through the LED should not
exceed the proper tolerances. For this reason, a resistor should be connected in series with
the LED.

To calculate the value of R, utilize Ohms laws: V (led) = IR. A typical value of 1, the safe
current through the LED, is 10mA. V (led) when forward biased is 1.7 Volts. So V(R) is
5-1.7= 3.3 volts. Hence, 3.3 volts= 10mA*R. The calculated value of R is 330 ohms. If
another source voltage, current or bias values have been specified, the resistance can be
recalculated.
There are two types of seven segment displays, common anode and common cathode. As
the name implies, the common cathode display has seven or more LEDs internally that
are connected together at the cathode terminal. Each segment’s LED is turned on by
applying a logic1 to the corresponding segment pin. The common cathode pin must be
connected to the ground. Note that one should connect a current limiting resistor to the
anode terminal of each LED. This is shown below.

The common anode display, Internally, has seven or more LED.s that are connected
together at the anode terminal. Each segment’s LED is turned on by applying a logic 0 to
the corresponding segment pin. The common anode pin must be connected to the 5 volts
supply. Note that you should connect a current limiting resistor to the cathode terminal of
each LED.

Procedure:
Verify the operation of different LEDs:
1) In your individual lab package.
 2) On the trainer board.
3) In the seven segment display in your lab package (determine if it is common
anode or common cathode).

Part 2:
In this section, you will connect the outputs of a counter chip (IC 7493) to different types
of LEDs to display the count sequence of the counter in both binary( using LEDs), and
decimal. To display the count sequence in decimal, you use a seven segment decoder chip
(7447).

Procedure:
Connect the output pins of the 7493 counter chip to LEDs on the trainer board.
Connected the power to the chip( +5 to Vcc and ground to GND pins). Connect the clock
input to the counter chip to the trainer’s clock terminal. Select 1 Hz clock source and
observe and observe the binary count sequence on the LEDs . The block diagram of the
connection is shown below.
You must use the TTL data book and convert the block diagram into a circuit diagram,
clearly labeling the connections (pin numbers, pin function, etc.). Look up the function
table ( or timing diagram) of the chip(s) that are used in the circuit, and make sure that
every connection is make a required in the function table. For Example, the 7493 counter
can function as a three-bit of as a four-bit counter. To have the chip function as a 4 bit
counter (to count values 0, 1, 2…9, 0) you must connect pin 12 to pin1. You ought to
develop the ability to understand the information provided in the data books.

Next, connect the decoder (7447) chip to the 7-segment decoder and the counter chip as
shown. The decoder chip converts the binary number sequence to the 7- segment display
format, hence output of the counter can be observed in decimal digits.
The circuit diagram for the 7-segment display is not provided in the TTL manual. The
following table lists the function of each pin of a typical 7-segment package. Verify that
this pin-out is correct, and if not correct, determine it (internally followed up by
verification).

PIN NO SEGMENT
1 A
2 F
3 CA
4,5 NP
6 NC
7 e
8 D
9 DP
10 C

11 G
12 NP
13 B
14 CA

NP= No pin, DP=decimal point, CA=common anode.

Connect the power to the circuit and observe the count sequence. Note that after digit 9,
the 7-segment display shows some invalid characters (10-15), copy them down.
The counter chip can be modified to count differently, depending on how its reset pins,
R1 and R2 are set. For example, set R1 and R2 pins to 9 and 11 pins ( of the counter)
respectively. This modifies the counter to count in binary coded decimal (BCD)—
sequence 0, 1, 2, .. 9, 0. The function of the reset pins R1 and R2 is to reset the counter
after the specified outputs of the counter become one. Notice the order of the counter
output pins which reset the counter.

Similar to the above ex. Modify the counter chip to count the sequence:
0-5
0-7, and
0-10.
In Order to accomplish this, connect the reset pins of the counter to the output pins 12,
9,8,11, in the specified combination of the output counter. If you are not sure, try a few
combinations!

Lab report:
Provide a lab report including the detailed circuit diagram for each stage of the
experiment; your lab report must have the format specified by your lab instructor.
 Experiment two
Digital Logic Gates.

Before attending the lab section, simulate the circuits involved in this experiment using
Logic-Works or equivalent software. Provide a copy of the simulation run and the circuits
diagrams to the lab instructor, at the beginning of each meeting.

Part list/Equipment/Software
7402
7408
7432
7404
7486
Trainer board
Dual channel oscilloscope

Objective:
To investigate the behavior of 6 IC gates and observe their input/output waveforms on the
oscilloscope.

Part1, Gate Verification:

In this section, you will verify the truth tables of 6 types of logic gates as; AND, OR,
NOT, NAND, NOR, EX-OR gates.

Procedure:
Connect the power and ground to the chips containing each type of logic gates shown
below, one chip at a time in the order given below. Make connection from the logic
switches on the trainer board to the input(s) of a logic gate in the chip under experiment
(always refer to TTL data book for pin configuration). Use the truth table for the logic
gate and set the input logic switches according to the values in the truth table. Observe
the output of the gate for each input combination on a LED. Verify that each of the 6
logic gates functions according to its truth table.
Part2, Timing diagram:
In this section, observe the input/output waveform relationships on an oscilloscope for
each of the 6 gates from the chips tested in part 1. Record the timing diagram for each
gate.

Procedure:
In this part instead of using the switches on the trainer board as the inputs to each gate,
use the first two outputs (2 least significant bits) of the 7493 counter chip- configure 7493
as you did in lab on. Record the input/output waveform (timing diag) for each of the 6
logic gates.

Part3, NAND gate as Universal gate:

In this section, you will connect a 7400 ICs (four 2-input NAND gates) to produce a 2
input AND gate, a 2-input OR gate, a 2-input NOR gate, an inverter, and a 2-input EX-
OR gate.

Procedure:
Using 2-input NAND gates only, construct a circuit to function as each gates listed above
(2-input AND gate, 2-input OR gate, etc.). Verify the operation of each of the NAND
implementation circuits (equivalent NAND circuits) with the truth table of each specified
gate. Record your circuit diagrams and the truth tables.
Part4, Propagation Delay of logic gates:
In this section, you will calculate the propagation delay of an inverter IC. Use the TTL
Data book values to compare the measured value using an oscilloscope, to the one
obtained from the Data book.

Procedure:
Connect 6- invertors in series as shown. The output will be the same as the input, just
delayed by the 6 invertors. Connect the clock source on the trainer to the input pin of the
first inverter. Setup the scope to function in the dual trace mode. Display the input clock
signals on channel one, and connect the probe for the second channel to the output of the
sixth inverter. Use the proper setting on the oscilloscope to measure the delay time
between the input and output signals (remember that you are measuring nanoseconds!).
The measured time is the propagation delay due to 6 gates. Compute the propagation
delay of the gate and compare the value to the propagation delay obtained from the TTL
databook.

Lab report:
In your lab report provide all circuit diagrams, timing diagrams, truth tables, etc,
obtained/used in each step.
 Experiment 3
Boolean algebra

Before attending the lab section, simulate the circuits involved in this experiment using
Logic-Works or equivalent software packages. Provide a copy of the simulation run and
the circuits diagrams to the lab instructor, at the beginning of each meeting.

Part list/Equipment/Software:
7408
7432
7404
7486
Trainer board
Objective:
To utilize digital logic gates to verify Boolean algebra expressions.

Part1:
Any Boolean expression can be verified using a digital logic circuit or a truth table. For
example, the simplification theorem XY+X=X can be verified by connecting the circuits
shown below.

This will implement both sides of the equation with a digital logic circuit composed of
AND/OR/NOT gates. Once the circuits are connected, they are verified by checking the
equivalence of the truth tables.

Procedure:
For the following Boolean algebra theorems, implement both sides of the equation and
verify by checking the truth tables.
1) X+0=X
2) X.1+X
3) X+X ' =1
4) X.X ' = 0
5) X(Y+Z)=(XY)+(XZ)
 6) X+YZ=(X+Y)(X+Z)

Part2:
Any Boolean expression can be implemented with AND/OR/NOT gates. In this section,
you will implement the simplified and unsimplified versions of the same function using
digital logic gates and compare the results.

Procedure:
Implement the following Boolean expression using 7408(AND gates), 7432(OR gates),
and (NOT gates) ICs without simplifying the expression. Obtain the corresponding truth
table. Next, simplify the expression and implement with gates and compare the 2 results
of the number components utilized in the circuits.

f( X, Y, Z)= ∑m( 1, 2, 4, 7)

Part3:
The EX-OR gate, IC 7486, can be utilized to implement certain Boolean functions. This
is done by grouping the literals into the EX-OR’s form: A' B+ B' A.
Implement the function given in part2, using 2 EX-OR’s gates only(manipulate the
expression into EX-OR form).

Lab report:
For the report include every algebraic manipulations, truth tables, logic diagrams (with
pin numbers clearly labeled on it) required/used in each step.
 Experiment Four
Application of Boolean algebra

Before attending the lab section, simulate the circuits involved in this experiment using
Logic-Works or equivalent software packages. Provide a copy of the simulation run and
the circuits diagrams to the lab instructor, at the beginning of each meeting.

Objective:
Digital logic problems can be stated as English sentences first. Each sentence can be
broken into phrases that can be associated with different Boolean Variables. A “phrase”
will be able to have values of ‘true’ and ‘false’. Once the sentences phrases have
variables associated with them, then sentence can be algebraically specified and then
implemented as a digital circuit. For example, consider the sentence: The recently eaten,
or if it is after midnight.

It can be broken down into phrases and associated with the following variables.
F=1 if the cat runs up the tree, 0 otherwise
X=1if the dog is chasing the cat, 0 otherwise
Z=1 if is after midnight, 0 otherwise
Y=1 if it has recently eaten, 0 otherwise.
The Boolean expression associated with this problem is:
F(X, Y, Z) =XY+Z
Which can be implemented with digital gates in a number of ways

Procedure:
Implement the following using 3 different circuits:

A bank vault has 3 locks, each with a different key. Each key is owned by a different
person. To open the door, at least 2 of the 3 people must put their key into the assigned
locks. X, Y and Z are equal to one if there is a key inserted into locks 1,2,3 respectively.

For your circuit, you could consider:

A. POS and SOP versions
B. Simplified and unsimplified versions
C. NAND/NOR conversions.

Lab report:
In your lab report, compare your circuits in terms of wiring, chips, complexity,
debugging, etc.
 Experiment five
Karnaugh Maps and Boolean Simplification

Before attending the lab section, simulate the circuits involved in this experiment using
Logic-Works or equivalent software packages. Provide a copy of the simulation run and
the circuits diagrams to the lab instructor, at the beginning of each meeting.

Part list/Equipment/Software
7410(3- Input NAND)
7400(NAND)
7404(NOT)

Objective:
In this experiment, the relationship between Karnaugh map simplification and digital
logic diagrams will be illustrated. Expressions derived from Karnaugh Maps can be in
Sum-of-Products (SOP) form-grouping ones, or Product-of-Sums (POS) form- grouping
zeroes. In addition, conversion of SOP and POS forms to NAND gates will be explored.
In this section, you will start with a given logic diagram( see fig1). You will utilize the
simplification procedure of K-map to reduce the number of gates and possibly chips.

Part1:
The logic circuit of Fig1, requires one 7410 chip and two 7400 chips. Note that the 7400
IC can be used as an inverter for the complemented versions of A, B, C. If you used the
7404(inverter) you would have needed an additional chip [not to mention the additional
wire]. Simplify the function by Karnaugh Map method. Then, wire and verify both the
simplified and unsimplified versions of the circuit by connecting the outputs to LEDs and
checking the outputs with the truth table. The outputs should be the same as each other
and the truth table.
Part 2, Boolean Functions:
Given
f( A,B,C,D)= ∑m(1,3,5,8,11,12)
g( A,B,C,D)= ∑m(8,9,10,11,12,14,15)

Simplify the functions F and G in SOP form with K-Maps. Next,, wire the combined
logic diagram with the 4 inputs: A,B,C,D; and the outputs F and G. Implement the logic
diagram with minimum number of NAND chips[refer to NAND conversion rules]. Don’t
duplicate the same product term gate if it is in two functions. Construct the composite
circuit. (F and G together) and verify the operation by verifying the LEDs to the truth
table minterms.

Part3, Complements and SOP/POS:

Plot the following in a K-map:

Combine the ones in the map together to obtain the function in SOP form. Plot the zeroes
in the map to obtain the simplified function F´(Complement of F) also in SOP form.
Implement both F and F´ (use NAND gates.). Show the two functions are complements(
the ones are zeroes and zeroes are ones) on both the LED’s and the truth tables.
Conversion from SOP/POS form to NAND gate representation:
Basically, the rules for changing SOP and POS to NAND gates are:
1) Simplify the function in SOP[POS ] form. The function, not including the
complemented inputs, will consist of 2 levels: AND gates for product terms and
an OR gate to OR all the product terms (for POS=ORS for the sum terms, and n
AND gate to multiply these sum terms).
2) Draw a NAND gate for each product term ( anded term).
3) Draw an invert OR (alternate version of NAND for each OR gate.
4) If the literal does not go through two levels, check the bubbles and invert.
5) For POS form, invert the inputs and invert the outputs with NANDS.

You should always check and verify your circuit with Boolean algebra to ensure that the
circuit is verified. You may need to adjust with inverters to obtain the correct function.

Lab report:
For your report, whenever possible, comment on your proposed design (do you use least
literals, least terms, least wiring, what are the advantages?. Complete document, the
design procedure (provide truth table, Boolean expressions, etc)
 Experiment six
Quine-McCluskey Method

Before attending the lab section, simulate the circuits involved in this experiment using
Logic-Works or equivalent software packages. Provide a copy of the simulation run and
the circuits diagrams to the lab instructor, at the beginning of each meeting.

Part list/Equipment/Software

7400(NAND)
7404(NOT)
7411(AND)
7432(OR)
Trainer kit
Logic works

Objective:
In this experiment, you will utilize the Quine-McCluskey method to simplify 2 functions.
You are required to implement the functions with NAND gates.

Part1:
Utilize the Quine-McCluskey method to simplify the following function:
F(a,b,c,d)=∑m(0,1,5,6,8,9,11,13)+d(7,10,15)

This function when simplified should have three two variable terms and one three
variable term (or better). You should check your implementation with K-map before
designing your circuit. The reduced function will be implemented with either NAND gate
(or AND/OR/NOT). Document the steps completely.

Part2:
Using the Quine-McCluskey method, design a four input circuit ( a circuit that indicates
when the inputs consists of a majority of ones). Obtain a logical expression, then
implement that function using NAND gates (or AND/OR/NOT)

Lab report:
In your lab report the steps involved in part one, two, and three.
 Experiment Seven
Decoder Implementation of Boolean functions

Before attending the lab section, simulate the circuits involved in this experiment using
Logic-Works or equivalent software packages. Provide a copy of the simulation run and
the circuits diagrams to the lab instructor, at the beginning of each meeting.

Part list/Equipment/Software
74193(2 x 4 decoder)
74155(dual 2 x 4 decoder)
7400(NAND)
Trainer kit
Logic Works

Objective:
In this experiment, you will implement four circuits, with a decoder or NAND

Part1:
Using two 2 x 4 active-low decoders and some appropriate logic gates, implement a
combinational circuit that conveys 4-bit Gray codes to 8421 code, give a complete circuit
diagram.

Part2:
Design a combinational circuit that has four inputs (ABCD) and one output (Z). The
output equals one when the Gray coded number represented by ABCD is less than five.
Reduce the function using SOP or POS forms and then partially factor if possible. Utilize
a decoder to realize this function.

Part3:
Three chairs are placed in a row. Each chair may be occupied (1) or may not be occupied
(0). Implement the logic function F (A, B, C) which is one only when there are no
adjacent empty chairs. Design the circuit using NAND gates, but do not construct the
circuit. Next, redesign and construct the circuit with two 2 x 4 decoders--use 74155 dual
2/4 decoder chip. In the circuit diagram show how to cascade the 2x4 decoder to obtain a
3x8 decoder.

Part3: Cascading decoders

Implement the following function by cascading four 3x8 decoders. Construct the function
using Logic-Works software. Provide a circuit diagram.
 f( A, B, C, D, E)=∑ m(0,1,4,9,15,31)

Lab report:
Include the truth tables, K-maps, etc and circuit diagrams for part one, two and three.
 Experiment 8
Multiplexers

Before attending the lab section, simulate the circuits involved in this experiment using
Logic-Works or equivalent software packages. Provide a copy of the simulation run and
the circuits diagrams to the lab instructor, at the beginning of each meeting.

Part list/Equipment/Software
74151 IC ( MUX)
74125 (Tri-state)
74126 (Tri-stat)
74139 (Decoder)
Trainer kit
Logic works

Objective:
In this experiment you will implement two logic functions using a multiplexer (MUX).
Also you built MUX's using logic gates.

Part1: Implementing logic functions using MUX's:

Realize the following functions with a 74151 multiplier

f (A, B, C, D)= Π M(0,1,2,5,6,7,8,9,13,15)

Part2:
Using a decoder and a mulitplexer only, design a combinational logic circuit that receives
a 3-bit gray code from an absolute mechanical shaft encoder, and produces a logic'1' as
output whenever the shaft is in the position indicated by 3 switches SW1, SW2, SW3. For
example if the switches are set to input 011 to the circuit, the output has to be logic '1'
whenever the shaft is in position 3 (135°<a<180°). Show the complete circuit diagram for
the circuit. The table for the shaft encoder is given below.
 SHAFT POSITION SHAFT ANGLE
0 0°< a < 45°
1 45°< a < 90°
2 90° < a < 135°
3 135° < a < 180°
4 180° < a < 225°
5 225° < a < 270°
6 270° < a < 315°
7 315° < a < 360°

Part 3:
a) Use the 74125 active high Tri- State buffer and an inverter gate to construct a 2x1
multiplexer. Provide the circuit diagram. Repeat using 74126 active low Tri-State
buffers.
b) Use a 74139 decoder an a 74126, active low Tri-State buffer to construct a 4x1
multiplexer. Provide the circuit diagram.
 Experiment nine
Adders/Subtractors and Magnitude Comparators

Before attending the lab section, simulate the circuits involved in this experiment using
Logic-Works or equivalent software packages. Provide a copy of the simulation run and
the circuits diagrams to the lab instructor, at the beginning of each meeting.

Part list/Equipment/Software
7485 IC (comparator)
741S86 IC (EX-OR)
74LS04 IC (NOT)
74LS08 IC (AND)
Trainer kit
Logic works

Objective:
In this experiment, you will construct a full adder and a full subtractor circuit. Also you
will utilize a magnitude comparator IC and built an equality detector circuit.

Part 1:
Design a full adder circuit that adds three bits. A, B, Cin (carry in) to give the outputs, Co
(carry out) and S (sum). Implement the circuit using appropriate logic gates.
Next, use four full adders and construct a 4-bit BCD adder. Use logic Works software,
construct the circuit and confirm that the circuit functions properly.

Part 2: Adder/Subtractor Logic

Design a fully combinational adder/subtractor that can be cascaded to form a multi-bit
circuit. The inputs are data inputs A, B, carry- in CI, and borrow in BI. The outputs are
data output F, carry-out CO, and borrow from left BL. A mode input M=0 indicates
addition and M=I indicates subtraction. Can the carry and borrow inputs and outputs be
combined. Simulate the circuit using the Logic Works software package.

Part 3: application of adders.

Using four full adders functional logic , design a circuit that receives as input excess-
three codes and it converts the number to a BCD number at its outputs. Construct and test
the circuit using Logic Works software.

Part4: Comparators
1. The 7485 IC will compare two four-bit numbers A (A3 A2 A1 A0) and B (B3 B2
B1 B0) and indicates whether A equals B, A is greater than B, or A is less than B.
Investigate what happens when pins 2,3,4 float, that is they are not connected to
anything. Investigate the function of this chip by using two two-bit binary
numbers W (w1 w0) and X (x1 x0). Start by obtaining a truth table consisting of
 every possible combination of W and Z. Use four logic switches on the trainer
board as input to the comparator. Input the values in the table and observe the
outputs on LED’s. Does the chip function according to the truth table?
2. Design a 4-bit equality detector that has eight input lines and one output line. The
circuit receives as input two 4-bit binary numbers, and it outputs a logic one
whenever the 2 numbers are (equal bit by bit). Implement the circuit with EX-
NOR (EX-OR and NOT) and AND gate(s) only.
 Experiment 10
Design of hazard-free combinational logic circuits

Part list/Equipment/Software
Logic Works software

Objective:
In the first part of this experiment you will design a hazard-free logic circuit. In the
second part, you will examine a multilevel logic circuit for static one and static zero
hazards. If hazards are detected, you are asked to modify the circuit to a hazard-free
network.

Part 1: hazards in two level logic circuits.

Using the K-map method, obtain a minimum sum of products for the following logic
function. Next, from the K-map determine the input conditions, if any, for which the
circuit will produce static 1- or 0 hazards. Using logic works software tool, implement the
circuit, run a simulation, and confirm the predicted hazardous conditions. Obtain a timing
diagram and identify the glitches in the diagram.
IF in the above steps it was determined that hazards exist, modify the circuit to a hazard-
free network. Run a Logic Works simulation to verify that the new circuit is free of static
hazards (Glitches).

f( a, b, c, d)= ∑m( 0,2,6,7,8,10,13)

Part 2: hazards in multilevel logic circuits

Determine all of the static 1-, and 0-hazards in the following multilevel logic circuit.
Remember that you must first obtain the transient output function, from the given
expression. Run a Logic- Works simulation identifying the glitches in the timing
diagram. Redesign the circuit to a hazard –free network.

Lab report:
Include documentation for the steps involved; K-maps, circuit diagram, simulation
printout, etc.
 Experiment eleven
Design of combinational logic circuits using PLAs

Part list/Equipment/Software
GAL16V8 (of GAL22V10)
Seven segment LED
CUPL
Allpro PLA programmer
Allpro software

Objective:
In this experiment you will design a hexadecimal- to- seven-segment LED display
decoder using a GAL16V8 (or GAL22V10) integrated circuit.

Procedure:
Design a combinational logic circuit that receives a 4-bit binary number as input, and it
generates seven outputs to drive a common anode seven segment display LED. Note: the
decoder; for hex numbers A,B,C,D,E, and F will have to produce signals that cause the
LED to display a, b, c, d, e, f.

1) Obtain a truth table

2) Write a CUPL program to implement the truth table. Use the Table statement to
declare the table to the compiler. Do not derive the equations from K-maps.
3) Compile the program and obtain Documentation and a JEDC file. Inspect the
equations produced by CUPL in the documentation file.
4) Use the JEDC file and program a GAL16V8 (or GAL22V10).
5) Connect the programmed PLA chip to a seven segment LED (do not forget to use
current limiting resistors).
6) Use logic switches on the trainer board and try numbers 0-F. Demonstrate the circuit to
the instructor.

Lab report:
In the lab report the truth table, a printed copy of the source file (.PLD), the
documentation file (.DOC) and the JEDC file. Provide the circuit diagram.
 Experiment twelve
Design of an ALU with PLDs

Part list/Equipment/Software
GAL22V10
Allpro programmer
Allpro software
trainer kit
CUPL compiler
Logic Works software

Objective:
In this experiment you will implement a 4-bit Arithmetic logic unit (ALU) for binary and
BCD operations, using a GAL22V10 IC and additional logic devices.

Specifications:
Design a 4-bit ALU with two input ports A (A3 A2 A1 A0) and B(B3 B2 B1 B0) for the
two 4-bit numbers. The device has seven output lines; four lines for the output function,
one line (C) as the carry out line (the value of carry must be zero for any logical
operation), one line (z) to show if all the four function output lines are low, and finally
line (I) to show if any of the 4-bit input number is an invalid BCD(if the operation is a
BCD arithmetic operation). For any non-BCD operation the T input line show is at logic
zero. The block diagram of the ALU and function is shown below.
 S2 S1 S0 Function
0 0 0 A
0 0 1 B
0 1 0 A’( NOT A)
0 1 1 A+B( OR operation)
1 0 0 (A.B) (AND op)
1 0 1 (A.B)’(NAND op)
1 1 0 A plus B (binary op)
1 1 1 A plus B( BCD addition)

Part1: PLA implementation

Can the above circuit be constructed with a single GAL22V10 IC? If yes, program a
GAL22V10 to function as shown above. Test the chip and demonstrate the function of
the circuit to the instructor.
If you determined that the entire circuit can not be implemented in a GAL22V10, use this
chip along with any necessary external IC(s)( chips provided in a lab kit.) to construct the
circuit. Demonstrate the function of the circuit to the lab instructor.

Part 2: Implementation using a ROM

Implement the ALU using ROM.
1) Obtain a ROM table.
2) Obtain a block diagram clearly labeling the connections to the address and data lines.
3) Simulate the circuit using Logic Works software package.

Lab report:
Provide documentation for the design procedure; CUPL source, documentation and
JEDC files. IF a single GAL22V10 can not be used to design the circuit, provide your
reasons in a concise discussion. For part two, provide Logic Works schematic and
simulation output.
 Experiment 13
Design of Priority Multiplexer using PLDs

Part list/Equipment/Software
GAL22V10
Allpro programmer
Allpro programmer software
CUPL compiler
Trainer kit

Objective:
In this experiment you will design a Priority Multiplexer using GAL22V10 and some
external circuitry if necessary.

Introduction:
The block diagram for a priority MUX is shown below. This device can be used to
connect the output lines (DA1- DA2- DB1, DC!, DD1-DD2) of the four devices A, B, C,
D to the system output lines( OT1-OT2) according to the following priority scheme.

RGC
RGB

DC1

DC2
DB1

DB2

RC
RB

DEVICE
D
DEVICE
A
 Device Priority
A Highest
B 2nd
C 3rd
D Lowest

Associated with each device is a request line.(RA,RB,RC,RD). A device can request to

be connected to the system output lines by asserting its request line. Four lines ( RGA,
RGB, RGC,RGD) are used by the priority multiplexer to signal devices that their requests
are granted or not. These signals should be activated only if a request has been received
from the devices and the device output lines have been connected to the system outputs.
The Priority multiplexer should also have a output valid signal to indicate whether the
system output is valid or not. If the output is valid, the Valid output should be asserted to
logic one, otherwise it should be set to logic zero.
The partial function table for this circuit is shown below.

RA RB RC RD OT1 OT2 RGA RGB RGC RGD VALID

0 0 0 0 X X 0 0 0 0 0
0 0 0 1 DD1 DD2 0 0 0 1 1
0 0 1 0 DC1 DC2 0 0 1 0 1
0 0 1 1 DC1 DC2 0 0 1 0 1
.
.
1 1 1 0 DA1 Da2 1 0 0 0 1
.

1 1 1 1 DA1 DA1 1 0 0 0 1

Procedure:
Implement the Priority Multiplexer given above using a GAL22V10 chip and additional
components (if necessary). Demonstrate the function of the circuit to the instructor.
1. Obtain a complete truth table
2. Write a CUPL program, compile the program and obtain. DOC and JEDEC files.
3. Program a GAL22V10 using Allpro programmer.
4. Construct a circuit to demonstrate the function of the device. Add additional external
components if the design can not be implemented in a single GAL22V10.

Lab report:
In your lab report provide a truth table; .PLD, .DOC and .JEDC files provide the circuit
diagram.