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  • 2016 Low Power

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    Rajender Reddy
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    A five day workshop on "Low Power System on Chip Design Using Xilinx FPGA Devices" was conducted by the Department of Electronics and Communication Engineering at J.B. Institute of Engineering & Technology, Hyderabad from September 5-9, 2016. Over 50 students attended the workshop where they learned about hardware verified power solutions, ultra scale FPGAs, Versal ACAPs, thermal design, and the Xilinx Power Estimator tool. The workshop aimed to educate participants on the importance and applications of low power system on chip design using Xilinx FPGA devices.

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    A five day workshop on "Low Power System on Chip Design Using Xilinx FPGA Devices" was conducted by the Department of Electronics and Communication Engineering at J.B. Institute of Engineering & Technology, Hyderabad from September 5-9, 2016. Over 50 students attended the workshop where they learned about hardware verified power solutions, ultra scale FPGAs, Versal ACAPs, thermal design, and the Xilinx Power Estimator tool. The workshop aimed to educate participants on the importance and applications of low power system on chip design using Xilinx FPGA devices.

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    © All Rights Reserved
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    42 views4 pages

    2016 Low Power

    Uploaded by

    Rajender Reddy
    A five day workshop on "Low Power System on Chip Design Using Xilinx FPGA Devices" was conducted by the Department of Electronics and Communication Engineering at J.B. Institute of Engineering & Technology, Hyderabad from September 5-9, 2016. Over 50 students attended the workshop where they learned about hardware verified power solutions, ultra scale FPGAs, Versal ACAPs, thermal design, and the Xilinx Power Estimator tool. The workshop aimed to educate participants on the importance and applications of low power system on chip design using Xilinx FPGA devices.

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    of 4

    TECHNOLOGY

    J.B.INSTITUTE OF ENGG &


    (UGC Autonomous)
    COMMUNICATION ENGINEERING
    DEPT. OF ELECTRONICS &

    CIRCULAR

    Date:02-09-2016

    on "Low Power
    invited /informed that a five day workshop
    All the faculty members are
    09-09-
    on 05-09-2016 to
    Xilinx FPGA Devices" will be conducted
    System on Chip Design Using
    2016 at 10.00AM at Seminar Hall.

    Contact
    Mr. N. Ramesh
    Assoc. Professor, ECE

    students.
    Note: Circulate to faculties and

    Tawhesds
    HOD ECE
    HOD ECE
    Technolog:

    Engineering&

    JB
    Institute of
    (uGC Autonomous AICTE

    Approved
    by
    by NAAC,
    Permanently i i a t e d JNTUH)

    (Accrecitec!

    andal

    Moinabad

    Nagar,
    Hyderabad-500
    B h a s k a r 075
    Report

    Five Day Workshop on Low Power System on Chip Design Using Xilinx
    FPGA Devices

    Xilinx FPGA Devices" was


    A Five Day Workshop on "Low Power System on Chip Design Using J.B.
    conducted by Department of Electronics and Communication Engineering
    Department at
    09-09-2016.
    Institute of Engineering & Technology, Hyderabad from 05-09-2016 to
    ascertained that need of
    Dr.P.V S. SRINIVAS, Principal of the college, during the inaugural address,
    such training.
    Department
    Dr. TOWHEED SULTANA, Head of Electronics and Communication Engineering
    and its applications
    during addressed abot the importance of Low Power System on Chip Design
    using Using Xilinx FPGA Devices

    Dr. A.K. CHAKRABARTY was the resource person..

    Low Power System on Chip Design Using


    During the session participants learned importance of
    Xilinx FPGA Devices.

    >Hardware Verified Power Solutions

    Ultrasacle +FPGAs
    Versal ACAP
    Thermal design
    >Xilinx Power Estimator (XPE)

    coordinated the program with their concerted efforts and


    Coordinators along with department faculty
    made the program more eventful and educative.

    lowheeelS

    HOD
    HOD- ECE

    Engineering
    & Tochnoiogy
    JB Institute of
    (LuGC Autonomous AICTE
    Approved by
    Accredited by NAAC,
    Permanentty iliated JNTUH)
    Mandal
    Moinabad
    Bhaskar Nagar,
    Hyderabad-500 075
    J.B. Institute of Engineering and Technology
    Communication Engineering
    Department of Electronics and
    A five day workshop on "Low Power System on Chlp Deslgn Using Xillinx FPGA Devices" StudentsS

    Attendance Sheet
    Roll No Name Day 1 Day 2 Day 3 Day4 Day 5
    S.No
    1 |12671A0401 CHINNAM SRI TEJA
    12671A0402 RAMIDI RAMESH
    12671A0403 VALAKATLA ASHOK
    4 12671A0404 Y YESWANTH KUMAR REDDY
    12671A0405 BATTU SRIKANTH
    12671A0406 JANAGAMA MOUNASAGAR
    12671A0407 VEMULA MANOJ
    12671A0408 KHAJA MD AKRAM ALI ANSARI
    w

    12671A0409 VASAM SAIKAVYA


    10 12671A0410 A SAIDAIAH

    11 12671A0411 CHIRAMDASU AKHIL

    |12671A0412 CHENNABOINA SHIVA KUMAR


    12
    13 |12671A0413 VANGARA RAVI TEJA

    12671A0414 BOORGU SAI KAVYA


    DESOJU SHIVA
    12671A04115
    16 12671A0416 MGOVARDHAN
    CHAKALI RAGHAVENDAR
    12671A0417
    BANOTHU RAJENDER
    12671A0418
    19 12671A0419 MANCHALA RISHI

    BODA SUNIL
    20 12671A0420
    MANASA PRIYADARSHINI
    21 12671A0421
    AFEEFA FATHIMA
    22 12671A0422
    A SAI PRABHA
    23 |12671A0423
    KARI VENKATA HANUMA SAI VISHWAK
    24 12671A0424

    12671A0425 THANDU SATISH


    25
    KALLEDA SOUJANYA
    26 12671A0426
    BUPATHI sWAPNA
    27 12671A0427
    GURRALA VINAYKUMAR
    28 12671A0428
    MATTEGUNTA JAHNAVI
    29 12671A0430
    V SESHA LAKSHMI SHREYA
    30 12671A0431
    CHINTHA VENU VISHWANATH
    31 12671A04332
    32 12671A0433 PROOPA
    SHIVANI ABHYANKAR
    33 12671A0434

    34 12671A0435 GIRIDHAR CHOWDHARY


    KOMMIDI RANJITH REDDY
    35 12671A0436
    36 12671A0437 B.SURYA VAMSI
    THIRUMALA HARSHITH KUMAR
    12671A0438
    MAKTHALA AKHILA
    38 12671A0439
    39 12671A0440 BOJJAGANI KISHAN

    40 12671A0441 G.MAYUR
    K.SRAVAN
    41 12671A0442
    42 12671A0443 M.LIKHITHAA
    12671A0444 JAMI SAI TEJA

    44 12671A0445 CH HARISH

    45 12671A0446 N.PRUTHV
    46 12671A0447 B.SAI SREE
    47 12671A0448 NANNAKA.vISHWANTH
    18 12671A0449 |SINDHURI.MOUNIKA
    49 12671A0450 T.MOUNISHA
    C.SRUTHI PRASAD
    50 12671A0451
    12671A0452 KAILASH LOYA
    MANTHA NIKHIL KUMAR
    52 12671A0453
    EGA.SURYA SAI KRISHNA
    12671A0454
    M.S.ANANTH SAYAN
    12671A0455
    V.VINOD KUMAR
    12671A04S6
    T.SOWMYA SRI
    56 12671A0457
    THATI RAVITEJA
    12671A0458
    K.ABHILASH REDDY
    58 12671A0459
    KANAKAM SRINIVAS
    59 12671A0460
    60 13675A0401 FARHA NAAZ
    BURRA REVANTH KUMAR
    61 13675A0402
    SATEESH KARRE
    62 13675A0403
    VALABOZU CHANDRA SHEKAR
    63 13675A0404
    NEERATI MOUNIKA
    64 13675A0405
    KARRE SRINIVAS
    65 13675A0406
    BODA GOUTHAMRA
    13675A0407
    MUTHYAM PRASAD
    67 13675A0408
    M VISHNU VARDHAN
    68 13675A0409
    E SREENUNAYAK
    13675A0410
    IRUKULA RAKESH
    7013675A0411
    KRANTHI KUMAR
    1 13675A0412 KARUKURI

    Teshaeds
    HOD E C E

    Engineering
    & fechnotogy
    Institute of
    JB (LIGC AItonomous)

    AlCTE.
    Approved by
    (Accieditecd
    Permanentlyby NAAC,
    tfiliated JNTUH)
    Mandal
    Moinabad
    Bhaskar Nagar,
    Hyderabad-500 075.

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