Digital Electronics Sem.: 3rd Sem. B.Tech.

Digital Logic Design

Assignment-2
Q.1 Explain design procedure of combinational circuit.
Q.2 Design a full-adder with two half-adders and an OR gate.
Q.3 Design a full subtractor with two half subtractor and an OR gate.
Q.4 Design 4-bit binary to gray code convertor.
Q.5 What is disadvantage of Binary Parallel adder? How it can be overcome?
Q.6 Design combinational circuit to convert BCD number to Excess-3.
Q.7 Design BCD to Excess-3 code converter using minimum number of NAND gates.
Q.8 Design combinational circuit which multiply a decimal digit by 5. Both input and
output are represented in BCD form.
Q.9 Design a combinational circuit that generates the 9′ complement of a BCD digit.
Q.10 Design a combinational circuit that accepts a three bit binary number and
generates an output binary number equal to the square of the input number.
Q.11 Design a combinational circuit whose input is four bit binary number and output
is the 2’s complement of the input binary number.
Q.12 How many don’t care condition are there in BCD adder?
Q.13 What is carry propagation?
Q.14 Construct 4x16 decoder with two 3x8 decoders.
Q.15 Design a BCD to decimal decoder.
Q.16 Explain BCD to 7-segment display decoder in common cathode configuration.
Q.17 Implement following Boolean function using Decoder.
a) 𝐹1 (𝑎, 𝑏, 𝑐, 𝑑) = ∑(1,3,5,2,11,15)and 𝐹2 (𝑎, 𝑏, 𝑐, 𝑑) = ∑(1,5,7,14,13)
b) 𝐹1 (𝑎, 𝑏, 𝑐, 𝑑) = ∑(1,12,3,2,14,15)and 𝐹2 (𝑎, 𝑏, 𝑐, 𝑑) = ∑(0,5,7,8,9)
c) 𝐹 = 𝑥 ′ 𝑦 ′ 𝑧 ′ + 𝑥 ′ 𝑦 ′ 𝑧 + 𝑥𝑦 ′ 𝑧 ′ + 𝑥𝑦 ′ 𝑧
d) 𝐹(𝑤, 𝑥, 𝑦, 𝑧) = ∏(1,2,3,5,8,11,15)
e) Full adder.
Q.18 Implement HEX to Binary Encoder.
Q.19 What is difference between encoder and priority encoder?
Q.20 Implement 16:1 multiplexer using 4:1 multiplexers.
Digital Electronics Sem.: 3rd Sem. B.Tech.

Q.21 Implement a full adder circuit using two 4:1 MUX.

Q.22 Implement following Boolean function using Multiplexer.
a) 𝐹1 (𝑎, 𝑏, 𝑐, 𝑑) = ∑(1,3,5,2,11,15) and 𝐹2 (𝑎, 𝑏, 𝑐, 𝑑) = ∑(1,5,7,14,13)
b) 𝐹 = 𝑥 ′ 𝑦 ′ 𝑧 ′ + 𝑥 ′ 𝑦 ′ 𝑧 + 𝑥𝑦 ′ 𝑧 ′ + 𝑥𝑦 ′ 𝑧
c) 𝐹(𝑤, 𝑥, 𝑦, 𝑧) = ∏(1,2,3,5,8,11,15)
d) Full adder.
Q.23 Implement following function using 4:1 multiplexer
F(A,B,C)=Σ (1,3,4,6)
Q.24 Implement the following function using 8:1 multiplexer
a) F(A,B,C,D)=Σ (2,4,5,7,10,14)
b) F(A,B,C,D)=Π(0,2,4,6,8,10,12,14)
Q.25 Implement the following Boolean functions using ROM
F1(A,B,C)= Σ (1,3,4,6)
F2(A,B,C)= Σ (0,5,6,7)
F3(A,B,C)= Σ (2,3,5,6)
Q.26 What is the minimum size of ROM to implement Full adder?
Q.27 Classification of ROM.
Q.28 Write a short note on Read Only Memory (ROM).
Q.29 Write a short note on Programmable Logic Array (PLA).
Q.30 Implement following Boolean function using PLA.
a) 𝐹1 (𝑎, 𝑏, 𝑐, 𝑑) = ∑(1,3,5,2,11,15)and 𝐹2 (𝑎, 𝑏, 𝑐, 𝑑) = ∑(1,5,7,14,13)
b) 𝐹1 (𝑎, 𝑏, 𝑐, 𝑑) = ∑(1,12,3,2,14,15)and 𝐹2 (𝑎, 𝑏, 𝑐, 𝑑) = ∑(0,5,7,8,9)
c) 𝐹1 (𝑎, 𝑏, 𝑐) = ∑(1,4,5,7) and 𝐹2 (𝑎, 𝑏, 𝑐) = ∑(1,4,5,6)
d) 𝐹 = 𝑥 ′ 𝑦 ′ 𝑧 ′ + 𝑥 ′ 𝑦 ′ 𝑧 + 𝑥𝑦 ′ 𝑧 ′ + 𝑥𝑦 ′ 𝑧
e) 𝐹(𝑤, 𝑥, 𝑦, 𝑧) = ∏(1,2,3,5,8,11,15)
f) Full adder.