EEE-251 Digital Logic Design Laboratory
Logic Gates Experiment
Name: Ahmet Yusuf Yatkın
Dep.: Electrical and Electronics Engineering
Student Number: 18290239
ahmetyusufyatkin@gmail.com
Abstract—In this experiment, we gave different
combinations of inputs to some logic gates (NAND, NOR, NOT,
XOR gates), and checked the outputs. Our aim was
demonstrating the how some logic gates work and what output
will they give. Our results matched with theoretical information.
Keywords—NAND Gate, NOR Gate, NOT gate, XOR gate,
Logic Gates, Truth Table, HI(HIGH) state, LOW state.
I. INTRODUCTION
Logic Gates is design to control some logical operations
of electrical inputs. Logical gates basically process their inputs
and give the output from those inputs what it designed for. our
experiment aims to demonstrate behavior some of the logical
gates mentioned in keywords. We gave inputs to these gates
and tested the output.
II. THEORETICAL BACKROUND
First, we began with NAND gate, NAND gate, known as
Not-AND gate inverses the AND gate truth table. NAND gate
outputs HIGH when one or all the inputs are LOW. It only
output LOW when both inputs are HIGH. In experiment, we
set test console controls to its initial control settings. And we
plugged PC112 card to PC1 position, and the PC103 Card
(which have NAND gates in its circuit) to PC2 Position. Then
gave +5V to cards. And we set the oscilloscope to needed
settings. We used one to one probe for oscilloscope’s CH1,
and BNC to BNC cable to X trigger. And we did other
connections given in instructions. Then we switched PC112
card switches to follows; S1 to HI, and S2 to HI. And we
measured TP1 Input point for NAND gate. Result was HI.
And Also, we measured TP2 Input point as HI. Then we
connect test probe to TP3, output was LOW. This is expected
for NAND gate (If both inputs are HI, output will be LOW).
Then we switch our Input switches S1 to HI and S2 to LOW
to check what output will be. We measured Input 1 as HI, and
Input 2 as LOW. Result measurement output was HI. This is
also expected. To do other combination, we set S1 Input to
Pulse, and S2 to HI. (we checked the inputs) Our output
measured as Pulsing. We switched PC1 and PC2 DC power
off to finish the experiment. Detailed results will be given in
results part.
Second, we did NOR gate experiment. NOR gate, known
as Not-OR gate inverses the OR gate truth table. NOR gate
outputs HIGH when both inputs are in LOW state. Other
combinations always output LOW state. In experiment, we
set test console controls to its initial control settings. And we
plugged PC112 card to PC1 position, and the PC105 Card
(which have NOR gates in its circuit) to PC2 Position. Then
gave +5V to cards. And we set the oscilloscope to needed
settings. We used one to one probe for oscilloscope’s CH1,
and BNC to BNC cable to X trigger. And we did other
connections given in instructions. Then, we switch NOR
gate’s input switches S1 to HI and S2 to HI. we measured
TP2 and TP3 inputs to check if matches with S1 and S2. TP2
and TP3 inputs shown as HI in oscilloscope screen. And
finally, we check the TP1 (Output of NOR gate), shown as
LOW state in oscilloscope screen. We set S1 switch to HI, S2
switch to LOW to test other combination. Since Input 1 (S1
switch’s output) Connected to TP2, and Input 2 (S2 switch’s
output) connected to TP3, they gave same states all the
experiment. Continuing steps will mention only one of these
points due to same states. Our TP1 point (output of NOR
gate) shown in LOW state. Then we set S1 and S2 switches
to LOW, which will set Input 1 and Input 2 to LOW state. We
measured Output of NOR gate as HI state. Then, we set S1
switch to HI S2 to Pulse. Then, we measured output (TP1) as
LOW state since one of the inputs is HI state. We switched
PC1 and PC2 DC power off to finish the experiment. Detailed
results will be given in results part.
Third, we did NOT gate (Inverter) experiment. NOT gates
basically inverts power which given in its input. So, if input
is LOW state, output will be HI state. If input is HI state, then
output will be LOW state. In experiment, we set test console
controls to its initial control settings. And we plugged PC112
card to PC1 position, and the PC106 Card (which have NOT
gates in its circuit) to PC2 Position. Then gave +5V to cards.
And we set the oscilloscope to needed settings. We used one
to one probe for oscilloscope’s CH1, and BNC to BNC cable
to X trigger. And we did other connections given in
instructions. We switch S1 to HI and S2 to HI. We see TP1 is
connected to S1 switch’s output. For input 1, Logic level is
HI state. And we place oscilloscope probe to TP2 point to
check output. Output was LOW state. Then we take probe to
TP3 point. Now we are measuring the input of our second
NOT gate’s Input. It stated HI. and then we checked TP4
point (output). Measured as LOW state. Then we switched
S1 switch to LOW state (input of TP1) and checked the
output. Output was HI. then we switch S3 switch to LOW and
checked TP3 (Input) is LOW. and the output of TP4 was HI
state. Then we switched the S1 switch to Pulse mode, now
input on TP1 is pulsing. And when we checked the output of
TP2, we see it’s pulsing too. But Output pulsing inverses the For the last experiment, XOR gate will output LOW if
input pulse. We switched PC1 and PC2 DC power off to both inputs are in same state. For other options, will output
finish the experiment. Detailed results will be given in results HI. If one of the input is Pulsed and the other is in HI state,
part. output will be pulse because when HI wave in pulse reached,
both inputs get same state that make output LOW, but when
Finally, we did XOR gate experiment. XOR gate, know LOW part of wave in input reached, due to difference in
as Exclusive OR gate, outputs HI if inputs are in different inputs XOR gate will output HI. It goes on for every wave,
states. Outputs LOW if inputs have same state. In experiment, and will be output pulsed. Also, my Proteus simulations
we set test console controls to its initial control settings. And prove all of these situations
we plugged PC112 card to PC1 position, and the PC107 Card
(which have XOR gates in its circuit) to PC2 Position. Then
gave +5V to cards. And we set the oscilloscope to needed IV. CONCLUSION
settings. We used one to one probe for oscilloscope’s CH1, To conclude, all of our experiments, theoretical
and BNC to BNC cable to X trigger. And we did other information and the simulation proved each other. All results
connections given in instructions. Then we switched PC112 are same in these three ways. With these experiments, we’ve
card switches to follows; S1 to HI, and S2 to HI. we checked learned the which output we’ll get in which input states in
the input test points (TP1, TP2) as HI. and we measured the inspected logical gates.
signal at TP3 (output of gate) as LOW state. Then we set S1
REFERENCES
to HI S2 to LOW to see other combination of inputs. When
[1] Lecture Videos of related week published by Ankara University
we checked output, oscilloscope screen shows HI state for
TP3. Then we set S1 switch to LOW and S2 switch remains [2] Experiment Videos of related week published by Ankara University
LOW. since they are inputs of TP1 and TP2, we measured [3] Researcher knowledge
same States with S1 and S2 switch output. And to check logic
gate output, we take oscilloscope probe to TP3 point (output
of gate) and output was LOW state. Then we set S1 to Pulse,
S2 to HI state. (Inputs same as S1 and S2 states) and we check
the TP3 point (output). Output was pulsing. Then computer
changed one of the Input’s state, and output gave HI state, the
changed input was TP1 from Pulse to LOW state.
III. EXPERIMENTAL RESULTS
For the first experiment, NAND gate supposed to output
LOW when both inputs are HI. this is because of NAND
gate’s work style. When one input is LOW and the other is
HI, this must output HI state. In our experiment, we proved
these situations. When Input 1 is pulsed, and other input is HI
state, Output pulsed. This is because one of our input remains
HI while other pulsing, when Pulsing input takes HI state, this
makes output LOW, and when Pulse input reach LOW state,
this makes output HI. than we can see output is pulsing in
time. Also, my Proteus simulations prove all of these
situations

For second experiment NOR gate supposed to output

LOW when both inputs are HI, Also if just one of input is HI,
Output again will be LOW. the only option that makes output
HI is then both input in LOW state. Last part of our
experiment, one of our inputs pulsing while other is HI, we
saw output remains on LOW state, because one HI state is
enough to make our output LOW, pulsing doesn’t important
while other input is HI state. Also, my Proteus simulations
prove all of these situations

For Third experiment NOT gate supposed to inverse input.

If input is HI, then output will be LOW, if input LOW then
output will be HI. if input pulses, output will be pulse, note
that it takes LOW when input pulse has HI, takes HI when
input pulse has LOW state. Also, my Proteus simulations
prove all of these situations