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Frequency Synthesizer Circuit
Frequency Synthesizer Circuit
Frequency Synthesizer Circuit
But at the same time it also has large spurious and limitation to the output
bandwidth
Frequency synthesizer circuit
• PLL is characterized by:
Low phase noise
wide output bandwidth
But there is problem between its frequency resolution and frequency switching
time
• Here, we will combine with DDS and PLL to make the best use of their respective
strengths to make up for each other's deficiencies
• Therefore, a better quality spectrum can be obtained under the premise of hop
rate, so as to achieve the indexes required by the frequency synthesizer
Crystal oscillator
• PLL reference clock is provided by the Temperature Compensated Crystal
Oscillator (TCXO-SMD-053-3.3V-19.2MHz)
• The selection criteria of the crystal oscillator mainly includes the following points:
• 2R17, 2R18 are dividing resistors at the adjust end of the crystal oscillator
• Adjusting the value of the dividing voltage can help to fine-tune the output
frequency
• The accuracy of the crystal oscillator frequency directly affects the accuracy of
the output frequency of subsequent stage of PLL.
Phased locked loop (PLL)
• We SI4133 circuit produced by SILICON Company
• IF synthesizer
• SI4133 includes:
Three VCOs
• Each center frequency is established by the value of an external inductance connected to the respective VCO
• Because the total tank inductance is in the low nH range, the inductance of the package must be considered when
determining the correct external inductance
• The total inductance (LTOT) presented to each VCO is the sum of the external inductance (LEXT) and the package
inductance (LPKG)
• Each VCO has a nominal capacitance (CNOM) in parallel with the total inductance, and the center frequency is as
follows:
Setting the VCO Center Frequencies
Design Example
• Consider that the goal is to synthesize frequencies in a 25 MHz band between 1120 and 1145 MHz
using the Si4133-GT.
• The PLL can adjust the VCO output frequency ±5% of the center frequency, or ±56.6 MHz of
1132.5 MHz
• A 4.1 nH inductance in parallel with this capacitance yields the required center frequency
Design Example
• An external inductance of 1.8 nH should be connected between RFLC and RFLD
• In Register 7,
The decimal number of R frequency tuning word of RF2 is 80
N
Fout = × Fref
R
• In Register 8
The decimal number of R frequency tuning word of IF is 24
• IF output
N
fout = × fref
R
• Register 0, the input code controls 1/2 of the output frequency of IF,
The frequency is 921.6MHz / 2 = 460.8MHz.
After subsequent filtering, the signal is input to DDS, being as DDS reference
clock,
Output coupling and Matching
• The RF output signal must be AC coupled to its load through a capacitor
• An External inductance between the RFOUT pin and the AC coupling capacitor
• The IFOUT pin must also be AC coupled to its load through a capacitor
The value of Inductor Match
RF output to Second local oscillator
• Pin 10 outputs 960.72MHz send to UPB587.
Twice
Four times
Eight times
Setting of frequency division
• In our design:
500 hops/sec
DDS
• During reception AD9954 DDS chip output local oscillator from 31.66 ~
89.635MHz
𝐹𝑇𝑊
𝑓𝑜𝑢𝑡 = × 𝑓𝑐𝑙𝑘
232
DDS Core
• Register 4 of DDS is the register of Frequency Control Word
At 30.025MHz
• 𝑅𝑠𝑒𝑡 = ൗ𝐼𝑜𝑢𝑡 Ω
39.9
Common Mode Noise
Circuit of Transmitting Channel
• During transmitting, DDS outputs RF signals of 30~87.975MHz
• Pin 20 and Pin 21 output the differential RF signals, which can reduce common
mode interference
• DC isolation
DAC output and final load
DDS circuit
Low Pass Filter
TX Channel
• DDS output is a common part for RX and TX
DC-8 GHz
Stable
• Output power:
High power =4 W
Middle power = 2 W
VG = 3V (Regulator?)
• Power voltage:
• Power consumption:
Amplification
Mixing and
• The device model is MA4P7002F-1072T, and its main role is to isolate the
receiving channel from the transmitting channel
PIN diode
• The device is a high-pressure PIN diode
Isolation
Small insertion
• Oscillator:
• Usually BITE is equal to zero, it is high after the operation of MENU-BITE-YES on the
radio
• After 2B3 is turned on, Pin 4 of 2B4 is powered up to work, and it generate 50MHz RF
• At the same time, DDS part of the frequency synthesizer generates a local oscillation
signal of 69.635MHz
Tunable Filter
• 2Z1 is a first-class electrically tunable filter of receiving channel
• The range of control voltage is about 0.8V ~ 13.6V, and the corresponding center
frequency of the filter is 30 ~ 87.975MHz
• The voltage is supplied by 2N21, which is a high precision, low noise, low voltage
bias wideband operational amplifier
2R35
• Vout = 1 + × Vin
2R33 ||2R34
22K
• Vin = 1 + × Vin
3.16K
Vout = 8 ∗ Vin
OP-AMP output test data
• The amplifier is to amplify the input voltage for eight times
Non-linear Gain
Parameter table of voltage amplification of
• Positive and Negative power supply for the Op-Amplifier
• Features:
High Gain
Aqueous washable
Intermediate frequency
• Mixer output:
Harmonic signals
• IF output =119.635MHz is the only useful signal, and others are interference
Excellent selectivity
Mixer/oscillator
Two IF amplifiers
Quadrature detector
RSSI
SA605DK
• Four main sections:
Mixer section
IF section
Demodulator section
Output section
Pin configuration
Mixer section
• Three areas in the mixer section
RF signal
LO signal
IF output
• The Gilbert cell is a differential amplifier (pins 1 and 2) that drives a balanced
switching cell
Matching circuit
• RF input impedance is about 4.5kΩ
2C24=120pF, 2C180=51pF
2L13=47nH
• 10.7 MHz
Sensitivity is lower
• IF amplifier:
Amplify IF signals
Can not provide a good limit in the wide range of input signal
• LTM455CU BW=25kHz
• It inputs to pin 14, and then enters the limiter to amplify the limiting
IF limiter
• Apply high gain to the IF frequency such that the
• Detector is composed:
• Pin 7 RSSI
Before the design, a number of different amplitude of test signals can be added to the radio
antenna end
Through the measurement of the data, you can obtain different input amplitudes and different
RSSI output voltage
When the self-test signal puts in to the MCU, the size of the level can be used as a