Implement a Digital Clock on FPGA Board

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Digital_Clock is
port(clk_100 : in std_logic;
second : out std_logic_vector(5 downto 0);
HEX3, HEX2, HEX1, HEX0 : OUT STD_LOGIC_VECTOR(0 TO 6));
end Digital_Clock;

architecture beh of Digital_Clock is

signal ss, mm : integer range 0 to 59;
signal hr : integer range 0 to 23;
signal count : integer := 1;
signal clk1 : std_logic := '1';

signal second_t : std_logic_vector(5 downto 0);

signal minute_t : std_logic_vector(5 downto 0);
signal hour_t : std_logic_vector(5 downto 0);
signal minute_bcd : std_logic_vector(7 downto 0);
signal hour_bcd : std_logic_vector(7 downto 0);

component bin_to_bcd is
port(bin_in : in std_logic_vector(5 downto 0);
bcd_out : out std_logic_vector(7 downto 0));
end component;

component hex7seg IS
PORT ( hex : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
display : OUT STD_LOGIC_VECTOR(0 TO 6));
END component;

begin
-- 1 Hz clock Generation from 50 MHz clock.
clock_generation : process (clk_100)
begin
if (rising_edge(clk_100)) then
count <= count + 1;
if (count = 50000000) then
clk1 <= not clk1;
count <= 1;
end if;
end if;
end process;
-- Functionality of Digital Clock.
digital : process (clk1)
begin
if (rising_edge(clk1)) then
if (ss = 59) then
ss <= 0;
if (mm = 59) then
mm <= 0;
if (hr = 23) then
hr <= 0;
else
hr <= hr + 1;
end if;
else
mm <= mm + 1;
end if;
else
ss <= ss + 1;
end if;
end if;
end process;

--Converts Integer Values into Standard Logic Vector.

second_t <= conv_std_logic_vector(ss,6);
minute_t <= conv_std_logic_vector(mm,6);
hour_t <= '0' & conv_std_logic_vector(hr,5);

second <= second_t;

B1 : bin_to_bcd port map(hour_t, hour_bcd);

B2 : bin_to_bcd port map(minute_t, minute_bcd);

S1: hex7seg port map(minute_bcd(3 downto 0), HEX0);

S2: hex7seg port map(minute_bcd(7 downto 4), HEX1);
S3: hex7seg port map(hour_bcd(3 downto 0), HEX2);
S4: hex7seg port map(hour_bcd(7 downto 4), HEX3);

end beh;

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bin_to_bcd is
port(bin_in : in std_logic_vector(5 downto 0);
bcd_out : out std_logic_vector(7 downto 0));
end bin_to_bcd;
architecture behav of bin_to_bcd is

begin

process(bin_in)
begin
case bin_in is

when "000000" => bcd_out <= "00000000";

when "000001" => bcd_out <= "00000001";
when "000010" => bcd_out <= "00000010";
when "000011" => bcd_out <= "00000011";
when "000100" => bcd_out <= "00000100";
when "000101" => bcd_out <= "00000101";
when "000110" => bcd_out <= "00000110";
when "000111" => bcd_out <= "00000111";
when "001000" => bcd_out <= "00001000";
when "001001" => bcd_out <= "00001001";
when "001010" => bcd_out <= "00010000";
when "001011" => bcd_out <= "00010001";
when "001100" => bcd_out <= "00010010";
when "001101" => bcd_out <= "00010011";
when "001110" => bcd_out <= "00010100";
when "001111" => bcd_out <= "00010101";
when "010000" => bcd_out <= "00010110";
when "010001" => bcd_out <= "00010111";
when "010010" => bcd_out <= "00011000";
when "010011" => bcd_out <= "00011001";
when "010100" => bcd_out <= "00100000";
when "010101" => bcd_out <= "00100001";
when "010110" => bcd_out <= "00100010";
when "010111" => bcd_out <= "00100011";
when "011000" => bcd_out <= "00100100";
when "011001" => bcd_out <= "00100101";
when "011010" => bcd_out <= "00100110";
when "011011" => bcd_out <= "00100111";
when "011100" => bcd_out <= "00101000";
when "011101" => bcd_out <= "00101001";
when "011110" => bcd_out <= "00110000";
when "011111" => bcd_out <= "00110001"; -- 31
when "100000" => bcd_out <= "00110010"; -- 32
when "100001" => bcd_out <= "00110011";
when "100010" => bcd_out <= "00110100";
when "100011" => bcd_out <= "00110101";
when "100100" => bcd_out <= "00110110";
when "100101" => bcd_out <= "00110111";
when "100110" => bcd_out <= "00111000";
when "100111" => bcd_out <= "00111001"; -- 39
when "101000" => bcd_out <= "01000000"; --40
when "101001" => bcd_out <= "01000001";
when "101010" => bcd_out <= "01000010";
when "101011" => bcd_out <= "01000011";
when "101100" => bcd_out <= "01000100";
when "101101" => bcd_out <= "01000101";
when "101110" => bcd_out <= "01000110";
when "101111" => bcd_out <= "01000111";
when "110000" => bcd_out <= "01001000";
when "110001" => bcd_out <= "01001001"; --49
when "110010" => bcd_out <= "01010000"; -- 50
when "110011" => bcd_out <= "01010001";
when "110100" => bcd_out <= "01010010";
when "110101" => bcd_out <= "01010011";
when "110110" => bcd_out <= "01010100";
when "110111" => bcd_out <= "01010101";
when "111000" => bcd_out <= "01010110";
when "111001" => bcd_out <= "01010111";
when "111010" => bcd_out <= "01011000";
when "111011" => bcd_out <= "01011001"; --59
when others => bcd_out <= "00000000";

end case;

end process;

end behav;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

-- the B input blanks the display when B = 1

ENTITY hex7seg IS
PORT ( hex : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
display : OUT STD_LOGIC_VECTOR(0 TO 6));
END hex7seg;

ARCHITECTURE Behavior OF hex7seg IS

BEGIN
--
-- 0
-- ---
-- | |
-- 5| |1
-- | 6 |
-- ---
-- | |
-- 4| |2
-- | |
-- ---
-- 3
 --
PROCESS (hex)
BEGIN
CASE (hex) IS
WHEN "0000" => display <= "0000001";
WHEN "0001" => display <= "1001111";
WHEN "0010" => display <= "0010010";
WHEN "0011" => display <= "0000110";
WHEN "0100" => display <= "1001100";
WHEN "0101" => display <= "0100100";
WHEN "0110" => display <= "1100000";
WHEN "0111" => display <= "0001111";
WHEN "1000" => display <= "0000000";
WHEN "1001" => display <= "0001100";
WHEN "1010" => display <= "0001000";
WHEN "1011" => display <= "1100000";
WHEN "1100" => display <= "0110001";
WHEN "1101" => display <= "1000010";
WHEN "1110" => display <= "0110000";
WHEN OTHERS => display <= "0111000";
END CASE;
END PROCESS;
END Behavior;