FSM Module

SEQUENTIAL LOGIC
DESIGN
Prof. Kanchan S. Gorde, TEC 1

Types of State Machines
State machine: generic name for sequential
circuits; (Finite State Machine: FSM)
Mealy Machine
Inputs Next Excitation State

Output
State Memory
Current Logic Outputs
Logic (F/F)
State
CLOCK
Next state= F (current state, input)

Output= G (current state, input)
 Characterized by – Outputs are a function of both
inputs and current state
Moore Machine
Inputs Next Excitation State

Output
State Memory
Current Logic Outputs
Logic (F/F)
State
CLOCK
Next state= F (current state, input)

Output= G (current state)
 Characterized by – Outputs are a function of

current state only

A Mealy Machine is an FSM whose output depends on the present state as well as the present
input. Moore machine is an FSM whose outputs depend on only the present state. Generally
speaking, Mealy machines tend to have fewer states, and Moore machines are safer to use.
Moore Machine –
1.Output depends only upon present state.
2.If input changes, output does not change.
3.More number of states are required.
4.There is less hardware requirement for circuit implementation.
5.They react slower to inputs(One clock cycle later).
6.Synchronous output and state generation.
7.Output is placed on states.
8.Easy to design.
Mealy Machine –
1.Output depends on present state as well as present input.
2.If input changes, output also changes.
3.Less number of states are required.
4.There is more hardware requirement for circuit implementation.
5.They react faster to inputs.
6.Asynchronous output generation.
7.Output is placed on transitions.
8.It is difficult to design. Prof. Kanchan S. Gorde, TEC 5
Characteristic Equations
• The Characteristic Equation formally specifies the flip-
flop’s next state as a function of its current state and inputs
• Q* means the next state value for the Q output of the F/F.
• S-R Latch/FF • Q* = S + R’ Q
• D Latch • Q* = D
• D F/F • Q* = D
• D F/F with Enable • Q* = EN D + EN’ Q
• J-K F/F • Q* = J Q’ + K’ Q
• T F/F • Q* = Q’
• T F/F with Enable
• Q* = EN Q’ + EN’ Q
Synthesis (Design) of a finite-state machine is the
process of finding a circuit implementation that
satisfies the behaviour of the FSM.
On the other hand, Analysis is breaking the FSM
apart to determine its behaviour and eventually its
function.

Clocked Synchronous State-
Machine Analysis
•The goal of a sequential circuit analysis is to determine
the next-state and output functions so that the behavior
of a circuit can be predicted.
• Theanalysis has basic steps:
Determine the excitation equations
Determine the transition equations.
Determine the output equations
To construct a transition/output table.
To construct a state/ output table.
Draw a state diagram
Find State Diagram

STATE REDUCTION & ASSIGNMENT
•State reduction is the elimination of states which are
equivalent within the state machine and state
assignment is the method of assigning a binary value to
a state name that will create a reduced logic equation.
•The three methods examined for state reduction are

(1) row matching method,
(2) implication chart method,
(3) successive partitioning method.
•The methods examined for state assignment are

(1) binary,
(2) gray code.
State Reduction Techniques
1. Row matching
It uses the state equivalence theorem: Si = Sj if and
only if for every single input X, the outputs are the same
and the next states are equivalent.
1. Start with the state transition table
2. Identify states with same output behavior
3. If such states transition to the same next state, they
are equivalent
4. Combine into a single new renamed state
5. Repeat until no new states are combined

EXAMPLE :

2. Implication Chart Method
•Uses a graphical grid of sorts to systematically find
equivalences among the states.

The steps that need to be taken in this method:
1. Construct implication chart, one square for each
combination of states taken two at a time.
2. Square labeled Si, Sj, if outputs differ then the square
gets an 'X'. Otherwise, write down implied state pairs for
all input combinations.
3. Advance through chart top-to-bottom and left-to-right.
If square Si, Sj contains next state pair Sm, Sn and that
pair labels a square already labeled 'X' then Si, Sj is
labeled 'X‘.
4. Continue executing Step 3 until no new squares are
marked with 'X‘.
5. For each remaining unmarked square Si, Sj, then Si
and Sj are equivalent.
3. Partitioning Method
method is a sort of hybrid between row matching and implication
chart in that it uses a visual detection for equivalences as well as
a chart to organize the process.
• The following state transition table example will be used to
demonstrate the partitioning method:
Sample transition table Machine table

•In order to start this reduction method, it is beneficial to
convert the transition table into a machine table which will
make it easier to transfer to the partition table. This is an
optional step, but it will save a little time in the long run.
•Refer to Machine Table. The rows of this machine table are
the state names from the transition table. The columns are
the next state conditions. The values within the cells are in
the form next state/output.
• The next step is to transfer the information into the
partitioning table as seen in Table below:
Partitioning table

•the next step is to find any of the outputs which are the
same, and then partition them off (or group them into a
partition) and record these in the P1 row (stands for partition
pass 1).
• The next step is to replace the outputs with the next state
names and then determine if any of the states need to be
partitioned out i.e. if states within the column being observed
are not within the partition, then it should be partitioned off
Partition 1 Partition 2
•After repeating this step for all columns and partitions, the final
partition table can be seen in Table:
Partition 3 (Final)
•The composite table with all of these steps combined can be

seen in Table .
Composite
partition table

•From the final step in the partition table, the states left grouped in
the partitions are all equivalent. In this case, the equivalences are
as follows:
A' = A = C = G = H
B' = B
C' = D
D' = E
E' = F
•The final step is to put the results of the successive partitioning
method back into either the state transition table or the state
machine table :
Final state machine table Final state transition table

State Assignment
Binary
•It counts up in binary starting from 0 and going up assigning
each state the next number.
•It uses Log2 bits to assign the states.
Gray Code
•Gray code was named after Frank Gray.
•In gray code, each successive state differs from the
previous state by only one bit.
•With only one bit changing from each state to the next,
power consumption is reduced from binary code where
multiple states can change at the same time.
•This allows for a minimum number of bits used and an also
a small equation for each bit.
Clocked Synchronous State-Machine
Design
•The steps for designing a clocked synchronous state
machine (the reverse of the analysis steps) :
1. Construct a state/output table corresponding to the
word description or specification, using mnemonic
names for the states.
2. Optional - minimize the number of states in the
state/output table.
3. Choose a set of state variables and assign state-
variable combinations to the named states.
4. Substitute the state-variable combinations into the
state/output table to create a transition/output table
that shows the desired next state-variable combination
and output for each state/input combination.
5. Choose a flip-flop type (e.g., D or J-K) for the state
memory.
6. Construct an excitation table that shows the
excitation values required to obtain the desired next
state for each state/input combination.
7. Derive excitation equations from the excitation
table.
8. Derive output equations from the transition/output
table.
9. Draw a logic diagram that shows the state-variable
storage elements and realizes the required excitation
and output equations. (Or realize the equations
directly in a programmable logic device.)

Q: Design FSM for give state diagram:
State output table

•State Assignments:
Let S0 = 00
S1 = 01
S2 = 10
S3 = 11
The above state table becomes:
Transition Output Table

•Four states will require two flip flops. Consider two D flip flops. Their excitation table
is shown below.
•Excitation table:

•K-maps to determine inputs to D Flip flop:
•Logic diagram:
Z
X’

In an overlapping sequence detector the last bit of one sequence
becomes the first bit of next sequence.
However, in non-overlapping sequence detector the last bit of
one sequence does not become the first bit of next sequence.
Examples:
For non overlapping case
Input : 0110101011001
Output:0000100010000
For overlapping case

Input : 0110101011001
Output:0000101010000
Design Mealy sequence detector to detect 1001
Overlapping
Non-Overlapping

Design Moore sequence detector to detect 1001
Overlapping
Non-Overlapping

Non-Overlapping
Overlapping

Non-Overlapping
Overlapping



Overlapping
Non-Overlapping

Overlapping
Non-Overlapping

Overlapping
Non-Overlapping

Overlapping
Non-Overlapping


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SEQUENTIAL LOGIC

Prof. Kanchan S. Gorde, TEC 1

Inputs Next Excitation State

Next state= F (current state, input)

Inputs Next Excitation State

Next state= F (current state, input)

 Characterized by – Outputs are a function of

Prof. Kanchan S. Gorde, TEC 3

process of finding a circuit implementation that

satisfies the behaviour of the FSM.

On the other hand, Analysis is breaking the FSM

apart to determine its behaviour and eventually its

Prof. Kanchan S. Gorde, TEC 7

Prof. Kanchan S. Gorde, TEC 25

•The three methods examined for state reduction are

•The methods examined for state assignment are

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Sample transition table Machine table

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•The composite table with all of these steps combined can be

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Final state machine table Final state transition table

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State output table

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The above state table becomes:

Transition Output Table

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For overlapping case

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