FPGA Building Blocks The architecture of the FPGA should be known by the reader to

appreciate its working principles. Although the reader will not directly interact with the architecture, this
knowledge will lead to better usage of the FPGA. Besides, design principles to be applied in
implementing a digital system on the FPGA will make sense. Therefore, we will introduce basic building
blocks of the FPGA (Xilinx Artix-7 XC7A35T) available on the Basys3 and Arty boards in this section. These
building blocks will be represented in abstract form. Since we do not want to go into detail of digital
electronics, we believe this level is sufficient. We will start with layout of the Xilinx Artix-7 XC7A35T
FPGA next.

2.2.1 Layout of the Xilinx Artix-7 XC7A35T FPGA

Basys3 and Arty boards have their FPGA from the Xilinx Artix-7 XC7A35T family. To be more specific, the
FPGA on the Basys3 board is XC7A35TCPG236-1. Similarly, the FPGA on the Arty board is
XC7A35TICSG324- 1L. These two FPGAs share similar properties. Therefore, we will call them by their
family name Xilinx Artix-7 XC7A35T from this point on. If there is a difference in the FPGA, then we
specify it by the board name. The Xilinx Artix-7 XC7A35T FPGA is basically composed of nine different
components. These are input/output blocks, configurable logic blocks (CLBs), interconnect resources,
block RAM, DSP slices, clock management block, XADC block, high-speed serial I/O transceivers, and PCIe
interface. Layout of these blocks is as in Fig. 2.9. Most of these blocks can also be observed via Vivado
design suite to be introduced in Chap. 4. Therefore, the reader will have chance to observe which of
them are used in his or her digital system design. Mentioned blocks (or their variants) are almost
standard in an FPGA. However, some of these may be missing or other extra blocks may be available in
different FPGA families. The reader should keep this in mind while using another FPGA family
2.2.2 Input/Output Blocks
A digital device interacts with the outside world through its input and output pins. This is also the case
for the FPGA. Hence, data from the outside world is acquired through input pins. Output is fed to the
outside world using output pins. Moreover, these input and output pins are located in input/output
blocks within the FPGA. The Artix-7 XC7A35T FPGA has input/output pins which can operate on standard
voltage levels from 1.2 to 3.3 V. The FPGA on the Basys3 board has 106 such input/output pins. In a
similar manner, the FPGA on the Arty board has 210 such pins. These input/output pins can be used as
input, output, and both. In the first case, data will be taken from outside world through the pin. In the
second case, voltage levels will be fed to outside world through the pin. In the third case, the same pin
can be used for both input and output purposes. Input/output pins are grouped into banks. Two pins in
these banks are grouped as positive (P) and negative (N) pairs. These can be used in two modes as
single-ended and differential. In the single-ended mode, input will be recognized as logic level zero when
input voltage is near ground. It will be recognized as logic level one when input voltage is near VCC. In
the differential mode, input will be recognized as logic level zero when the voltage at pin P is lower than
the voltage at pin N. When the voltage at pin P is higher than the voltage at pin N, then input will be
taken as logic level one. Input/output pins can also be used in reference mode. Here, input will be taken
as logic level zero when input voltage is below reference voltage. When input voltage is above reference
voltage, it will be taken as logic level one. Single-ended pins can also be used as output. When output is
at logic level one, the corresponding voltage value at the pin will be VCC. When output is at logic level
zero, the corresponding voltage value at the pin will be ground.

2.2.4 Interconnect Resources

What we mean by interconnect resources is a collection of wires and programmable switches. These are
responsible for connecting CLBs and other building blocks within the FPGA. Interconnect is also called
routing channels. CLBs in the Artix-7 FPGA are placed in a grid structure which simplifies planning of
interconnection usage. Note that it is not necessary to know interconnect features to use an FPGA at the
beginner or intermediate level.

2.2.10 Peripheral Component Interconnect Express Interface

Peripheral component interconnect express (PCIe) is a high-speed serial connection bus standard. The
Artix-7 XC7A35T FPGA has one integrated block for PCIe interfacing.