Nama : Ichsan Harun Wicaksono

NIM : 195060307111011

2.1 Multiplexer 2 input 1 output dengan model dataflow

Persamaan logika : 𝒎 = ( 𝒙 • 𝒔
̅) + (𝒔 • 𝒚)
Tabel kebenaran :
x y s 𝒙 • 𝒔̅ 𝒔 • 𝒚 m
0 0 0 0 0 0
0 0 1 0 0 0
1 0 0 1 0 1
1 0 1 0 0 0
0 1 0 0 0 0
0 1 1 0 1 1

Design
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;

entity mux is port(

x, y, s : IN std_logic;
m : OUT std_logic
);
end mux;
architecture df_mux of mux is
begin
m <= ((x and (not s)) or (y and s));
end df_mux;

Test Bench
library IEEE;
use IEEE.std_logic_1164.all;
entity tb_mux is
end tb_mux;
architecture df_tb_mux of tb_mux is
component mux is port(
x, y, s : IN std_logic;
m : OUT std_logic
);
end component;

signal xin, yin, sin, mout: std_logic;

begin

dut : mux PORT MAP(

x => xin,
y => yin,
s => sin,
m => mout
);

process

begin

xin <= '1';

yin <= '0';
sin <= '1';
wait for 10ns;

xin <= '1';

yin <= '1';
sin <= '1';
wait for 10ns;

xin <= '0';

yin <= '0';
sin <= '0';
wait for 10ns;

xin <= '1';

yin <= '1';
sin <= '0';
wait for 10ns;
 xin <= '0';
yin <= '0';
sin <= '1';
wait for 10ns;

xin <= '0';

yin <= '1';
sin <= '0';
wait for 10ns;

xin <= '1';

yin <= '1';
sin <= '0';
wait for 10ns;

xin <= '1';

yin <= '1';
sin <= '1';
wait for 10ns;

wait;

end process;

END df_tb_mux;

HASIL

ANALISIS

X y S M
0 0 0 0
1 0 0 1
0 1 0 0
 0 0 1 1
1 0 1 0
0 1 1 0
1 1 0 1
1 1 1 1

2.2 Multiplexer 2 input 1 output dua bit dengan model dataflow

Design.vhd
library IEEE;
use IEEE.std_logic_1164.all;

entity or_gate2 is port(

x : in std_logic_vector (1 downto 0);

y : in std_logic_vector (1 downto 0);
s : in std_logic;
m : out std_logic_vector (1 downto 0) );
end or_gate2;

architecture or2 of or_gate2 is

begin

m <= (x and (not s)) or (y and s);

end or2;

Testbench.vhd

library IEEE;
use IEEE.std_logic_1164.all;

entity or_gate2_tb is
end or_gate2_tb;

architecture tb of or_gate2_tb is

component or_gate2 is port(

x : in std_logic_vector (1 downto 0);
y : in std_logic_vector (1 downto 0);
s : in std_logic;
m : out std_logic_vector (1 downto 0)
);
end component;
 signal x_in : std_logic_vector(1 downto 0) := "00";
signal y_in : std_logic_vector(1 downto 0) := "00";
signal s_in : std_logic := '0';
signal m_out : std_logic_vector(1 downto 0);

begin

dut : or_gate2 PORT MAP(

x => x_in,
y => y_in,
s => s_in,
m => m_out
);

process

begin

wait for 10 ns; x_in <= "11"; s_in <= '0'; y_in <= "10";
wait for 10 ns; x_in <= "10"; s_in <= '1'; y_in <= "01";
wait for 10 ns; x_in <= "01"; s_in <= '0'; y_in <= "00";
wait for 10 ns; x_in <= "11"; s_in <= '1'; y_in <= "00";
wait for 10 ns; x_in <= "01"; s_in <= '1'; y_in <= "11";
wait for 10 ns; x_in <= "00"; s_in <= '0'; y_in <= "10";

wait;

end process;
end tb;

HASIL
ANALISIS

Tabel keluaran

x s Y m
00 0 00 00
11 0 10 11
10 1 01 01
01 0 00 01
11 1 00 00
01 1 11 11

3.1 Multiplexer 2 input 1 output dua bit dengan model struktural

Design.vhd

library IEEE;
use IEEE.std_logic_1164.all;

entity mux_1bit is port(

a: in std_logic;
b: in std_logic;
c: in std_logic;
d: out std_logic);
end mux_1bit;

architecture mux of mux_1bit is

begin
d<=((a and (not c)) or (b and c));
end mux;

library IEEE;
use IEEE.std_logic_1164.all;

entity muxfull is port (

x: in std_logic_vector(1 downto 0);
y: in std_logic_vector(1 downto 0);
s: in std_logic;
m: out std_logic_vector(1 downto 0));
end muxfull;
architecture structural of muxfull is
component mux_1bit port(
a,b,c: in std_logic;
d: out std_logic);
end component;

begin
mux_1: mux_1bit port map(
a => x(0),
b => y(0),
c => s,
d => m(0)
);
mux_2: mux_1bit port map(
a=> x(1),
b=> y(1),
c=> s,
d=> m(1)
);

end architecture structural;

Testbench.vhd
 library IEEE;
use IEEE.std_logic_1164.all;

Entity testbench is
end testbench;

Architecture multiplexer of testbench Is

Component muxfull
port (
x : in STD_LOGIC_VECTOR(1 downto 0);
y : in STD_LOGIC_VECTOR(1 downto 0);
s : in STD_LOGIC;
m : out STD_LOGIC_VECTOR(1 downto 0)
);
End Component;

Signal x_int : STD_LOGIC_VECTOR(1 downto 0) := "00";

Signal y_int : STD_LOGIC_VECTOR(1 downto 0) := "00";
Signal s_int : STD_LOGIC := '0';
Signal m_int : STD_LOGIC_VECTOR(1 downto 0) := "00";

begin
dut: muxfull PORT MAP (
x => x_int,
y => y_int,
s => s_int,
m => m_int );
process
begin
x_int <= "10"; y_int <= "01"; s_int <= '0'; wait for 10 ns;
x_int <= "11"; y_int <= "01"; s_int <= '1'; wait for 10 ns;
x_int <= "01"; y_int <= "00"; s_int <= '0'; wait for 10 ns;
x_int <= "00"; y_int <= "11"; s_int <= '1'; wait for 10 ns;
wait;
end process;
end multiplexer;

HASIL
 ANALISIS

Tabel keluaran

x S Y M
10 0 01 10
11 1 01 01
01 0 00 01
00 1 11 11

4.1 Multiplexer 2 input 1 output dengan model behavioral

Persamaan logika nya:

Jika s = 0 maka m = x
Jika s = 1 maka m = y

Tabel kebenaran:

x_in y_in S m
0 1 0 0
0 1 1 1

Design.vhd
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port( x, y, s : in std_logic;
m : out std_logic);
end mux;
architecture behavioral of mux is
begin
process (x, y, s) is
begin
if (s = '0') then
m <= x;
else
m<= y;
end if;
end process;
 end architecture behavioral;

Testbench.vhd

library IEEE;
use IEEE.std_logic_1164.all;

entity testbench is

end testbench;

architecture behavioral of testbench is

component mux is

port(

x: in std_logic;
y: in std_logic;
s: in std_logic;
m: out std_logic);
end component;

signal x_in, y_in, s_in, m_out: std_logic;

begin

DUT: mux port map(x_in, y_in, s_in, m_out);

Process
begin
x_in <= '0'; y_in <= '1'; s_in <= '0'; wait for 15 ns;
x_in <= '0'; y_in <= '1'; s_in <= '1'; wait for 15 ns;

wait;
end process;
end behavioral;

HASIL
ANALISIS

Tabel hasil keluaran

x Y S M
0 1 0 0
0 1 1 1

4.2 Multiplexer 2 input 1 output dua bit dengan model behavioral

Persamaan logikanya :

Jika s = 0 maka m = x
Jika s = 1 maka m = y

Tabel kebenarannya :

x_in y_in S m
00 01 0 00
11 10 1 10

Design.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port(
x : in std_logic_vector (1 downto 0);
y : in std_logic_vector (1 downto 0);
s : in std_logic;
m : out std_logic_vector (1 downto 0)
);
end mux;

architecture Behavioral of mux is

begin
process(x,y,s)
begin
if(s = '0') then
m(0) <= x(0);
m(1) <= x(1);
else
m(0) <= y(0);
 m(1) <= y(1);
end if;
end process;
end Behavioral;

Testbench.vhd

library IEEE;
use IEEE.std_logic_1164.all;

entity tb_mux is
end tb_mux;

architecture rpstb of tb_mux is

component mux is port(

x : in std_logic_vector (1 downto 0);

y : in std_logic_vector (1 downto 0);
s : in std_logic;
m : out std_logic_vector (1 downto 0)
);
end component;

signal x_in, y_in, m_out : std_logic_vector (1 downto 0);

signal s_in:std_logic;
begin
dut : mux PORT MAP(

x => x_in,
y => y_in,
s => s_in,
m => m_out
);

process

begin
x_in <= "00" ; y_in <= "00" ; s_in <= '0'; wait for 10ns;
x_in <= "01" ; y_in <= "00" ; s_in <= '0'; wait for 10ns;
x_in <= "01" ; y_in <= "01" ; s_in <= '0'; wait for 10ns;
x_in <= "10" ; y_in <= "00" ; s_in <= '0'; wait for 10ns;
x_in <= "10" ; y_in <= "10" ; s_in <= '0'; wait for 10ns;
x_in <= "11" ; y_in <= "10" ; s_in <= '0'; wait for 10ns;
x_in <= "01" ; y_in <= "00" ; s_in <= '1'; wait for 10ns;
x_in <= "00" ; y_in <= "01" ; s_in <= '1'; wait for 10ns;
x_in <= "11" ; y_in <= "10" ; s_in <= '1'; wait for 10ns;
x_in <= "11" ; y_in <= "11" ; s_in <= '1'; wait for 10ns;

wait;
end process;
end rpstb;
 HASIL

ANALISIS
Tabel hasil keluaran
x Y S m
00 00 0 00
01 00 0 01
01 01 0 01
10 00 0 10
10 10 0 10
11 10 0 11
01 00 1 00
00 01 1 01
11 10 1 10
11 11 1 11

5.1 Multiplexer 3 input 1 output dengan multiplexer 2 input 1 output

Tabel kebenaran

s0 s1 m
0 0 x
0 1 x
1 0 Y
1 0 Z

Design.vhd
library IEEE;
use IEEE.std_logic_1164.all;

entity mux is port(

a: in std_logic;
 b: in std_logic;
c: in std_logic;
d: out std_logic);
end mux;

architecture lab5_1 of mux is

begin
d<=((a and (not c)) or (b and c));
end lab5_1;

library IEEE;
use IEEE.std_logic_1164.all;
entity mux3to1 is port(
x, y, z, s0, s1 : in std_logic;
m : out std_logic);
end mux3to1;

architecture rps of mux3to1 is

component mux port(
a: in std_logic;
b: in std_logic;
c: in std_logic;
d: out std_logic);
end component;
signal d_int : std_logic;

begin
mux1 : mux port map(
a=>x,
b=>y,
c=>s0,
d=>d_int);
mux2 : mux port map(
a=>d_int,
b=>z,
c=>s1,
d=>m);
end architecture rps;

Testbench.vhd

library IEEE;
use IEEE.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavioral of testbench is

component mux3to1 is

port(
x: in std_logic;
y: in std_logic;
z: in std_logic;
s0: in std_logic;
 s1: in std_logic;
m: out std_logic);
end component;

signal x_in, y_in, z_in, s0_in, s1_in, m_out: std_logic;

begin

DUT: mux3to1 port map(x_in, y_in, z_in, s0_in,s1_in, m_out);

Process
begin
x_in <= '0'; y_in <= '0'; z_in <= '1'; s0_in <= '0'; s1_in <= '0';
wait for 15 ns;

x_in <= '0'; y_in <= '1'; z_in <= '0'; s0_in <= '0'; s1_in <= '1';
wait for 15 ns;

x_in <= '1'; y_in <= '0'; z_in <= '1'; s0_in <= '1'; s1_in <= '0';
wait for 15 ns;

x_in <= '1'; y_in <= '0'; z_in <= '1'; s0_in <= '1'; s1_in <= '1';
wait for 15 ns;

wait;
end process;
end behavioral;

HASIL

ANALISIS
Tabel hasil keluaran
x y z s0 s1 m
0 0 1 0 0 0
0 1 0 0 1 0
1 0 1 1 0 0
1 0 1 1 1 1