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JNTU ONLINE EXAMINATIONS [Mid 2 - ES]
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1. Which is interrupt-driven program?
a
a. getkey
ttaarr. tt
a. svnseg
a
seven- segment displays.
ISS b. inkey
c. sunkey
nnddIISS n IISS
b. lcdisp
dd
c. lcdisp2
n
d. lcdkey
..UUaa
2. Which is interrupt-driven program?
..UUaa d. svnseg3
13. In intelligent LCD display, D0 to D7 are located at
a. getkey
b. codekey
wwww wwww a. 1 to 7 pins
b. 7 to 14 pins
c. sunkey
d. lcdkey ww
3. The routine ___ constant scans a 10-key pad via
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d. 8 to 16 pins
14. The ___ display contains two internal byte-wide
ports 0 and 3. registers.
a. getkey a. seven segment display
.o rgg
b. inker
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c. codekey
o . oorgg
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b. intelligent LCD display
c. 4X4 display
ttaarr.
d. bigkey
ttaarr.
4. The program ____ uses both hardware timers, T0
d. 2X2 display
ta
t
15. ___ displays include incandescent and, more likely,
ISS and T1.

a. getkey
nnddIIS
S nn IISS
LED indicators.
d
d
a. single light
b. inker
c. codekey
..UUa
a ..UUaa b. double light
c. single character
d. bigkey
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5. The program _____ is interrupt-driven by a high-to-
wwww d. intelligent alphanumeric
16. ____ displays include numeric and alphanumeric
a. getkey
b. inker
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low transition on INTD.
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a. single light
b. dou7ble light
c. codekey c. single character
d. bigkey d. intelligent alphanumeric
rrgg
using to generate a periodic 2ms delay in an
.o o .oorrgg
6. The ___ program can scan an 8 X 8 keyboard matrix 17. _____ displays are equipped with a built-in
microcontroller.
ttaarr.
interrupt mode.
a. getkey
ttaarr. a. single light
t a
b. double light
t
ISS ISS ISS
b. inker c. single character
c. odekey
nndd I nndd I
d. intelligent alphanumeric
d. bigkey
..UUaa
7. The completely interrupt-driven small keyword
..UUaa
18. The program ___ displays sharacters found in
locations ch1 to ch4 on four common-cathode
example is
a. getkey
wwww wwww seven- segment displays.
a. svnseg
b. inker
c. codekey
d. bigkey
ww ww b. lcdisp
c. lcdisp2
d. svnseg3
8. The ___ works best when handling data in byte-sized 19. The program ____ is very cumbersome when many
packages. messages must be displayed.
a. 8031 a. svnseg
.oor
b. 8051
rgg .oorgg
r b. lcdisp
ttaarr.
c. 8071
d. 8081
ta
t arr. c. lcdisp2
t a
d. svnseg3
t
ISS S S
9. The ___ program canbe modified to use a timer to 20. 20 characters per line display can be possible in
nndd
bounce time and the ''all-up'' delay.IIS
generate associated with the key-down de
nnd II S
a. seven segment display
d
a. getkey
b. inker
..UUaa ..UUaa c. 4X4 display
d. 2X2 display
c. codekey
wwww wwww 21. Control sequence of D/A conversion is
d. bigkey
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10. A ____ keboard is interfaced with 8051
microcontroller.
ww a. CS then WR
b. WR then CS
c. CS then WR then RD
a. 16-key d. WR then RD
b. 32-key 22. Control sequence of A/D conversion is
c. 64-key a. CS then WR
.oorgg
d. 128-key
r . o
11. _____ displays commonly contain LED segments
orrgg b. WR then CS
c. CS then WR then RD
ttaarr.
arranged as an 8.
ta
t arr. tta
d. WR then RD
ISS S S
a. seven segment display 23. A/D conversion time is
c. 4X4 display
n
n d
dII S n
n d II S
a. 1 μs
d
b. 2 μs
d. 2X2 display
..UUaa
..UUa
a c. 3 μs
d. 4 μs
wwww
wwww 24. For a 1000-hertz wave, S could be ____ samples.
ww ww
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a. 50d 37. Reference voltage value in D/A conversion is a) b)
b. 100d c) d)
.oor
c. 150d
gg
r . oorgg
r a. ±8V
ttaarr.
d. 200d
25. D/A conversion time is
ttaarr. b. ±10V
c. ±12V
tta
ISS S S
a. 3 μs d. ±14V
b. 4 μs
c. 5 μs
nnddII S n d II S
38. A/D conversion time is
n d
a. 1 μs
d. 6 μs
..UUaa
26. The frequency of the counted pulse train is
..UUaa b. 2 μs
c. 3 μs
w ww
a. unknown frequency = counter / timer
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ww
b. unknown frequency = counter X timer
c. unknown frequency = counter - timer
d. unknown frequency = counter + timer
ww 39. In intelligent LCD display, D0 to D7 are located at
a. 1 to 7 pins
b. 7 to 14 pins
27. If the counter counts 200 pulses over an interval of c. 2 to 8 pins
0.1 second generated by the timer, the d. 8 to 16 pins
frequency is 40. _____ displays commonly contain LED segments
.oorgg
a. 200 Hz
r
b. 2000Hz
. oorgg
r arranged as an 8.
ttaarr.
c. 20000Hz
ttaarr. ta
t
ISS S S
d. 200000Hz c. 4X4 display
is
nnddIIS
28. The frequency of the pulse value in D/A conversion
nnd II S
d. 2X2 display
d
41. ____ is not suitable for the interchange of data
a. UF = 1 / (wave time high X 2)
..UU
b. UF = 1 / (wave time high + 2)a
a ..UUaa between 8051 microcontrollers.
a. mode 0
wwww
c. UF = 1 / (wave time high - 2)
wwww b. mode 1
a. ±8V
b. ±10V
ww
d. UF = 1 / (wave time high / 2)
29. Reference voltage value in D/A conversion is
ww c. mode 4
d. mode 3
42. Data transmission using modes 2 and 3 features
___ bits per character.
c. ±12V a. 8
d. ±14V b. 9
o
a. SAR
. orrgg
30. A/D converters use ____ types.
.oorrgg c. 10
d. 11
ttaarr.
b. flash
c. magnetic
ttaarr. 43. Which serial data communication mode is
tta
multiprocessor 9-bit UART?
ISS d. bubble
31. A/D converters use ____ types.
nnddIS
IS nn IS
IS
a. mode 0
dd
b. mode 1
a. SAR
b. flash
..UUaa ..UUaa c. mode 2
d. mode 4
c. magnetic
d. bubble
wwww wwww 44. Which serial data communication mode is standard
8-bit UART?
a. 50d
b. 100d
ww
32. For a 1000-hertz wave, S could be ____ samples.
ww a. mode 0
b. mode 1
c. mode 4
c. 150d d. mode 3
d. 200d 45. Which is used for time-sharing applications?
.o rrgg
o .oorgg
r
a. Star
b. loop
ttaarr.
seven- segment displays.
a. svnseg
ta
t arr. c. hybrid
t
d. bus
ta
ISS b. lcdisp
c. lcdisp2
nnddIS
IS nnddIS
I S
46. Which is used for data-gathering applications?
a. Star
d. svnseg3
. UUaa
34. The ___ display contains two internal byte-wide
. ..UUaa b. loop
c. hybrid
registers.
wwww wwww d. bus
47. The ___ is a good choice when the number of nodes
c. 4X4 display
d. 2X2 display
ww
ww is small.
a. Star
b. loop
35. The 8051 external input pin is c. hybrid
a. INT1 d. bus
b. DPH 48. Which serial data communication mode is standard
c. DPL
.oorgg
r . oorrgg 8-bit UART?
ttaarr.
d. IE
36. The 8051 external input pin is
ta
t arr. a. mode 0
t
b. mode 1
ta
ISS I SS I SS
a. INT0 c. mode 2
b. DPH
n
n d
d I n
n d
d I
d. mode 3
c. DPL
d. IE
..UUaa ..UUa
a
49. Which serial data communication mode is high
speed?
wwww wwww a. mode 0
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b. mode 1 61. A semaphore that does not specify the order in
c. mode 2 which processes are removed from the queue is
.oorgg
r
d. mode 3
. oorgg
r _____________
ttaarr.
register?
ttaarr.
50. Which serial data communication mode is 8-bit shift a. mutex
t
b. strong
ta
ISS S S
a. mode 0 c. counting
b. mode 1
c. mode 2
nnddII S n d II S
d. weak
n d
62. The process that has been blocked the longest is
d. mode 3
..UUaa
51. A standard for OS interfaces proposed by IEEE is
..UUaa released from the queue hint:
a. mutex
a. POSIX
wwww wwww b. strong
b. QNX
c. AMX
d. Intel
ww ww c. counting
d. weak
63. semaphores [c]
52. The basic building block of software written under a. are used to do I/O
an RTOS is the b. synchronize critical resources to present condition.
a. scheduler c. synchronize critical resources to present dead lock.
.oor
b. task
gg
r
c. context
. oorgg
r d. allow processes to communicate with one another.
64. The non-binary semaphore is often referred to as
ttaarr.
d. reentrancy
ttaarr. ta
________ semaphore
t
ISS S S
53. The ___ state means that this task has not got any a. mutex
thing to do right now, even if the
microprocessor become available.
nnddIIS nnd II S
b. strong
d
c. counting
a. running
b. ready
..UUa
a ..UUaa d. weak
65. Binary semaphore is also known as
c. blocked
wwww wwww a. General semaphore
d. suspended
nonatomic way.
a. mutex
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54. A _____ function may not use the hardware in a
ww b. Mutex
c. Cluster
d. Spooling
66. For both counting semaphores and binary
b. task semaphores, a _____ is used to hold processes waiting
c. reentrant on the semaphores.
o orrgg
d. semaphore
55. Under most RTOS a task is simply a _____.
. .oorrgg a. stack
b. queue
ttaarr.
a. routine
b. subroutine
ttaarr. c. dequeue
tta
d. circular queue
ISS c. interrupt
d. exception
nnddIS
IS nn IS
IS
67. ______ guarantee freedom from starvation.
dd
a. Strong semaphores
.. Uaa
56. A ____ RTOS will stop a lower-priority task as soon
U
as the higher-priority task unblocks.
..UUaa b. Weak semaphores
c. Delay semaphores
a. preemptive
b. non preemptive
wwww wwww d. Binary semaphores
68. The barbershop problem is an example of
c. interpret
d. exception ww
57. A_____ RTOS will only take the microprocessor
ww a. Deadlock
b. Starvation
c. Semaphore
away from the lower-priority task when that task d. Live lock
blocks. 69. In the producer/consumer problem, there are
.o rrgg
a. preemptive
b. non preemptive
o .oorgg
r
a. one or more producers and one or more consumers
b. single producer and single consumer
ttaarr.
c. interpret
d. exception
ta
t arr. c. single producer and one or more consumers
tta
d. one or more producers and single consumer
ISS ddISS
58. A function that works properly even if it is called by
I
more than one task is called a ____ function.
nn nnddIS
I S
70. A semaphore count of negative n means (s= -n)
that the queue contains waiting process. [b]
a. mutex
b. task
..UUaa ..UUaa a. n+1
b. n
c. reentrant
d. semaphore
wwww wwww c. n-1
d. 0
ww
59. The ____ state means that the microprocessor is
executing the instructions that make up this.
a. running
ww 71. ______ can be considered as an array of mailboxes
a. pipes
b. semaphore
b. ready c. timer
c. blocked d. message queue
d. suspended 72. In a time sharing operating system, when the time
.oorgg
r . oorrgg
60. The ___ state means that some other task is in the slot given to a process is completed , the
ttaarr. ta arr.
running state but that this task ha things that
it could do if the microprocessor becomes available.
t
process goes from the RUNNING state of the
t a
a. BLOCKED state
t
ISS I SS I SS
a. running b. READY state
b. ready
n
n d
d I n
n d
d I
c. SUSPENDED state
c. blocked
d. suspended
..UUaa ..UUa
a
d. TERMINATE state
73. a mutex can be
wwww wwww a. locked state
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b. unlocked state a. EDORAM
c. either in locked state or unlocked state b. Rambus DRAM
.oorgg
r
d. neither in locked state nor unlocked state
. oorgg
r c. SDRAM
ttaarr.
74. A task owning a mutex, can not be ______
a. added
ttaarr. d. FPMDRAM
t a
86. ______ are used to measure the elapsed time of
t
ISS S S
b. modified events
c. released
d. deleted
nnddII S n d II S
a. timers
n d
b. counters
a. pipes
..UUaa
75. Array of mailboxes can be considered as
..UUaa c. schedulers
d. processes
b. semaphore
wwww wwww 87. A _____ is an extremely common peripheral
c. timer
d. message queue
76. Mutex stands for
ww ww devises that can measure time intervals
a. counters
b. timers
a. mutual text c. schedulers
b. mutual exclusion d. process
c. mutual task 88. To use a _______ , we must configure its inputs
.oorgg
d. mutual timer
r . oorgg
r
77. ________ occurs when two or more tasks wait for a
and monitors its outputs
a. counters
ttaarr.
resource being held by another task
ttaarr. ta
b. timers
t
ISS S S
a. deadlock c. schedulers
b. live lock
c. semaphore
nnddIIS nnd II S
d. process
d
89. A ______ timer is an application that measures the
d. starvation
..UUa
a
78. Mutual exclusion problem occurs between
..UUaa time a person takes to respond to a visual or
audio stimulus
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a. two disjoin process that do not interact
wwww a. watchdog
ww
b. processes that share resources
c. processes that do not use the same resource
d. processes have priority
79. What problem is solved by dijkstra�s bankers
ww b. special
c. reaction
d. proactive
90. System's _____ interrupt response time has to be
algoritham? considered while evaluating the performance
a. mutual exclusion of an operating system embedded software
o orrgg
b. deadlock recovery
c. deadlock avoidance
. .oorrgg a. best-case
b. worst-case
ttaarr.
d. cache coherence
80. Mutex is a special
ttaarr. c. average-case
tta
d. all cases
ISS a. count semaphore

b. binary semaphore
nnddIS
IS nn IS
IS
91. ISR stands for
dd
a. Interface service routine
c. task semaphore
d. time semaphore
..UUaa ..UUaa b. Interrupt Service Runner
c. Interrupt Service Routine
www
81. A common use of ____ is to serve as the program
w
memory for a micro processor
wwww d. Interface Standard Routine
92. When a process makes a system call, its mode
a. ROM
b. EPROM
c. EEPROM
ww ww change from
a. user to kernel
b. kernel to user
d. Flash memory c. restricted to process
82. to obtain better memory utilization dynamic loading d. unrestricted to restricted
.oorrgg
ids used with dynamic loading a routine is
.o rgg
r
not loaded until it is called for implementing dynamic
o
93. The technique that allows only one user to work
with a file at a particular time is called
ttaarr.
loading
ta
t a
a. special support from hardware is essentialrr. a. semaphore
tta
b. critical region
ISS ddISS
b. special support from operating system is essential
I
c. special support from both hardware and operating system
nn nnddIS
I S
c. locking
d. dedicated mode
are essential
. UUaa
d. user programs can implement dynamic loading
. ..UUaa 94. _____ is a hardware signal that informs the CPU

that an important event has occurred
system or the hardware

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without any special support from the operating
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b. signal
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83. One common use of a ______ timer is to enable an
embedded system to restart itself in case of a
failure
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d. interrupt
95. When interrupt occurs , CPU saves its context and
a. watchdog jumps to the _______
b. special a. ISR
c. reaction b. API
.oorgg
r
d. proactive
. oorrgg c. IP
ttaarr.
84. ______ is an extension of EEPROM
a. RAM
ta
t arr. d. ITS
t a
96. The maximum time for which interrupts are
t
ISS I SS I SS
b. SRAM disables + time to start the execution of the first
c. Flash memory
n
n d
d I n
n d
d I
instruction in the ISR is called_______
d. DRAM
U aa
85. ____ is really more of a bus interface architecture
.. U ..UUa
a
a. Interrupt response time
b. Interrupt recovery time
the DRAM architecture
wwww wwww c. Interrupt latency
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d. Interrupt handler 109. The _____ stores the status and uses it when
97. Time between receipt of interrupt signal and responding to later status request from the
.oorgg
r
starting the code that handles the interrupt is
. oorgg
r network.
ttaarr.
called_____
ttaarr. a. DTP protocol task
t a
b. ADSP protocol task
t
ISS S S
b. Interrupt recovery time c. serial port task
c. Interrupt latency
d. Interrupt handler
nnddII S d II S
d. Interrupt routine
nn d
110. For both counting semaphore and binary
..UUaa
98. Time required for CPU to return to the interrupted
code/ highest priority task is called
..UUaasemaphore a ___ is used to hold processing waiting on
the semaphores
w
www wwww a. stack
c. Interrupt latency
d. Interrupt handler
ww
b. Interrupt recovery time
ww b. queue
c. dequeue
d. circular queue
99. In a preemptive kernel , response time = 111. the barber problem is an example of
a. Interrupt recovery time + time to save CPU registers a. dead lock
context b. starvation
.oor
contextgg . oorgg
b. Interrupt respond time + time to save CPU registers
r r c. semaphore
d. live lock
ttaarr. ttaarr.
c. Interrupt handler + time to save CPU registers context
ta
112. Binary semaphore will take the values of _______
t
ISS S S
d. Interrupt latency + time to save CPU registers a. 0
context
100. Principle of RTOS is
nnddIIS n d I
b. 1
nd I S
c. Either 0 or 1
a. write short interrupt routines
..UUa
a
b. you do not need tasks for priority
..UUaa d. Neither 0 nor 1
113. To access a shared resource , there should be a
wwww
c. you need tasks for inheritance
wwww mechanism so that there is discipline . this is
cuts throughput.
a. time-slicing
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d. consider turning time-slicing off
101. _____ causes more task switched and therefore
ww known as ____ synchronization
a. resource
b. task
c. shared
b. encapsulation d. write
c. priority 114. Binary semaphore is also known as
o orrgg
d. routines
. .oorrgg a. general semaphore
b. mutex
ttaarr.
b. you do not need tasks for priority
ttaarr. c. cluster
tta
d. spooling
ISS c. you need tasks for inheritance

d. consider turning time-slicing on
nnddIS
IS n IS
IS
115. counting semaphore will have an integer value
dd
greater than ______
n
..UU
a. write short interrupt routinesaa ..UUaa a. 0
b. 1
www
b. you need tasks for priority
w
c. you need tasks for inheritance
wwww c. 2
d. 3
ww
ww 116. If an 8 � bit integer is used for implementing a
counting a semaphore , the semaphore can take a
value between ___ and ______
b. you do not need tasks for priority a. 0 and 255
c. you need tasks for encapsulation b. 0 and 65,535
.o rrgg
105. ______ determines if frame is addressed to
o .oorgg
r
c. 0 and 127
d. 0 and 63
ttaarr.
telegraph.
a. DTP protocol task
ta
t arr. 117. In order to allow only one process to enter its
tta
critical section binary semaphore are initialized to
ISS b. ADSP protocol task

c. serial port task
nnddIS
IS nnddIS
a. 0
I
b. 1 S
. UUaa
106. ______ determines if frame is print data, status
. ..UUaa c. 2
d. 3
request, etc.
wwww wwww 118. What is the initial value of the semaphore to allow
only one of the many process to enter their
c. serial port task
ww ww critical section
a. 0
b. 1
107. ______ determines if serial data contains new c. 2
status. d. 3
a. DTP protocol task 119. Semaphore are used to solve the problem of
.oorgg
r
. oorrgg a. rare condition
ttaarr.
c. serial port task
ta
t arr. b. process asynchronization
t a
c. mutual exclusion
t
ISS I SS I SS
108. ______ receives network frame or serial data. d. compilation
n
n d
d I d
d I
120. A ______ mechanism is used to get your software
n
n
c. serial port task
..UUaa ..UUa
a
into your target for debugging purposes.
a. shared memory
wwww wwww b. virtual memory
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c. secondary memory c. state mode
d. overlay memory d. monitors
.oorgg
r
121. A program that resides in the target ROM is
. oorgg
r 133. RISC stands for
ttaarr.
a. loader
b. compiler
ttaarr. a. Reduced Instruction Set Computer
t a
b. Reverse Instruction Set Computer
t
ISS S S
c. monitor c. Run Instruction Set Computer
d. linker
nnddII S
122. You should encapsulate semaphores, queues, and
n d II S
d. Range Instruction Set Computer
n d
134. A _____ can capture one-time events.
..UUaa
so on, in ____ modules so that the input
between modules is a function call.
..UUaa a. oscilloscope
b. multimeter
a. 3
wwww wwww c. storage scope
b. 2
c. 1
d. 4
ww ww d. ohm meter
135. The goal of typical testing process is
a. find the bugs lately
123. A device that replaces the ROM in the target b. exercise some code
system is c. develop reusable, repeatable tests
a. PROM d. keep audit trail of test
.oorgg
b. ROM emulators
r
c. In-circuit emulator
. oorgg
r 136. Simulator disadvantage is
a. testing assembly-language code
ttaarr.
d. flash
ttaarr. ta
b. resolving probability issues
t
ISS S S
124. A common feature of in-circuit emulator is c. shared-data bugs
a. shared memory
b. virtual memory
nnddIIS nnd II S
d. determine response and through put
d
137. An oscilloscope is
c. secondary memory
d. overlay memory
..UUa
a ..UUaa a. analog device
b. digital device
wwww
125. A _____ understands the same C language as a
wwww c. converter
native compiler.
a. cross-compiler
b. cross-assembler
c. linker/loader
ww ww d. detector
138. ______ captures data without reference to any
events on the circuit it is examining.
a. self-collected
d. re-compiler b. clock
126. A _____ understands as assembly language that is c. state mode
o orrgg
specific to your target microprocessor.
a. cross-compiler
. .oorrgg d. monitors
139. In _____ a logic analyzer can capture traces.
ttaarr.
b. cross-assembler
c. linker/loader
ttaarr. a. self-collected
tta
b. clock
ISS d. re-compiler
n ddIS
IS
127. A _____ combines separately compiled and
n nn IS
IS
c. state mode
dd
d. monitors
a. cross-compiler
.. Uaa
assembly modules into an executable image.
U ..UUaa 140. For both counting semaphores and binary

semaphores, a _____ is used to hold processes waiting
b. cross-assembler
c. linker/loader
wwww wwww on the semaphores.
a. stack
d. re-compiler
ww
128. Linker/locators use _____ to decide where to put
different parts of the code and data.
ww b. queue
c. dequeue
d. circular queue
a. cross-compiler 141. ______ guarantees freedom from starvation.
b. cross-assembler a. Strong semaphores
.o rrgg
c. tool design
d. segments
o .oorgg
r
b. Weak semaphores
c. Delay semaphores
ttaarr. ta
t arr.
129. One way to save data space in an embedded
system that uses an RTOS is to make your tasks
d. Binary semaphores
tta
142. ______ is used for measuring resistance.
ISS a. stacks
nnddI
____ only as large as they need to be.
S
IS nnddIS
I S
a. oscilloscope
b. emulator
b. queue
c. lists
..UUaa ..UUaa c. ohm meter
d. multimeter
d. records
wwww
130. ______ captures data without reference to any
wwww 143. Voltmeter is used for
a. clock differences
a. self-collected
b. clock
ww
events on the circuit it is examining.
ww b. voltage differences
c. resistance differences
d. Delay differences
c. other hardware 144. Binary semaphore is also known as
d. monitors a. General semaphore
131. The goal of typical testing process is b. Mutex
.oorgg
r
a. find the bugs lately
. oorrgg c. Cluster
ttaarr.
b. exercise all code
c. develop reusable, repeatable tests
ta
t arr. d. Spooling
t a
145. BDM stands for
t
ISS I SS I SS
d. keep audit trail of test a. Background Debug Monitor
d
d I
132. _____ use a combination of software and
n
n n
n d
d I
b. Backend Debug Monitor
a. self-collected
..UUa
hardware to give you standard debugging capabilities.
a ..UUa
a
c. Based Debug Monitor
d. Bound Debug Monitor
b. clock
wwww wwww 146. ICE stands for
ww ww
www . www .
www www
a. In-Circuit Emulator d. TEQ
b. In-Circuit Entrance 160. ARM load-store instruction is
.oorgg
r
c. Extractor In-Circuit
. oorgg
r a. CMP
ttaarr.
d. In-Circuit Enabled
147. Merit of simulator is
ttaarr. b. MOV
c. CMN
tta
ISS S S
a. shared-data bugs d. ADR
b. other hardware
c. solving portability issues
nnddII S n d II S
161. The ____ operation is used for iterative
n d
algorithms.
..UUa
d. testing assembly language code
a
148. _____ will work with any microprocessor.
..UUaa a. MODE1
b. RECIPS
a. emulators
wwww wwww c. STKY
b. logic analyzers
c. oscilloscope
d. monitors
ww ww d. SCALB
162. The routing models used for floating-point
arithmetic are controlled by two bits in the ___region.
149. Analog device is a. MODE1
a. oscilloscope b. MODE2
b. emulator c. STKY
.oorgg
c. ohm meter
r
d. multimeter
. oorgg
r d. SCALB
163. The SHARC ___ instruction provides procedure
ttaarr.
150. ''Overflow'' condition code in ARM is
ttaarr. ta
calls. a) b) c) d)
t
ISS S S
a. VC a. JUMP
b. VS
c. EQ
nnddIIS nnd II S
b. CALL
d
c. SEND
d. EZ
..UUa
a
151. ''Equals zero'' condition code in ARM is
..UUaa d. PROC
164. The _____ bits are set along with the ASTAT
a. VC
wwww wwww register bits, but are not cleared.
b. VS
c. EQ
d. EZ
ww ww
152. In ____, the value stored in the register is used as
a. MODE1
b. MODE2
c. STKY
d. SCALB
the address to be fetched from memory. 165. The _____ operation adds an integer value to the
a. Register-indirect addressing exponent of a floating-point operand.
o orrgg
b. Direct addressing
c. Indirect addressing
. .oorrgg a. MODE1
b. MODE2
ttaarr.
d. Register-direct addressing
ttaarr.
153. In ____, the value stored in the register is used as
c. STKY
tta
d. SCALB
ISS the address to be fetched from memory.

a. Register-indirect addressing
nnddIS
IS nn IS
IS
166. A SHARC instruction consists of _____ bits
dd
a. 32
b. Direct addressing
c. Indirect addressing
..UUaa ..UUaa b. 48
c. 16
www
d. Register-direct addressing
w
154. ARM has ____ general-purpose registers.
wwww d. 8
167. The SHARC member is internally organized as
a. 6
b. 8
c. 12
ww ww _____ bit works.
a. 32
b. 48
d. 16 c. 16
155. The ____ instruction is the basic mechanism is d. 8
a. A
.oorrgg
ARM for changing the flow of control.
.oorgg
r
168. The SHARC has _____ data address generators.
a. 5
ttaarr.
b. B
c. C
ta
t arr. b. 4
c. 3
tta
ISS d. D
ddIS
IS
156. ARM is actually a family of ____ architectures.
nn nnddIS
d. 2
I S
169. The _____ instruction is the basic mechanism for
a. RISC
b. CISC
..UUaa ..UUaa changing the flow of control in the SHARC.
a. JNZ
c. RISK
d. CISK
wwww wwww b. JMP
c. JUMP
a. 8
b. 16
ww
157. The standard ARM word is ____ bits length.
ww d. JNN
170. What does the SHARC CLIP instruction do?
a. sets range
c. 32 b. finds maximum
d. 64 c. absolute value
158. ARM comparison instruction is d. compare
a. MOV
.oorgg
r . oorrgg 171. The address _____ is reserved for the extended
ttaarr.
b. MVN
c. LDR
ta
t arr. 10-bit addressing scheme in I2C.
t a
a. 11100XX
t
ISS I SS I SS
d. TST b. 11111XX
159. ARM comparison instruction is
n
n d
d I n
n d
d I
c. 11110XX
a. MOV
b. MVN
..UUaa ..UUa
a
d. 11000XX
172. The _____ bus has been used to support many
c. LDR
wwww wwww I/O cards for PC-based embedded systems.
ww ww
www . www .
www www
a. I2C b. 14
b. PCI c. 15
c. ISA
.oorgg
r . oorgg
r d. 12
ttaarr.
d. VME
173. SDL stands for
ttaarr. 186. CAN bus stand for
t a
a. Controller Area Network
t
ISS S S
a. Serial discrete line b. Converter Area Network
b. serial deliver line
c. serial divide line
nnddII S n d II S
c. Connection Area Network
n d
d. Coded Area Network
d. serial data line
..UUaa
174. ______ encourages a data-push programming
..UUaa 187. The ____ bus was developed for automotive
electronics.
style.
wwww wwww a. I2C
a. I2C
b. CAT
c. LON
ww ww b. CAN
c. LON
d. DSP
d. DSP 188. The ____ network was developed for home and
175. The address _____ is used to signal a general call industrial automation.
in I2C. a. I2C
.oorgg
a. 00000
r
b. 0000000
. oorgg
r b. CAN
c. Echelon LON
ttaarr.
c. 0000
ttaarr. d. DSP
ta
t
ISS S S
d. 000 189. The _____ bus uses bit-serial transmission.
systems.
nnddIIS
176. The ____ bus is used in microcontroller-based
nnd II S
a. I2C
d
b. CAN
a. I2C
b. CAN
..UUa
a ..UUaa c. Echelon LON
d. DSP
c. LON
wwww wwww 190. Control of the _____bus is arbitrated using
d. DSP
ww
177. The ____ bus is a well-known as commonly used
to link microcontrollers in to systems.
a. I2C
ww CSMA/AMP.
a. I2C
b. CAN
c. Echelon LON
b. CAN d. DSP
c. LON 191. ______ is used for network management services.
d. DSP
o orrgg oorrgg
178. The _____ bus is designed as a multimaster bus.
. .
a. TCP
b. IP
ttaarr.
a. I2C
b. Can
ttaarr. c. HTTP
t
d. UDP
ta
ISS c. LON
d. DSP
nnddIS
IS nn IS
IS
192. TCP stands for
dd
a. Transmission Condition Protocol
MPEG-2 video chip.

.. Uaa
179. Which is used for the command interface in an
U ..UUaa b. Transmission Control Protocol

c. Transmission Cancel Protocol
a. I2C
b. Can
wwww wwww d. Transmission Cooperative Protocol
193. The simplest way to test the controllers to build
c. LON
d. DSP
180. SCL stands for
ww ww an elevator simulator using an ______ .
a. APGA
b. CPGA
a. Serial Command Line c. EPGA
b. Series Clock Line d. FPGA
.o rrgg
c. Serial Clock Line
d. Send Clock Line
o .oorgg
r
194. The IP address is typically written in the form
a. XXX.XX.XX.XX
ttaarr.
a. 13
ta
t arr.
181. CRC field length in the CAN bus is ____ bits. b. XXX.XX.XX.XXX
tta
c. XX.XX.XX.XX
ISS b. 14
c. 15
nnddIS
IS nnddIS
I S
d. XX.X.XX.XX
195. ______ creates packets for routing to the
d. 16
. UUaa
182. Data field length in the CAN bus is ___ bits.
. ..UUaa destination.
a. TCP
a. 0-28
b. 0-16
wwww wwww b. IP
c. HTTP
c. 0-64
d. 0-128 ww
183. _____ is a synchronous bus.
ww d. SMTP
196. A node that transmits data among different types
of networks is known as a _____ .
a. I2C a. router
b. CAN b. linker
c. Echelon LON c. receiver
d. DSP
.oorgg
r . oorrgg d. layer
ttaarr.
184. CRC stands for
a. Cyclic Removal Code
ta
t arr. 197. DNS stands for
t a
a. Domain Name Source
t
ISS I SS I SS
b. Cyclic Remote Code b. Domain Name Server
c. Cyclic Redundancy Code
n
n d
d I n
n d
d I
c. Domain Name Service
d. Cyclic Ready Code
U aa
185. An arbitration field in the CAN bus is ___ bits.
.. U ..UUa
a
d. Domain Name Sender
198. Using IP as the foundation, TCP is used to provide
a. 13
wwww wwww ____ for batch file transfers.
ww ww
www . www .
www www
a. HTTP
b. SMTP
c. FTP
.oorgg
r . oorgg
r
ttaarr.
d. SNMP
t aarr.
t tta
ISS S S
______ for World Wide Web service.
a. HTTP
b. SMTP
nnddII S nnddII S
c. FTP
d. SNMP
..UUaa ..UUaa
w ww
w wwww
______ for email.
a. HTTP
b. SMTP
ww ww
c. FTP
d. SNMP
.oorgg
r . oorgg
r
ttaarr. ttaarr. ta
t
ISS nnddIIS
S nnd
d IISS
..UUa
a ..UUaa
wwww wwww
ww ww
.o orrgg .oorrgg
ttaarr. ttaarr. tta
ISS nnddIS
IS nnddIS
IS
..UUaa ..UUaa
wwww wwww
ww ww
.oorrgg .oorgg
r
ttaarr. ta
t arr. tta
ISS nnddIS
IS nnddIS
I S
..UUaa ..UUaa
wwww wwww
ww ww
.oorgg
r . oorrgg
ttaarr. ta
t arr. tta
ISS n
n d
dIISS n
n d
d IISS
..UUaa ..UUa
a
wwww wwww
ww ww

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www . www .

ISS and T1.

wwww 24. For a 1000-hertz wave, S could be ____ samples.

wwww wwww a. mode 0

wwww wwww a. locked state

ISS a. count semaphore

. ..UUaa 94. _____ is a hardware signal that informs the CPU

system or the hardware

wwww wwww c. Interrupt latency

www wwww a. stack

ISS c. you need tasks for inheritance

ISS b. ADSP protocol task

. oorrgg a. rare condition

wwww wwww b. virtual memory

U ..UUaa 140. For both counting semaphores and binary

wwww wwww 146. ICE stands for

ISS the address to be fetched from memory.

wwww wwww I/O cards for PC-based embedded systems.

MPEG-2 video chip.

U ..UUaa b. Transmission Control Protocol

wwww wwww ____ for batch file transfers.

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