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3.analysis of Class B Amplifiers
3.analysis of Class B Amplifiers
● The push-pull circuit requires two transformers, one as input transformer called driver
transformer. Both transformers are center-tapped, as shown in Figure 4.
● In the circuit, both Q1 and Q2 transistors are of NPN type
● The circuit can use both Q1 and Q2 as p-n-p type (change Vcc to be negative)
● The driver transformer drives the circuit
● The input signal is applied to the primary of the driver transformer
● The center tap of the secondary of the driver transformer is grounded
● The center tap on the primary of the output transformer is connected to supply voltage
+Vcc
● w.r.t the center tap, for a positive half cycle of the input signal, the point A shown on the
secondary of driver transformer will be positive while the point B will be negative
● Thus the voltage in the two halves of the secondary of the driver transformer will be
equal but with opposite polarity
● Hence the input signals applied to the base of the transistors Q1 and Q2 will be 180 ° out
of phase
● The transistor Q1 conducts during the positive cycle of the input producing a positive half
cycle across the load. Transistor Q2 conducts during the negative half cycle of the input,
producing a negative half cycle across the load. Thus, we get a full cycle for a full input
cycle across the load, as shown in figure 5.
+Vcc
I1
A Q1
ib1 iL
N1
Vi N2
N1 Load, RL
Driver ib2
Transformer Q2
B
I2
Push Pull
Output
Circuit
Transformer
Figure 4: Push-pull class B amplifier
Figure 5: Basic push-pull operation
● When point A is positive, Q1 gets driven into the active region while Q2 is in the cut-off
region. When point A is negative, point B is positive, and the transistor Q2 gets driven
into an active region while Q1 is in the cut-off region.
Note: For the output transformer, the number of turns of each half of the primary is N1, while the
number of turns in the secondary is N2. Hence the total number of turns in the primary is 2N1.
So the turns ratio of the output transformer is specified as 2N1:N2.
DC OPERATION
● The dc biasing point, i.e., Q point, is adjusted on the x-axis such that V CEQ =V cc and I CQ is
zero. Hence the co-ordinate of the Q-point is ( V cc , 0 ). There is no dc base bias current.
DC Power Input
● Each transistor output is in the form of a half rectified waveform. Hence if I m is the peak
Im
value of the output current of each transistor, the dc or average value is due to the half
π
rectified waveform. The two currents drawn by the two transistors from the dc supply are
in the same direction. Hence the dc or average current drawn from the supply is the
algebraic sum of the individual average current drawn by each transistor.
Im I m Im
∴ I dc = + =2
π π π
● The total d.c power input is given by:
Pdc =V cc × I dc
I m V cc
∴ P dc=2
π
AC OPERATION
● When the ac signal is applied to the driver transformer, during the positive half cycle, Q1
conducts. The path of the current drawn is shown in Figure 6.
o
● Figure 6: Q1 conduction
● For the negative half cycle, Q2 conducts. The path of the current drawn by Q2 is shown
in Figure 7.
Figure 7: Q2 conduction
● When Q1 conducts, the lower half of the primary does not carry any current. Hence only
N1 number of turns carry the current.
● When Q2 conducts, the upper half of the primary does not carry any current hence only
N1 number of turns carry the current. Hence the reflected load on the primary can be
written as:
RL N2
o R'L= 2
wheren=
n N1
NB: The step-down transformer turns ratio is 2N1:N2, but when calculating the reflected
load, the turns ratio becomes N 2/ N 1. So each transistor shares an equal load which is the
reflected load R'L
−1
● The slope of the ac load line is while the dc load line is a vertical line passing
R'L
through the operating Q on the x-axis, as shown in Figure 8.
o
Figure 8: Load lines for class B push pull amplifier
● The slope of the ac load line can be represented in terms of V m and I m as:
1 Im
'
=
RL V m
' Vm
∴ R L= where I m is peak value of collector current
Im
AC Power Output
● As V m and I m are the peak values of the output voltage and output current respectively,
then:
Vm
V rms =
√❑
● Hence the a.c output power is expressed as:
Pac =V rms I rms
2 ' V rms 2
∴ P ac=I rms R = '
L
RL
Efficiency
I 2m R'L
P
η= ac ×100=
Pdc
2
( )
2 I m V cc
π
× 100 %
I m π R'L
η= × 100 %
4 V cc
Vmπ
η= × 100 %
4 V cc
Power Dissipation
Pd =Pdc −Pac
I m V cc V rms 2
Pd =2 − '
π RL
1 Im
but, '
=
RL V m
also
Vm
V rms =
√❑
2 V cc V m V m2
∴ P d= '
− '
π RL 2 RL
Maximum Dissipation
● This is obtained by differentiating the Pd equation w.r.t V m and equating it to zero.
dP 2V cc 2 V m
⟹ = − =0
d V m π R 'L 2 R'L
2V cc Vm
'
=
πR L R'L
2V cc
∴ V m= →This isthe condition for maximum power dissipation
π
● Hence the maximum power dissipation is
2
2 V cc 2 V cc 1 2 V cc
( Pd )max =
π RL
'
×
π
− ' ×
2 RL π ( )
4 V cc2 2V cc2
¿ 2 '
− 2 '
π RL π RL
2V cc2
∴ ( Pd ) max= 2 '
π RL
NB: For maximum efficiency, V m =V cc hence the power dissipation is not maximum when the
efficiency is maximum. And when power dissipation is maximum, efficiency is not maximum.
Therefore maximum dissipation and maximum efficiency do not occur simultaneously in case of
class B amplifiers.
Now
V m2
∴ P ac= '
2 RL
and
Hence,
V cc 2
( Pac )max = '
2 RL
2 V cc2 2
4 V cc
( Pd )max = 2 ' = 2
π RL π 2 R'L ( )
2V cc 2 4
∴ ( Pd ) max= = ( Pac )max
π 2 R'L π 2
This much power is dissipated by both the transistors hence the maximum power dissipation per
transistor is: ( Pd )max /2.
4
( Pac )max
π2
⇒ ( P d )max =
2
2
∴ ( Pd ) max per transistor= ( Pac )max
π2
{ This forms the power rating of a transistor ¿be used ∈ push pull configuration }
e.g., if 10W maximum power is to be supplied to the load, then power dissipation of each
transistor should be:
2
×10=2.02 W
π2
Example:
Prove that in the case of push-pull class B amplifier, the efficiency at the time of maximum
power dissipation is 50 %
Solution:
2 V cc
V m=
π
VmIm
Pac =
2
Pac at maximum power dissipation:
2 V cc I m V cc I m
Pac = =
π 2 π
2V cc I m
Pdc =
π
Hence:
V cc I m
P π
η= ac ×100= ×100 %=50 %
Pdc 2 V cc I m
π
Determine the maximum efficiency:
Soln:
Therefore:
V cc 2
Pac =
2 R'L
2V cc I m
Pdc =
π
but
1 I
'
= m
RL V m
2 V m V cc 2 V cc2
∴ P dc= '
= '
π RL π RL
V cc 2
Pac 2 R'L π
η= ×100= 2
= ×100=78.5 %
Pdc 2 V cc 4
π R'L
● Let the input base current be sinusoidal in nature and given by:
i b =I Bm cosωt and i b =−I Bm cosωt=I Bm cos ( ωt + π )
1 2
The negative indicates that the two currents are 180° out of phase
● if we take higher order harmonics (i.e. the non-linearity of the transistor is a power series
function)
i 1=I c + B0 + B1 cosωt +B 2 cos 2 ωt + B3 cos 3 ωt +…
From this expression, we see that even harmonics get canceled; only odd harmonics are present.
Even Harmonics are suppressed if we use two transistors in a push-pull configuration.
Solution
N2 1
R L=12Ω ; n= = =0.333 ; η=78.5
N1 3
' RL
RL = =108 Ω
n2
For ( P ac )max , V m =V cc
V cc2 1 20 2
∴ ( Pac ) max= ' =
2 R L 2 108 ( )
=1.8518 W
2 2
( Pd )max per transistor = P
2 ( ac )max
= 2 ×1.8518=0.3752W
π π
V m Im
( Pac )max =
2
V m =V cc ∧I m=( I c )max
20 ( I c )max
∴ 1.8518=
2
( I c )max =0.1851 A
( I c )max
( I b )max = h =7.407 mA
fe
Example:
A class B push pull amplifier drives a load of 16 Ω connected to the secondary of an ideal
transformer. The supply voltage is 25V. If the number of turns on the primary is 200 and the
number of turns on the secondary is 50, calculate maximum power output, dc power input,
efficiency and maximum power dissipation per transistor.
N 2 50
R L=16 Ω; n= = =0.5 ;
N 1 100
' RL
RL = =64 Ω
n2
maximum power output
V cc 2 1 252
( Pac )max = =
2 R'L 2 64 ( )
=4.8828 W
I m V cc
Pdc =2
π
Vm
=R'L∧V m =V cc
Im
V cc 25
I m= '
= =0.3906
R L
64
dc power input
0.3906 × 25
Pdc =2 =6.2169 W
π
Efficiency
Pac 4.8828
η= ×100= × 100=78.5 %
Pdc 6.2169
The configuration employs one NPN and one PNP transistor and requires no center tap
transformers.
The circuit is driven from a dual supply of ± V cc. Q1 is n-p-n and Q2 p-n-p type
In the positive half cycle of the input signal, the transistor Q1 gets driven into the active region
and starts conducting. The same signal gets applied to the base of Q2 but remains off condition
during the positive half-cycle as it is a complementary type. This results in a positive half cycle
across the load R L.
During the negative cycle of the signal, the transistor Q2 being p-n-p gets biased into conduction,
while Q1 is driven into cut-off. This results in a negative half cycle across the load R L.
Example:
A complementary push-pull amp has a capacitive coupled load R L=8 Ω, supply voltage ± 12V .
Calculate:
i) ( Pac )max
ii) P D of each transistor
iii) Efficiency
Solution:
V 2cc 122
( Pac )max = =
2 R L 2× 8
=9 W
P D=P DC −Pac
P DC =V cc I DC
2 Im
but I DC =
π
P DC =V cc ( 2πI )
m
but
Vm
R L=
Im
Vm
hence I m = ∧V m=V cc
RL
2V cc ( 12 )2 ×2
P DC =V cc ( )
π RL
=
8π
=11.4591 W
P D=P DC −Pac
∴ P D =11.4591−9=2.4591 W
2.4591W
P D per transistor= =1.2295W
2
Pac
η= ×100=78.5 %
P DC
Example:
A complementary symmetry push-pull amplifier is operated using ± 10V and delivers power to a
load R L=5 Ω
Calculate:
i) maximum output power
ii) The power rating of the transistor
iii) DC input power for maximum output power
Solution:
V cc =±10 V ; R L =5 Ω
V 2cc 10 2
( Pac )max = 2 R = 2× 5 =10 W
L
2
For ( P D )max ,V m = V cc =6.3632 V
π
but
Vm
R L=
Im
V m 6.3662
∴ I m= = =1.2732 A
RL 5
P DC =V cc ( 2πI )= 10 × 2×1.2732
m
π
=8.1056W
V m I m 6.3662× 1.2732
Pac = = =4.0527 W
2 2
2 I m 10 × 2× 2
P DC =V cc ( )
π
=
π
=12.7323 W
Comparison of Push-Pull and Complementary Symmetry Circuits
One main fundamental problem with push-pull amplifiers is that the two transistors do not
combine fully at the output of both halves of the waveform due to their unique zero cut-off
biasing arrangement. As this problem occurs when the signal changes or “crosses over” from one
transistor to the other at the zero voltage point, it produces an amount of “distortion” to the
output wave shape. This results in a condition that is commonly called Crossover Distortion.
Crossover Distortion produces a zero voltage “flat spot” or “dead band” on the output wave
shape as it crosses over from one half of the waveform to the other. The reason for this is that the
transition period when the transistors are switching over from one to the other does not stop or
start exactly at the zero cross-over point, thus causing a small delay between the first transistor
turning “OFF” and the second transistor turning “ON”. This delay results in both transistors
being switched “OFF” simultaneously, producing an output wave shape as shown in Figure 10.
Figure 10: Cross over distortion waveform
So that there should be no distortion of the output waveform, we must assume that each
transistor starts conducting when its base to emitter voltage rises just above zero, but we know
that this is not true because, for silicon bipolar transistors, the base-emitter voltage must reach at
least 0.7v before the transistor starts to conduct due to the forward diode voltage drop of the
base-emitter PN-junction, thereby producing this flat spot. This cross-over distortion effect also
-reduces the overall peak-to-peak value of the output waveform, causing the maximum power
output to be reduced, as shown in Figure 11.
● To eliminate cross over distortion, some modifications are necessary for the basic circuits
of the class B amplifiers
● The basic reason for the cross over distortion is the cut-in voltage of the transistor
junction
● To overcome the cut-in voltage, a small forward bias voltage is applied to the transistor
Practical Circuits
The drop across the diode D is equal to the cut-in voltage of the base-emitter junction of the
transistor. Hence the transistor conducts for full half-cycles eliminating the cross-over distortion.
Figure 13: Shift of Q point as a result of bias provided by diode
● Due to the forward bias provided to eliminate the cross-over distortion, the Q point shifts
upwards on the load line. The operation of the amplifier no longer remains class B but
becomes class AB operation
● Since the amplifier handles large signals in the order of volts, the shift in Q point is
negligibly small.
NB: For all practical purposes, the operation is treated as a class B operation, and all the
expressions derived apply to these modified circuits.
2. Complementary Symmetry Class B Amplifiers
● In Push-pull, transformer-coupled type, the drop across the forward-biased one diode
is sufficient
● But in the case of complementary symmetry circuits, base-emitter junctions of both
Q1 and Q2 are required to provide a fixed bias. Hence for silicon transistors, a fixed
bias of 0.7+ 0.7=1.4 V is needed. This can be achieved using a voltage divider
arrangement.
Figure 14: Voltage divider arrangement
● In this circuit, the bias provided is fixed, equal to 1.4V. The junction cut in voltage
changes with respect to temperature
● Therefore there is still a possibility of distortion when there is a temperature change
● Therefore instead of the use of R2, two diodes can be used to provide the required fixed
bias.
● As the temperature changes, the diode characteristics get changed and maintain the
necessary biasing needed to overcome the cross-over distortion when there is a
temperature change.
NB: All the expressions derived for the dual supply version are still applicable to the single
V cc
supply version. The only change required is that the value of V cc must be taken as while
2
calculating the various parameters of the circuit
Operation:
● For the positive half cycle of input, the base of NPN Q1 goes positive and conducts.
Q2 remains cut off
● Therefore the Darlington Pair provides a positive half cycle across the load.
● For the negative half cycle of input, the base of NPN Q1 goes negative; hence Q2
conducts. This drives Q4 to conduct, providing a negative half-cycle to the load with
a low impedance. Thus, a full cycle is available across the load for a common input
signal applied to the circuit.
NB: Practically, the Quasi Complementary Push Pull Power Amplifier Circuit is the most widely
used power amplifier