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Introduction To Digital Systems 3 (Combinational Ics
Introduction To Digital Systems 3 (Combinational Ics
Introduction To Digital Systems 3 (Combinational Ics
COMBINATIONAL ICs
voltage
V
Hmax
V H region
VHmin
Forbidden region
VLmax
V region
L
V Lmin
x
f z
y
N-TYPE:
open (off) if VCA < VTn
closed (on) if VCA > VTn
VTn { THE THRESHOLD VOLTAGE FOR N-TYPE SWITCH
P-TYPE:
open (off) if VBC < VTp
closed (on) if VBC > VTp
VTp { THE THRESHOLD VOLTAGE FOR P-TYPE SWITCH
B VBC + B
C
nS -
+ pS
C
V (a)
CA -
A A
Figure 3.3: a) N-TYPE AND P-TYPE CONTROLLED SWITCHES. b) nmos AND pmos TRANSISTORS.
x C z x z
nS
vin vout vin vout
A
vin
Ground (0V) VTn VDD
VDD - VTp
(a)
vin vout (b)
x z
VH VL x z
1 0
VL VH 0 1
(c) (d)
VDD VDD
z y
x
z
Circuit 1 Circuit 2
xy z z
0 0 1 1
0 1 1 0
1 0 1 0
1 1 0 0
AND OR
x x
z z
y y
VDD VDD
S3 S4 S5 x S4
z y S3 S5
x S2 S6
z
S1 S2 S6
y S1
u u
v v
z z
x x
y y
z = (uv + xy)’ z = [(u+v)(x+y)]’
Figure 3.7: COMPLEX GATES.
u v x y u v x y
VDD VDD VDD VDD
S4 S5
S3 S6
z z
S2 S7
S1 S8
C’
C n-switch p-switch z
0 off off Z
x z
1 on on x
(a)
Figure 3.8: a) TRANSMISSION GATE
x TG1
x
z z
y
TG2
y
(b)
Figure 3.8: b) xor GATE
y TG1 TG2 z
0 on off x
1 off on x 0
x0 TG1 x1 1
z MUX z
x0 0
x1 TG2
s
s
(c)
Figure 3.8: c) 2-INPUT mux.
s TG1 TG2 z
z = mux(x1 x0 s) = x1s x0s 0
0 on off x0
1 off on x1
Input Output
high
Input
50% 50%
low
high
Output 50% 50%
low
high-to-low low-to-high
propagation delay propagation delay
t t pLH
pHL
t
(a)
high
90% 90%
a
Gate Gate Gate
b z
1 2 4
c d
Gate
3
a
i in Gate
v in C in R in
high
Input voltage
low
Load A
high
Output voltage Load B
low
Load B > Load A
t
pLH (for load A)
t
pLH (for load B)
Load factor:
1
Gate
(Driving gate) 2
Gate 3
1 Gate
Total 3
load:
7 1
Gate
4
2
Gate
5
Noise margins
VHmin (OUT)
VHmin (IN)
Forbidden region
VLmax (IN)
VLmax (OUT)
s0
Module a0
M0
s1
y
sk
Module ak
Mk
s0
a0
Module bus
M0
s1
Module a 1 s0=s2=s3=0
M1 s1=1
s2 y
Module a 2
M2
s3
Module a 3
M3
(c)
(a)
VDD
e x g h pS nS y
e g
pS
x 0 0 1 0 open open Z
y 0 1 1 0 open open Z
h
nS 1 0 1 1 open closed 0
1 1 0 0 closed open 1
Figure 3.16: a) THREE-STATE GATE: SYMBOL AND FUNCTION. b) CIRCUIT AND OPERATION.
FULL-CUSTOM
SEMI-CUSTOM (standard cells)
GATE-ARRAY
(y = abd + a’c + c’d)
y
a
a’ abd
b
b’ a’c
c
c’ c’d
Silicon wafer
chip
pin
Enclosed chip
(IC package)
chip-to-pin wire
Printed circuit
board (PCB)
Connector
Rack
Backplane with
connectors
and wiring
PC boards
Cooling
fans
racks
Power
supply