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KAKATIYA INSTITUTE OF TECHNOLOGY & SCIENCE, WARANGAL-506015

(An Autonomous Institute under Kakatiya University, Warangal)
B. Tech. (EIE) VI-Semester
I-Mid Semester Examination
U14EI604 VLSI DESIGN

Date: 01.02.2017 Note: Answer the following questions.

Time: 2 Hours Max. Marks: 25

1 a Define Moore’s law and explain the developments in IC Technology. 2

b Differentiate between CMOS and bipolar technologies. 2

c Define transconductance and derive an expression for the same. 2

d Draw the circuit diagram of a 3 input nMOS NOR gate. 1

2 a Explain nMOS fabrication process with the help of neat sketches. 3

b Show the structure of nMOSFET and derive an expression for Drain current. 3
(OR)
c With the help of neat sketches explain P-Well fabrication process. 3
d Elaborate on various types of etches used in photolithographic process. 3

3 a Derive Pull Up- Pull Down ratio for nMOS inverter driven by another nMOS 3
inverter.
b Write about latch up phenomenon. Explain how latch up can be eliminated. 3
(OR)
c With the help of circuit explain the operation of a simple BiCMOS inverter. 3
Mention the advantages and drawbacks.
d Draw the stick diagram for a 2 input CMOS NAND gate. 3

4 a Explain the nMOS design style for drawing the stick diagrams. Show the 3
coding.
b Draw the stick diagram for a 2 input nMOS XOR gate. Use color coding for 3
stick diagram.
(OR)
c With neat sketches explain Lambda based design rules. 3
d Draw the lay out for a 2 input nMOS NAND gate. 3

---- Paper Ends ----

Paper set by: Prof. K. Sivani

 (b) Find the minimal SOP and POS expressions for the following function (3)
using K-Map and realize them with NAND and NOR gates respectively.
F(w,x,y,z)= ∑(0,1,2,3,4,6,7,8,9,11,15)
(c) Find the minimal expression for the following cyclic function using (3)
Tabulation (QM) method.
F(w,x,y,z)=∑(0,1,5,7,8,10,14,15)

4. (a) Write the truth table and derive the expressions for Sum and Carry outputs (3)
of a Full Adder circuit. Realize Full Adder circuit with two Half Adders.
(b) Construct a 4 to16 Decoder with five 2 to 4 Decoders with enable input and (3)
explain the operation.
(OR)
(c) Draw the schematic of a BCD Adder and explain its operation. (3)
(d) Implement the circuit which produces the following functions using a (3)
Decoder of appropriate size.
(i) F1(w,x,y,z)= xy’z’+x’y
(ii) F2(w,x,y,z)= ∑(0,1,4,5,6,7,9,10,11,15)

******

Paper set by:

Dr. K. Sivani
Sri.O.Anjaneyulu
Smt.B.Smitha
Sri. B.Venu Maheshwar
Sri. P.Yugander