Direct Memory Access (DMA)

Assuming the microprocessor HRQ pin is active, the microprocessor:

 Finishes execution of the current instruction

 Issues HLDA and the bus connection impedance goes HIGH.
 Waits for the HRQ signal to be inactive

DMA transfers take place through the DMA controller

DMA Controller (DMAC)

 Takes over READ /WRITE (RD/WR) and address functions

 DMAC requires
o Starting address of the sending or writing device
o Starting address of the receiving device
o How many bytes to transfer.
 DMAC operations
o Sends out the starting address for the sending device and the starting address for the
receiving device by sending READ pin active and receiver WRITE pin active
o Data is transferred at clock speed of DMA controller until all bytes have been
transferred
o Of course , after each byte transfer, addresses of both sender and receiver are
incremented before next transfer
 Modes of transfer
BYTE
Single byte of data -Used for refreshing of memory (DRAM) termed as
‘Dummy’ DMA READ

BLOCK

If a block was 512 bytes, then block would be 512

BURST

This mode does not limit the number of bytes. DMA sets different quantities for
each operation.

The 8237 DMA Controller

The 8237 has four programmable DMA channels. There are four DMA request inputs labeled DRQ0-
DRQ3. Any device requesting DMA services must drive the DRQ line active. After the DMA
controller issues a HOLD request to the microprocessor and intern received a HLDA, a
preprogrammed starting address for sender and receiver and a DAK that corresponds to DRQ are
Page 1 of 5
issued. DAKO-DAK3 serve as DMA acknowledge lines that cause the requesting device controller to
initiate the DMA operation.

Powerful computers with multitasking operating system in particular use the DMA concept to free the
microprocessor from simple but time-consuming data transfers where microprocessor registers are
involved in the data transfer. DMA controller establishes a second path between the peripheral and the
main memory in a computer system.

Data transfer is not carried out via an internal register of the DMA chip, but immediately via the data
bus between the main memory and the peripheral. The DMA controller outputs only the address and
bus control signals, thus the peripheral can access main memory directly through allocated DMA
channels. During this time of data transfer, the microprocessor may have calculated the shading of a
drawing or makeup of a page to be printed.

Page 2 of 5
Summary of DMA Controller (i8237)

 Has 27 internal registers with width between 4 and 16 bits

 One channel is allocated at any time.
 Registers
o Base address, base count, current address, current count, and mode registers are 4 for
each channel (totaling to 20 registers).
o Temporary address, temporary count, status, command, mask and request registers are
the other seven (7)
 Sixteen bit registers has a usable ability 64k depending on the application.
 Example:

o If count register reads 03ffH, the transfers are 1k of data.

o When count register reaches 1k , a terminal count (TC) is asserted by the DMA
o HRQ and DACK lines are deactivated before dropping DREQ.

 DMA requests can be served through two types of priority requests, fixed and rotating. With
fixed, channel 0 is the highest. Rotating mode has requests serviced in order of their
occurrence. Afterwards the current serviced channel is assigned the lowest priority.
 For DMA (i8237) to address more than eight bit, an additional external address latch is
provided for address A8 – A15. This address is loaded to the latch by the DMA through its data
bus (DB0 – DB7). The latch is activated by a ADSTB signal.
 For addressing beyond 16 bits, a DMA page register is used. A page register is available for
every channel. The page register is loaded by the microprocessor. The addressable space in this
mode is physically divided in pages or segments (64kB each for 8 bit channels 0- 3, or pages of
128kB for 16 bit channels 5-7. During these schemes, A0-A7 and A8-A15 are taken to
represent the offset.

DMA Segment Overflow (64kB page/segment)

Occurs when the counter contains addresses that cannot be marched with those on the address
register. A wrap-around of the address register from ffffh to 0000h occurs. Programmers must
be careful that data to be transferred is within the remaining section of the DMA page.
Page 3 of 5
Channels

DMA controller contains 4 independent 8-bit channels consisting of both an address register and
counter base on 8237 and 4 additional 16-bit channels. Some of the channels are allocated to fixed
devices such as the floppy disk. Although the channels may be used with other devices, it is best to
avoid situations where devices cannot receive their required DMA channel. The channel assignments
are presented in the following table:

Channel Size Usage

0 8-bit DRAM refresh
1 8-bit Free
2 8-bit Floppy Disk Controller
3 8-bit Free
4 16-bit Cascading
5 16-bit Free
6 16-bit Free
7 16-bit Free

Example: I/O to Memory Transfer

In this example, we will consider a DMA transfer from an I/O device (the diskette drive) to memory,
also referred to as a DMA write operation.

1. The diskette driver receives a request to read data from a specific sector and transfer the
information to a specific buffer. The diskette drive uses DMA channel 2, which means that the
DMA buffer must fall within the first 1MB of memory (newer controllers allow all eight channels
to access memory within the first 16MB) and cannot exceed 64K, nor cross a 64K page. We will
Page 4 of 5
 assume that the diskette driver has already allocated a suitable DMA buffer as part of its
initialization.
2. The diskette driver now performs the necessary operations to position its read/write head on the
correct sector and track before sending the necessary information to the DMA controller including
the following:
o The base address in memory where the DMA buffer is located.
o The number of bytes to transfer minus one.
o The offset within the buffer.
o The DMA operation (in this case a write operation).
3. The diskette driver updates the DMA mask to allow recognition of DMA channel 2 requests before
sending the read command to the diskette controller. In a multi-processing operating system, the
kernel will block the user process that requested the diskette operation and schedule a new process
for execution.
4. The diskette drive, under the supervision of its controller card, will begin to read data from the
diskette surface before transferring it to its data register. Once data becomes available, the diskette
controller will request DMA service by asserting a high on DMA request line 2 (DREQ2).
5. The DMA controller verifies that DREQ2 may be allowed (by examining its mask register) and
requests the CPU to enter a hold mode. This is done by asserting the hold request line (HRQ).
6. The CPU will respond by asserting hold acknowledge (HLDA) and now enters a bus holding state.
7. The DMA controller will generate an address before passing it to the bus and activating the
memory write and I/O read control lines. The DMA acknowledge signal (DACK2) is activated to
inform the diskette controller that the DMA transfer is in progress.
8. The data is transferred from the diskette controller's data register to memory without passing
through the DMA controller. After every transfer, the DMA controller will decrement the
countdown register associated with channel 2. During the transfer, the CPU effectively shares the
bus with the diskette controller by interleaving bus hold cycles and normal cycles under the
supervision of the DMA controller (sometime referred to as cycle stealing).
9. If the transfer completes, the DMA controller will assert the terminal count line signal (TC). Note
that the DMA controller may temporarily stop the transfer by dropping DREQ2 if the transfer rate
is too fast to handle. The TC signal indicates to the diskette controller that the operation has been
completed and the HRQ and DACK2 lines are deactivated before dropping DREQ2.
10. At this point the CPU will resume normal bus control, but the diskette controller will signal the
operating system through the PIC that the operation is complete by asserting IRQ6. Control will
typically be transferred to the interrupt handler of the diskette driver to verify the controller results
before copying the data from the DMA buffer to the buffer supplied by the user processes.

Page 5 of 5