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2110251 Digital Computer Logic
Homework #4
Instructions: Please submit only one PDF file in myCourseVille before the deadline on
October 24, 11:59 pm.

1) (3 points) You have learned about D flipflop in the class. Consider clock and input D
shown in the waveform below. Draw output waveforms from D device for each of the
following type of D-device (assume no delay)
1.1) clock latch or level-sensitive
1.2) negative edge-triggered flip-flop
1.3) master-slave flip-flop (same concept as master-slave JK flip-flop)
1.4) positive edge-triggered flip-flop

1111
Clk

1.1)

1.2)

1.3)

1.4)
 ^
AB

✗ o o 1 P = B- + AP
,

P{ ✗ 0 I

¥ A B P H
2. (4 points) Consider the cross-coupled NAND gates. o o o ✗

1 0 0 1 ✗ ) forbidden
A I \P ° ^ ° °

}
o
, reset
0 I 1 O

n 0 0

1 0 I
1)
7
set
°
'
P
B
,
o
! ! 9 9) hola

2.1) What input conditions cause the state of this latch-like device to be reset or set? Write
down truth table for inputs as A and B and output as P and \P and identify state (hold, set,
reset, forbidden, toggle) for each of the case. For column, P and \P, you can answer 0, 1, P,
and \P.

A B P \P State
0 0 7 1 forbidden
0 1 0 1 reset

1 0 I 0 set

1 1 p IP hold

2.2) Write down the Boolean equation for P in terms of A, B or P.

P+ =
B- + AP

2.3) You have studied R-S latch, J-K flip-flop, D flip-flop, and T flip-flop in the class. Write
down the variables in terms of R,S,J,K,D,T or Q in the blank boxes below that has the same
circuit behavior to the cross-coupled NAND gates.

R Q

S IQ
3) (3 points) Look at the excitation tables in the lecture, implement T flip-flop with J-K flip-
flop. Draw K-map, characteristic equation, and the circuit.
T
O l
a

0 1
0

I 1 0

eéi TÉ + Ice =
TXORQ

T
0 1
a
0 0 7

I
✗ X

J = T
T
O '
Q
O ✗ ✗

I 0 1

k =
T

Jk - RLIPRLOP
-
J Q -

-
K a- ←

CLK

rn