LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY part5 IS

PORT ( SW : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

HEX0 : OUT STD_LOGIC_VECTOR(0 TO 6) ;
HEX1 : OUT STD_LOGIC_VECTOR(0 TO 6) ;
HEX2 : OUT STD_LOGIC_VECTOR(0 TO 6) ;
HEX3 : OUT STD_LOGIC_VECTOR(0 TO 6) ;
HEX4 : OUT STD_LOGIC_VECTOR(0 TO 6) ;
HEX5 : OUT STD_LOGIC_VECTOR(0 TO 6) );

END part5;

ARCHITECTURE Behavior OF part5 IS

COMPONENT mux_2bit_4to1
PORT ( S,U, V, W, X,Y,Z : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END COMPONENT;

COMPONENT char_7seg
PORT ( C : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
Display : OUT STD_LOGIC_VECTOR(0 TO 6));
END COMPONENT;

SIGNAL Ch_Sel : STD_LOGIC_VECTOR(2 DOWNTO 0);

SIGNAL Ch0, Ch1, Ch2, Ch3, Ch4, Ch5 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL H5_Ch,H4_Ch,H3_Ch, H2_Ch, H1_Ch, H0_Ch : STD_LOGIC_VECTOR(2
DOWNTO 0);

begin

Ch_Sel <= SW(2 downto 0);

Ch0 <= "000";
Ch1 <= "001";
Ch2 <= "010";
Ch3 <= "011";
Ch4 <= "100";
Ch5 <= "101";

M5: mux_2bit_4to1 PORT MAP (Ch_Sel, Ch0, Ch1, Ch2, Ch3, Ch4, Ch5, H5_Ch);
M4: mux_2bit_4to1 PORT MAP (Ch_Sel, Ch5, Ch0, Ch1, Ch2, Ch3, Ch4, H0_Ch);
M3: mux_2bit_4to1 PORT MAP (Ch_Sel, Ch4, Ch5, Ch0, Ch1, Ch2, Ch3, H1_Ch);
M2: mux_2bit_4to1 PORT MAP (Ch_Sel, Ch3, Ch4, Ch5, Ch0, Ch1, Ch2, H2_Ch);
M1: mux_2bit_4to1 PORT MAP (Ch_Sel, Ch2, Ch3, Ch4, Ch5, Ch0, Ch1, H3_Ch);
M0: mux_2bit_4to1 PORT MAP (Ch_Sel, Ch1, Ch2, Ch3, Ch4, Ch5, Ch0, H4_Ch);

H5: char_7seg PORT MAP (H5_Ch, HEX5);

H4: char_7seg PORT MAP (H4_Ch, HEX4);
H3: char_7seg PORT MAP (H3_Ch, HEX3);
H2: char_7seg PORT MAP (H2_Ch, HEX2);
H1: char_7seg PORT MAP (H1_Ch, HEX1);
H0: char_7seg PORT MAP (H0_Ch, HEX0);

END Behavior;

//////////////////////////////////////////
library ieee;
use IEEE.STD_LOGIC_1164.all;

entity PART8 is
PORT (SW : IN STD_LOGIC_VECTOR(9 DOWNTO 7);
LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 7);
Q,L,R : OUT STD_LOGIC_VECTOR(0 TO 6);
X,Y,U: OUT STD_LOGIC_VECTOR(0 TO 6));
end entity PART8 ;

architecture st of PART8 is
COMPONENT MUXA
PORT (G1,G2,G3,G4,G5,G6 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sel : in std_logic_vector(2 downto 0);
M: OUT std_logic_vector (3 DOWNTO 0) );
end COMPONENT ;
COMPONENT seg
PORT (C : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Seven_Segment : OUT STD_LOGIC_VECTOR(0 TO 6));
end component ;
signal m,v,j,g,B: std_logic_vector(3 downto 0);
signal H5_Ch,H4_Ch,H3_Ch,H2_Ch,H1_Ch,H0_Ch: std_logic_vector(3 downto 0);
signal sel : std_logic_vector(2 downto 0);
begin
LEDR <=sel;
sel <= sw(9 downto 7);
m <= "0000" ;
v <= "0001" ;
j <= "0010" ;
g <= "0011" ;
B <= "0100" ;
M0 : MUXA port map (B,B,m,v,j,g,sel,H0_Ch) ;

M1 : MUXA port map (B,m,v,j,g,B,sel,H1_Ch) ;

M2 : MUXA port map (m,v,j,g,B,B,sel,H2_Ch) ;

M3 : MUXA port map (v,j,g,B,B,m,sel,H3_Ch) ;

M4 : MUXA port map (j,g,B,B,m,v,sel,H4_Ch) ;
M5 : MUXA port map (g,B,B,m,v,j,sel,H5_Ch) ;
H0:seg PORT MAP (H0_Ch,U);
H1:seg PORT MAP (H1_Ch,Y);
H2:seg PORT MAP (H2_Ch,X);
H3:seg PORT MAP (H3_Ch,R);
H4:seg PORT MAP (H4_Ch,L);
H5:seg PORT MAP (H5_Ch,Q);
end st ;
library ieee;
use ieee.std_logic_1164.all;
entity seg is
port(C : in std_logic_vector(3 downto 0);
Seven_Segment : out std_logic_vector(0 to 6));
end seg;
architecture Behavior of seg is
begin
with C select
Seven_Segment <= "1000010" when "0000",
"0110000" when "0001",
"1001111" when "0010",
"0000001" when "0011",
"1111111" when others ;

end Behavior;
library ieee;
use ieee.std_logic_1164.all;
entity MUXA is
port ( G1 : in std_logic_vector(3 downto 0);
G2 : in std_logic_vector(3 downto 0);
G3 : in std_logic_vector(3 downto 0);
G4 : in std_logic_vector(3 downto 0);
G5 : in std_logic_vector(3 downto 0);
G6 : in std_logic_vector(3 downto 0);
sel : in std_logic_vector(2 downto 0);
M : out std_logic_vector(3 downto 0));
end entity;

architecture Behavioral of MUXA is

begin
M <= G1 when sel = "000" else
G2 when sel = "001" else
G3 when sel = "010" else
G4 when sel = "011" else
G5 when sel = "100" else
G6 when sel = "101" ;
end Behavioral;
---------------------------MUX-----------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY mux_2bit_4to1 IS
PORT (S,U, V, W, X,Y,Z : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END mux_2bit_4to1;

ARCHITECTURE Behavior OF mux_2bit_4to1 IS

begin

with S select
M <= U when "000",
V when "001",
W when "010",
X when "011",
Y when "100",
Z when "101",

(others => 'Z') when others;

END Behavior;

--------------------------7-seg-----------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY char_7seg IS
PORT ( C : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
Display : OUT STD_LOGIC_VECTOR(0 TO 6));
END char_7seg;

ARCHITECTURE Behavior OF char_7seg IS

begin

with C select

Display <= "1111111" when "000",

 "1111111" when "001",
"1000010" when "010",
"0110000" when "011",
"1001111" when "100",
"0000001" when "101",

--Display <= "1000010" when "000",

-- "0110000" when "001",
-- "1001111" when "010",
-- "0000001" when "011",
-- "1111111" when "100",
-- "1111111" when "101",

(others => 'Z') when others;

END Behavior;

-----------------------------------------------------------------