Professional Documents
Culture Documents
Answer Key CSE 105 II - CIA PART A (10X2 20)
Answer Key CSE 105 II - CIA PART A (10X2 20)
PART A (10X2=20)
The address specified in a branch, which becomes the new program counter (PC) if the branch is
taken. In the MIPS architecture the branch target is given by the sum of the offset field of the
instruction and the address of the instruction following the branch.
We can generate the 4-bit ALU control input using a small control unit that has as inputs the
function field of the instruction and a 2-bit control field, which we call ALUOp.
4. Classify the hazards in the pipeline based on its recoverable nature and justify.
Structural hazard (Non Recoverable)
Data and Control hazard (Recoverable)
5. When will the forwarding method fail and give a suitable example?
Forwarding will fail for load- use case. (1)
Any one load instruction for the example. (1)
7. Construct five-stage pipeline with the graphical representations for the given instruction
lw $10, 20 ($1)
8. Identify the dependencies in the following instruction sequence and detect the possible
hazards
sub $2, $1, $3
and $12, $2, $5
or $13, $6, $2
A technique to get more performance from loops that access arrays, in which multiple copies of
the loop body are made and instructions from different iterations are scheduled together.
Hit time is the time to access the upper level of the memory hierarchy, which includes the time
needed to determine whether the access is a hit or a miss.
The miss penalty is the time to replace a block in the upper level with the corresponding block
from the lower level, plus the time to deliver this block to the processor.
11. Construct the MIPS datapath neatly with all the control signals and explain the operation of
branch-on-equal instruction by high lighting the active blocks in that datapath.
For MIPS data path for BEQ with active and non active blocks (5 Marks)
12. What is branch penalty? Explain in detail about the available handling methods to reduce it.
Clock cycles wasted in wrongly fetching subsequent instruction in pipeline before the calculation
of branch address during control hazard is called as branch penalty. (2 Marks)
c) Model the architecture for dynamically scheduled pipeline and explain how dynamic
pipeline scheduling is done? (4 Marks)
14. a) Classify the memories based on speed, access time, size, cost, technology and arrange
them in hierarchical order. (4)
Diagram with the above related illustration of various parameters (4 Marks)
i) Deduct the clock cycle at which the exception will be taken into pipeline (assume
instruction at 50hex address fetched in CC1)?
ii) Interpret the PC register value during overflow and after exception?
Flushing of instructions after add instruction in the pipeline from the pipeline
registers will happen. (2 Marks)