IEEE Sponsored 2nd International Conference on Innovations in Information Embedded and Communication Systems

ICIIECS’15

FPGA Implementation of Efficient AES Encryption

S.Sridevi sathya Priya1,P.Karthigai Kumar2, N.M. SivaMangai3, V.Rejula4

1, 3, 4
Department of Electronics and Communication Engineering, Karunya University, Coimbatore.
2
Department of Electronics and Communication Engineering, Karpagam College of Engineering, Coimbatore.

Abstract- In this paper, a high throughput modified

Advanced Encryption Standard (AES)-128 bit
algorithm is implemented. A new increased parallelism
technique is introduced in modified AES architecture
in Mix Column round which increases the overall
throughput of AES algorithm. This technique is
implemented in XC5VLX50T FPGA device Virtex-5.
Using this technique throughput is increased 5 % and
area is decreased by 30 % when compared to parallel
mixcolumn.
Keywords- AES ,increased Parallelism, throughput,
latency,high throughput.
I . INTRODUCTION
Encryption is the process of encoding information
so it cannot be read by hackers. The information is
encrypted using AES algorithm and is converted into
a form unreadable, which is called a cipher text. The
authorized person will decode the information using
decryption algorithms. The cryptography algorithms
are of three types symmetric cryptography (using 1
key), asymmetric cryptography (using 2 different
keys), and cryptographic hash functions using no
keys.
Symmetric algorithms are faster than asymmetric
algorithms since the CPU cycles needed for
symmetric encryption are fewer than for asymmetric
encryption. Advanced Encryption Standard (AES),
Data Encryption Standard (DES), Triple DES, Rivest
Cipher (RC2), Rivest Cipher (RC6), and Blowfish are
some of the symmetric algorithms. Remote Secure
Access is an asymmetric algorithm.
The AES operates on 128-bits of data. The
algorithm can encrypt and decrypt blocks using
cipher keys. The key size can either be 128 bit, 192
bit, or 256 bit. The AES (advanced encryption
standard) is an encryption standard and a symmetric
block cipher.
II. RELATED WORK:
The first AES implementation on silicon, which
provides a throughput of 2.29 Gbps using a non
pipeline architecture [1]. The common technique
used to enhance the performance of AES system is by
using pipelining, which acquired a throughput of 8
Gbps [2]. The first AES implementation with a
throughput over 10 Gbps was proposed by applying
T-box, which is a combination of the Sub Bytes, Shift
Rows, and Mix Columns phases in the AES
algorithm [3]. A fully pipelined AES processor has
more complex operations and achieves throughput
between 30 and 70 Gbps [4]. A high performance
AES system, by using a ten stage implicit pipelined
architecture, the system performance is limited upto
1.85 Gbps because of the memory usage [5].
Implementation of a fully pipelined AES processor
on FPGA which gave a performance of 21.54 Gbps
but occupied a large area of 5177 slices and showed
latency of 31 cycles [6]. A new methodology to
implement the AES algorithm using partial and
dynamic reconfiguration. This technique uses
pipelining and parallel implementation with partial
and dynamic reconfiguration and gives a throughput
of 24.922 Gbps but uses 3576 slices and has a larger
area [7]. Parallelism was applied to blocks which
causes more delay thereby increasing the throughput
of Mix Columns to 68.82 Gbps using Many-Core 167
Processor [8].

978-1-4799-6818-3/15/$31.00 © 2015 IEEE

IEEE Sponsored 2nd International Conference on Innovations in Information Embedded and
Communication Systems ICIIECS’15
In June 2003, the National Security Agency (NSA) Add Round Key - each byte of the state is combined
announced that AES-128 may be used for classified with the round key; each round key is derived from
information at the SECRET level and AES 192/256 the cipher key using a key schedule [10].
for TOP SECRET level documents. AES is an
algorithm for performing encryption decryption
which is a series of well-defined steps that can be
followed as a procedure. The original information as
input is known as plaintext, and the encrypted result
as cipher text. The cipher text message contains the
same plain text information , but is in a unreadable
format by a human or computer without the proper
mechanism to decrypt it; it should resemble
meaningless to those not intended to read it. The
encrypting procedure varies depending on the key
which changes the detailed operation of the
algorithm. Without the key, the cipher cannot be
obtained on encryption and the plain text cannot be
decrypted. In the past, cryptography helped to ensure
secrecy in important communications, such as those
of government intelligence operations, military
leaders, and diplomats. Cryptography has come to
widespread use by many civilians who do not have
higher needs for secrecy, although it is transparently
built into the infrastructure for computing and
telecommunication applications.

AES for high-throughput hardware

implementations are mostly used for high-end
devices such as accelerator cards for e-commercial
service and security trunk communication [9].
Fig. 1. AES Encryption

The paper is organized as follows. In section 3, a

brief description of the AES algorithm is given. In
section 4 , the architecture of the proposed design is
provided. Section 5 provides the implementation
results. Performance analysis and the results are
shown in section 6. Section 7, deals with the
conclusion.
AES algorithm comprises of various rounds
depending on the key size and block size is explained
in Table I. Out of all the rounds the Pre- round
comprises only Add Round Key whereas the final
round omits the Mix Columns stage.
TABLE I
Key-Block-Round Combinations

III. AES ALGORITHM Key Length(32- Block Size(32- Number of

bit word) bit word) Rounds
AES is based on Rijndael Cipher. Rijndael is a
AES-128 4 4 10
family of ciphers with different key and block sizes
AES-192 6 4 12
in multiple of 32 bits. AES is a symmetric-key
algorithm, because the same key is used for both AES-256 8 4 14
encrypting and decrypting the data. AES operates on
a 4×4 array of bytes, called the state. In encryption, A. Sub Bytes
each round consists of four stages except the last The function of the sub byte is only nonlinear
round which excludes mix column round as shown in function and that operates independently on each byte
Fig. 1. Sub Bytes - a non-linear substitution step of the state using a substitution table (S-box). It
where each byte is replaced with another according to substitutes all bytes of the state array using a LUT
a lookup table (known as S Box). Shift Rows - a which is a 16x16 matrix of bytes, often called S-box
transposition step where each row of the state is table.
shifted cyclically a certain number of steps. Mix
Columns - a mixing operation operates on the B. Shift Rows
columns of the state, using a linear transformation.
IEEE Sponsored 2nd International Conference on Innovations in Information Embedded and
Communication Systems ICIIECS’15
In shift rows transformation the last three rows of single clock cycle the execution of the whole block
the State are cyclically shifted over different numbers takes place i.e. the eight stages of parallelism divides
of bytes in this process the row 0 is not shifted, row 1 the clock period of the mix columns block, such that
is shifted one byte to the left, row 2 is shifted two two elements of the matrix are executed during 1/8th
bytes to the left and row 3 is shifted three bytes to the of the clock period.
left [11]. This reduces the latency of the process and
C. Mix Columns increases the speed and also area is optimized when
This transformation is based on Galois Field compared to the previous four stage parallelism
multiplication. Each byte of the matrix is replaced technique [13].
with another value that is a function of all four bytes
in the given column. The Mix Columns
transformation works on the State column wise,
treating each column as a four term polynomial.

D. Add Round Key

The Add Round Key operation is a simple EXOR
operation between the State and the Round Key. The
Round Key is obtained from the Cipher key by means
of the key schedule. The State and Round Key are of
the same size and to obtain the next State an EXOR
operation is done.

E. Key Scheduling
The Round Keys are derived from the Cipher Key
by means of a key schedule. The number of Round
Keys necessary to encrypt one block of information
depends on the block length and key length as this
determines the number of rounds. For a block length
of 128 bits, 11 Round Keys are needed i.e. one for
initial round, 9 for standard rounds(sub bytes, shift
rows, mix column and add round key) and one for the
final round).

IV. PROPOSED METHODOLOGY

Fig. 2. AES using Eight Stage Parallelism

A. Four Stage Parallelism in Mix Column
The AES Mix Columns transformation operates on
a four column data block, and the operation on each V. IMPLEMENTATION RESULTS
and every column is independent. In a single loop,
the execution delay of Mix Columns results in 60 A. Simulation of Eight stage Parallelism in
percent of the total latency. Therefore Parallelism is Modelsim
introduced in Mix Columns block. As a result, the
throughput of the Mix Columns implementation is
increased [12].
In Four stage Parallelism, each Mix Column block
computes only one column at a time rather than a
whole data block.

B. Eight Stage Parallelism in Mix Column

In order to increase the throughput further, we are
modifying the four stage parallelism to eight stage
parallelism which is known as the increased
parallelism technique. Each mix column block in
eight stage parallelism computes only 2 elements at a
time rather than considering a column, the structure
of eight stage parallelism is shown in Fig. 2. In a
IEEE Sponsored 2nd International Conference on Innovations in Information Embedded and
Communication Systems ICIIECS’15
Fig. 3. Eight Stage Parallelism Simulated Result [7] J. Granado-Criado, M. Vega Rodriguez, J. Sanchez Perez, and
J. Gomez Pulido, “A New Methodology to Implement the AES
Algorithm Using Partial and Dynamic Reconfiguration,”
The Plain text for AES encryption is Integration, the VLSI J., vol. 43, no. 1, pp. 72-80, 2010.
“3243f6a8885a308d313198a2e0370734” and its [8] Bin Liu, and Bevan M. Baas, “Parallel AES Encryption
cipher text is ”3925841d02dc09fbdc1185979196a0 Engines for Many-Core Processor Arrays,” IEEE transactions on
computers, vol. 62, no. 3, march 2013.
b32”. The execution of the two elements of the [9] Chi-Jeng Chang1, Chi-Wu Huang2, Kuo-Huang Chang1, Yi-
matrix are performed by executing two elements at Cheng Chen2 and Chung-Cheng Hsieh1,”High Throughput 32-bit
the same time in parallel using eight stage parallelism AES Implementation in FPGA “.
technique, in order to increase the throughput of AES [10] Vedkiran Saini, Parvinder Bangar, Harjeet Singh Chauhan,”
Study and Literature Survey of Advanced Encryption Algorithm
Encryption. for Wireless Application ,“ International Journal of Emerging
Science and Engineering (IJESE) ISSN: 2319–6378, Volume2,
VI. PERFORMANCE COMPARISON Issue-6, April 2014.
[11] Bin Liu and Bevan M. Baas Department of Electrical and
TABLE II Computer Engineering University of California, Davis,” A High-
Comparison of throughput, delay and area. Performance Area-Efficient AES Cipher on a Many-Core
Platform”.
Technique Throughput Delay Area [12] Bin Liu, Student Member, IEEE, and Bevan M. Baas, Senior
Used (Gbps) (ns) (no. of Member, IEEE, ”Parallel AES Encryption Engines for Many-Core
slices) Processor Arrays,” IEEE transactions on computers, vol. 62, no. 3,
Mix Columns march 2013.
56.77 2.255 7920 [13] Rajalakshmi A and Ashok Kumar A,” Design of High-
Four stage throughput and Area efficient hardware using AES Algorithm
parallelism in 57.16 2.239 4576 ,”International Journal of Scientific & Engineering Research,
Mix Column Volume 5, Issue 5, May-2014.
Eight stage
parallelism in 60.47 2.117 3168
Mix Column
The results obtained on synthesis is shown in
Table II. The throughput of parallelized blocks are
increased and their area is decreased .

VII. CONCLUSION

The AES which is presented is used to protect the

information. In order to increase the efficiency, the
increased parallelism technique is used. The proposed
design requires less area when compared to the
previous other techniques and throughput is increased
5% and is implemented using XC5VLX50T FPGA
device Virtex-5.

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