TRƯỜNG ĐẠI HỌC BÁCH KHOA HÀ NỘI

VIỆN ĐIỆN TỬ - VIỄN THÔNG

TECHNICAL WRITING AND PRESENTATION

FINAL REPORT

Topic:
DESIGN AN ALGORITHMIC AMPLIFIER CIRCUIT
OPERATIONAL AMPLIFIER

Student: ĐÀO VIỆT DŨNG

Student ID: 20180049
Class: CTTN – ĐTTT – K63
Instructer: PhD. NGUYỄN THU VÂN

Hà Nội, 8-2021
 TABLE OF CONTENTS

LIST OF FIGURES ................................................................................................................... i

ABSTRACT ..............................................................................................................................ii

CHAPTER 1. INTRODUCTION TO OPERATIONAL AMPLIFIER CIRCUIT ............. 1

1.1 Definition......................................................................................................................... 1

1.2 Characteristics of an amplifier circuit ........................................................................... 1

CHAPTER 2. THEORETICAL BASIS.................................................................................. 2

2.1 Op-Amp parameters ........................................................................................................ 2

2.1.1 Gain .......................................................................................................................... 2
2.1.2 Small-Signal Bandwidth .......................................................................................... 2
2.1.3 Output Swing ........................................................................................................... 2
2.1.4 Phase margin ............................................................................................................ 2

2.2 Circuit diagram and circuit structure ............................................................................ 3

2.3 Block 1: Current mirror ................................................................................................. 4

2.4 Block 2: Amplifier stage 1: Differential pair ................................................................. 5

2.5 Block 3: Amplifier stage 2: Source................................................................................. 7

2.6 Calculatin the parameters for the circuit ....................................................................... 7

CHAPTER 3. DESIGNING AND SIMULATING OPERATIONAL AMPLIFIER

CIRCUIT ................................................................................................................................. 10

3.1 Design on Cadance ....................................................................................................... 10

3.2 Simulation result ........................................................................................................... 10

CHAPTER 4. CONCLUSION............................................................................................... 13

REFERENCES ....................................................................................................................... 14
 LIST OF FIGURES

Figure 1.1: I-O pin diagram of the Op-Amp ...................................................................1

Figure 2.1: Basic Two-stage Op-Amp configuration ......................................................3
Figure 2.2: Complete circuit diagram of Op-Amp ..........................................................3
Figure 2.3: Current mirror ...............................................................................................4
Figure 2.4: Basic Current mirror diagram .......................................................................4
Figure 2.5: Differential pair .............................................................................................5
Figure 2.6: (a) Single-ended and (b) Differential signals ................................................6
Figure 2.7: (a) Corruption of a coupling signal, (b) Reduction of coupling by
differential........................................................................................................................6
Figure 2.8: Suorce follower .............................................................................................7
Figure 3.1: Complete circuit topology...........................................................................10
Figure 3.2: Simulation result of Gain ............................................................................ 11
Figure 3.3: Simulation result of Phase Margin .............................................................. 11

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 ABSTRACT

Operational amplifiers (Op-Amp) are an integral part of many analog and mixed-
signal systems. Op-Amp with vastly different levels of complexity are used to realize
functions ranging from DC bias generation to high-speed amplification or filtering.
The algorithmic amplifier circuit plays an important part in most electronic devices
today. Its main function is to regulate the electric current so that the current has the
right value to flow into the subsequent part of the circuit. This report aims to determine
how such circuits can output that current and obtain a high gain. Specifically, it
focuses on the circuit to operate in a large frequency range.
To test the principle of the algorithmic amplifier circuit, the Cadence tool was used
for circuit simulation to get the most reliable results. The results showed that the
circuit can operate very stably and the time to reach a steady-state is also very fast. On
this basis, an operational amplifier circuit is suitable for use in bigger circuits that
require large currents and operate at high frequencies.

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 CHAPTER 1. INTRODUCTION TO OPERATIONAL

AMPLIFIER CIRCUIT

1.1 Definition
An operational amplifier, commonly referred to as Op-Amp for short, is a “DC-
coupled” amplifier circuit (input signal including BIAS signal) with very high gain,
differential input and a normal single output. In common applications, the output is
controlled by a negative feedback circuit so that the gain, input impedance, and output
impedance can be determined.

Figure 1.1: I-O pin diagram of the Op-Amp

1.2 Characteristics of an amplifier circuit

The two inverting and non-inverting inputs allow an Op-Amp to the amplify
asymmetric signal source.
An Op-Amp has:
• A very large gain that allows it to amplify even signals with amplitudes of only
a few microvolts.
• A large input impedance that allows it to amplify signal source with low power.
• A small output impedance that allows it to provide good voltage and current to
the load.
• A very wide bandwidth, enabling it to work well with many different types of
signal sources.
This report deals with the analysis and design of CMOS Op-Amp, we describe
simple Op-Amp as a two-stage amplifier configuration.

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 CHAPTER 2. THEORETICAL BASIS

2.1 Op-Amp parameters

This section describesa number of Op-Amp design parameters, providing an
understanding of why and where each may become important.

2.1.1 Gain
The open-loop gain of n Op-Amp determines the precision of the feedback
systemusing Op-Amp. The required gain may vary by four orders of magnitude
according to the application. The minimum required gain must be known for such
parameters as speed and output voltage swings. In addition, a high open-loop gain may
also be necessary to suppress non-linearity.

2.1.2 Small-Signal Bandwidth

The high-frequency behavior of Op-Amps plays a critical role in many
applications. For example, as the frequency of operation increases, the open-loop gain
begins to drop, creating larger errors in the feedback system. The small-signal
bandwidth is usually defined as the “unity-gain” frequency, which exceeds 1 GHz in
today’s CMOS Op-Amps.

2.1.3 Output Swing

Most systems employing Op-Amps required large voltage swings to accommodate
a wide range of signal amplitude. For example, a high-quality microphone that senses
the music produced by an orchestra may generate instantaneous voltages that vary by
more than four orders of magnitude, demanding that subsequent amplifiers and filters
handle large swings and achieve low noise. The need for large output has made fully
differential Op-Amps quite popular. Op-Amps generate “complementary” outputs,
roughly doubling the available swing. However, the maximum voltage swing trade-off
with device size and bias currents and hence speed. Achieving large swings is the
principal challenge in today’s Op-Amp design.

2.1.4 Phase margin

In electronic amplifiers, the phase margin (PM) is the difference between the phase
lag φ (<0°) and -180°, for an Op-Amp’s output signal at zero dB gain.
PM = φ - (-180°)
For example, if the Op-Amp’s open-loop gain crosses 0 dB at a frequency where
the phase lag is -135°, so the phase margin of this feedback system is (-135°) –(-180°)
= 45°. Normally, the value of PM will be between 45° and 75° for the system to reach
asteady-state as quickly as possible.

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2.2 Circuit diagram and circuit structure
Previous sections described the I-O pin diagram of an Op-Amp. This section will
show its inner circuit. A two-stage Op-Amp circuit is illustrated in Figure 2.1.

Figure 2.1: Basic Two-stage Op-Amp configuration

In this circuit, we can see two separate amplification stages, with two current
sources Iss and Il for each stage. However, using up to two current sources would make
the circuit too large and face asynchronous problems. A circuit that uses only one
current source that can be duplicated using the current-mirror method, providing two
amplification stages, will not face the problem of circuit sizing andsynchronization.
Figure2.2 illustrates the circuit implemented using only one current source.

Figure 2.2: Complete circuit diagram of Op-Amp

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2.3 Block 1: Current mirror

Figure 2.3: Current mirror

The reason why this method is used in this circuit is that the design of current
sources in analog circuits is based on “copying” currents from a reference, with the
assumption that one precisely defined current source is already available. A complex
circuit is used to generate a stable reference current, IREF, which is then copied to many
current sources in the system.

Figure 2.4: Basic Current mirror diagram

For example, in Fig. 5, the structure consisting of M1and M2 is called a “current
mirror”. How do we guarantee Iout = IREF? For a MOSFET ID = f(VGS), where f()
denotes the functionality of ID versus VGS, then VGS = f1(ID). If the first is biased at
IREF, then is produced VGS=f-1(IREF). Therefore, if this voltage is applied to the gate and
source terminals of the second MOSFET, the resulting current is Iout = f(f-1(IREF)) =
IREF.
In the general case, the devices need not be identical.

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 1 w
IREF = μn Cox ( ) 1(VGS − VTH )2
2 l
1 w
Iout = μn Cox ( ) 2(VGS − VTH )2
2 l
Hence
W
( )1
l
Iout = W
IREF
( )2
l

Based on the above equation, we can control the currents flowing into the
W
following parts of the circuit by changing the ratio ( ) of the MOSFET M5, M6, M7 in
L

Fig.4. The key property of this topology is that it allows precise copying of the current
with no dependence on process and temperature. This is really suitable for integrated
circuits that need stability and accuracy, especially with our topic, algorithmic
amplifier circuit.

2.4 Block 2: Amplifier stage 1: Differential pair

Figure 2.5: Differential pair

The differential amplifier is among the most important circuit inventions, offering
many useful properties. The differential operation has become the dominant choice in
today’s high-performance analog and mixed-signal circuits.
A single-ended signal is defined as one that is measured with respect to a fixed
potential, usually the ground. A differential signal is defined as one that is measured
between two nodes that equal and opposite signal excursions around a fixed potential.
Figure 2.6 illustrates the two types of signals conceptually.

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 Figure 2.6: (a) Single-ended and (b) Differential signals
An important advantage of differential operation over single-ended signaling is a
higher decrease in noise. Consider the example depicted in Fig.8, where two adjacent
lines in a circuit carry a small, sensitive signal and large clock waveform. Due to
capacitive coupling between the lines, transitions like L2 corrupt the signal on line L1.
Mow suppose, as shown in Fig.8(b), the sensor signal is distributed as two equal and
opposite phases. If the clock line is placed midway between the two, the transitions
disturb the differential phases by equal amounts, leaving the difference intact. Since
the common-mode level of the two phases is disturbed but the differential output is not
corrupted.

Figure 2.7: (a) Corruption of a coupling signal, (b) Reduction of coupling by differential
Another useful property of differential signaling is the increase in maximum
achievable voltage swings, which makes the circuit operate at a high performance.
Other advantages of differential circuits over single-ended counterparts include
simpler biasing and higher linearity. However, the gain of this topology is quite low.
In conclusion, the differential circuit is very efficient for the purpose of the master
circuit, the numerous advantages of differential operation by far outweigh the possible
increase in the area.

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2.5 Block 3: Amplifier stage 2: Source

Figure 2.8: Suorce follower

This block has the terminal Voutof the circuit so it plays an important role in
ensuring the output spec of our circuit. In amplifier stage 1, we have achieved the
condition of differential input, anti-interference ability but again is not achieved, so in
this stage, we will focus on gain and output swing. The ideal voltage Vout would be
equalVDD/2 to have the largest output swing. Analysis of power supply indicates that,
to achieve a high voltage gain with limited supply voltage, the load impedance must be
as large as possible.
This block needs to be designed with the main function of having a large gain
factor, specifically the gain factor gm2 of amplifier stage 2 must be about 10 times
larger than gm1 of stage 1. Besides, because of creating a zero in the transfer function, a
compensation capacitor C1 is added as shown in Figure 2.8.
To summarize, this is a basic single stage-amplifier circuit so calculating for each
component is a key to have a good working circuit.

2.6 Calculatin the parameters for the circuit

Before entering the specific circuit design, I have set the expected parameters of
my circuit in table 2.1, then I will calculate with these parameters to get the value of
each component in the circuit.

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 Table 2.1: Expected parameters
Parameters Values
Maximum voltage (VDD) 1.2 V
Input signal amplitude (Vin) 0.6 V
INPUT
Bias current (Ib) 0.2 µA
Load capacitor (C0) 600 fF
Gain Bandwidth (GBW) 10MHz
OUTPUT Phase Margin (PM) ≥ 55°
Gain (G) ≥ 60dB
The transfer function of a circuit is defined as the ratio between Vout and Iin. For an
Op-Amp the transfer function is expressed as
Vout −g m1 R1 R 2 (g m2 + s. C0 )
=
Iin R1 C1 C0 (1 + g m2 R 2 )s2 + [(1 + g m1 g m2 R1 R 2 )C0 + g m2 R1 R 2 ]s + g m2
Where:
(gm1, R1) and (gm2, R2) are the gain and Ron of amplifier stages 1 and 2,
respectively
C1, C0 are the capacitors in figure 10.
Therefore the circuit contains a zero in the left half-plane, which can be chosen to
cancel one of the poles. As with the circuit of figure 10, this topology contains a zero
in the left half-plane and two poles. Using similar approximations, we compute the
poles and zero as.
1
P1 =
g m2 R1 R 2 C0
g m2
P2 =
C1
g m2
z=
C0
The equation for calculating Gain Bandwidth is illustrated as below
g m1
GBW =
2πC0
Based on the table 2.1: GBW = 10 MHz and C0 = 600 fF, so gm1 = 38 µ
The ratio between gm and the current Id in an amplifier is always from 10 to 15.
This ratio is chosen as 10, the value of Id1 will beapproximately
g m1 38
Id1 = = = 3.8 ≈ 4μA
10 10

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 Moreover, for an NMOS operating in a saturation region, the equation of the
relationship between gm1 and Id1 is

w
g m1 = √2μn Cox ( ) Id1
l 1

w g2
m1 382 1
→( ) = = ≈
l 1 2μn Cox Id1 2.1.300.4 2

w w
Following the same steps, the ratio ( ) for PMOS is ( ) ≈ 3
l 2 l 2

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 CHAPTER 3. DESIGNING AND SIMULATING

OPERATIONAL AMPLIFIER CIRCUIT

3.1 Design on Cadance

Based on the calculations about the size of the MOSFETs, we designed the circuit
with the parameters that illustrate in Figure 3.1. MOSFETs are taken from the library
“TSMC180nm”, power supply VDD, current source Ib and capacitors are taken from the
library “analoglib”. The differential input signal is simulated by two AC voltage
sources in the opposite phases.

Figure 3.1: Complete circuit topology

3.2 Simulation result

After designing, I proceed to run the simulation in AC mode and operating
frequency from 0 to 1 GHz. Then, when the simulation is completed, we plot graphs of
Gain and Phase Margin as shown in Figures 3.2 and 3.3 below.

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 Figure 3.2: Simulation result of Gain
According to the graph, we get the output of gainapproximately 77 dB so it has met
the requirements. This parameter needs to be as large as possible, the fact that our
circuit achieves such a great value is due to the approximation in the above calculation
results. Taking that approximation could make the gain smaller or larger but based on
personal experience I have customized those approximations to get a very good value.
A high gain circuit could be really useful in many applications.

Figure 3.3: Simulation result of Phase Margin

An important result in Figure 3.3 is that the red line above illustrates the correct
property of the transfer function. This line has two horizontal and two downward

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slopingsegments, corresponding to 3 explained state change pints, which are 2 poles
and 1 zero. Based on the graph, the value of Phase Margin with Gain Bandwidth 10.6
MHz is determined by
PM = (-132°) – (-180°) = 48°
These values are quite close to the output values set above, which is PM = 45° with
Gain Bandwidth 10 MHz.

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 CHAPTER 4. CONCLUSION

This report has provided the necessary knowledge about operational amplifiers
such as concepts, structure, properties, characteristics, applications and a specific
configuration. After that, the report represents the essential parameters, related
calculations and detailed analysis of aconfiguration of an Op-Amps before designing
it. In the content of the design, I have set the expected input and output parameters
myself so they are the basis for calculations. When I have the required parameters, the
Candance tool was used to simulate the circuit. The simulation results obtained are
very great, which proves that my circuit has a lot of potentials.
Although the results are not bad, this is just the simulation on the schematic,
the results obtained when layout this circuit may be very different. Therefore,
the next steps are layout the circuit, testing and adjustment after layout. When I
finally get a layout result that gives a reasonable value, I would order production
to have an actual chip.

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 REFERENCES

[1] “Design of Analog CMOS, Integrated Circuit” Textbook – Behzad Razavi –

McGRAW – HILL INTERNATIONAL EDITION, Electrical Engineering Series

[2] Design of Low-Power High-Gain Operational Amplifier, 2016 IEEE Computer

Society Annual Symposium on VLSI by Sanjay SighRajput, Ashish Singh,
Ashwani K.Chandel, Rajeevan Chandel

[3] Website: Op-amps cấu tạo và nguyên lý làm việc cơ bản - Blog Chia Sẻ Kiến
Thức Và Đam Mê Điện Tử (dammedientu.vn)

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