International Conference on Communication and Signal Processing, April 3-5, 2018, India
Design of Soft Edge Flip Flops for the
Reduction of Power Delay Product in Linear
Pipeline Circuits
Kosanam Manikanth and Ramesh S R

Abstract—In VLSI Design Static Timing Analysis (STA) is
carried out for timing closure of a design.Due to some process
variations statistical analysis should also be carried out for
accuracy.In this work, comparision between normal D-Flip Flop
and Soft Edge Flip Flops(SEFF) is done.SEFFs are a type of
Flip Flops created by modifying the conventional D-Flip Flops
in order to create a transparency window.The aim of this work
is to design a library of SEFFs so that the power and delay
are reduced for various voltage and frequency settings under
various scenarios by both deterministic and statistical delays.
Power and delay analyses are carried on SEFF and conventional
D-Flip Flop.This designed SEFF is utilized in a conventional
Linear Pipeline to reduce the overall Power Delay product (PDP)
of it. The simulations are carried out in Cadence Virtuoso for
gpdk90nm and gpdk45nm technology libraries. It is observed that
a power reduction of nearly 70 percent is observed from D-Flip
Flop to SEFF (at 137.40ps transparency window width and 1.2V).
A comparison between gpdk90nm and gpdk45nm is also done in
this work.
Index Terms—Cadence Virtuoso, Linear Pipeline, Low power,
Soft Edge Flip Flop, Static Timing Analysis
I. INTRODUCTION
W ITH the use of portable chargeable personal devices and
ultra low scale electronic peripherals, the requirement of
power minimal design has became important. Also more and
more power and heat problems are causing processor
failures.Due to the use of pipelines in high end processors,
power consumption and heating issues are becoming more.
The modern processors nowadays use high level of
pipelined circuitry in order to achieve maximum speed in the
modules.A speculative execution of hardware method called
pipeline gating is used to limit the rigorous speculation in the
pipeline.Here performance is degraded in the current day
processors[1].Clock power reduction technique was proposed
in [2] by using the clock gating technique.Here 40%-60%
power reduction is observed.The disadvantage is redundant
clock pulses are produced in this process.
Kosanam Manikanth is with the Department of Electronics and
Communication Engineering, Amrita School of Engineering, Coimbatore,
Amrita Vishwa Vidyapeetham, India. (e-mail: kmanikanth442@gmail.com).
Ramesh.S.R.is working as an Assistant Professor(Sr.Gr) with the
Department of Electronics and Communication Engineering, Amrita School
of Engineering, Coimbatore, Amrita Vishwa Vidyapeetham, India. (e-mail:
sr_ramesh@cb.amrita.edu).
978-1-5386-3521-6/18/$31.00 ©2018 IEEE
0148
Many methods have emerged to optimize the power of a
microprocessors pipeline such as pipeline gating, clock gating
[3] and voltage scaling [4].These techniques will not be
sufficient for high end processors.
A new approach to Dynamic Voltage scaling (DVS) called
RAZOR is proposed in [5] .This is a common principle for
static,domino and self redundant logics.A new approach called
RAZOR is implemented in [6] on a 64 bit processor in which
the energy saving is reported as 64.2 %.The performance is
reduced due to the error recovery mechanism.
The pipeline that is made of SEFFs is termed as a linear
pipeline.SEFFs have small window created due to the delayed
clock which provides time borrowing principle between the
pipeline stage delays.SEFFs are used for reducing the impact
of clock skew on the circuits yield [7].High speed domino
logics are used to reduce the delay of the circuits [8].The
hardware overhead is seen due to the extra logic present for
the high speed system.
To reduce the effect of process variations Monte carlo
simulations were done in [9] to obtain accurate values of the
variations and the statistical viability of the parameters.The
power increment is reported as 2.8 %.The idea of reducing the
PDP by using SEFF’s is seen in [10].The drawback in this
method is the area overhead for violation detection and
correction circuitry.
The probabilistic node activity estimator in LUT based
circuits and timing analysis for such circuits is proposed in
[11].An algorithm to estimate the effect of inverted
temperature dependance is proposed in [12].The voltage and
temperature are varied independently to estimate the timing
violations.Improved statistical static timing analysis using
refactored graphs is proposed in [13].The SSTA engine is
improved by using the refactored graphs of the netlist. In this
work, analysis of the problem of optimal power-delay pipeline
design is done by redesigning the flip flops into SEFFs and
using time borrowing concept.This method is based on the
concept of utilizing SEFF’s for slack passage and reducing the
error percentage in pipeline units.
In this paper Section-II describes the basic methodologies
used. Proposed work methodology is explained in Section-III.
Results and discussions are illustrated in Section-IV. Section-
V concludes the proposed work.
 II. BASIC TERMINOLOGIES

A. Timing conditions in a pipeline

A 2-stage linear pipeline is shown in Fig. 1. A linear
pipeline is described with the following conditions.
1) Stages must be linear , with zero feedback loops;
2) It has a fixed operation; and
3) Stages are divided by flip-flops(FF’s) which are clocked
with same clock signal. Fig. 3. Example of a Linear Pipeline
The flip flop sets are named as FF1,FF2,...,FFn.The delay of
combinational parts,D2Q,C2Q,are voltage dependent.Let The time borrowing principle can be observed from the
uspresume the pipeline is working under voltage vj. To ensure following waveforms shown in Fig. 4. The slack that is
normal working of the pipeline the following conditions (1) available due to the SEFF is passed to the preceding flip flop
and (2) are to be met. as shown in Fig. 4 in order to reduce the overall delay of the
(1) pipeline.
d dT  t
ij Clk , j
 t i : 1 d i d N
cq , ( i 1) j s ,ij

G ij
d t h,ij  t cq ,(i 1) j i : 1 d i d N (2)

Here di and δi denote the upper and lower threshold delays

of delay logic (DE) in stage i, Tclk denotes the time period of
the clock applied ts,i and th,i are setup and hold times of FF’s in
the ith FF-set whereas tcq,(i-1) denotes clock to Q (C2Q) delay
of FF’s in (i − 1)st FF’s-set. N indicates number of pipeline
stages.
Fig. 4. Time borrowing principle in a Linear Pipeline with SEFF’s [10]

III. WORK METHODOLOGY

Fig. 1. Simple Linear Pipeline
B. SEFF Design
The SEFF circuit diagram is shown in the Fig. 2. The major
difference between conventional D-Flip Flop and SEFF is its
transparency window in which the data is captured.The clock
is delayed by a delay logic DE. The DE is appropriately
modeled by using inverter chains
Fig. 2. Circuit of SEFF [10]
C. Linear Pipeline with SEFF
A general example of a linear pipeline is shown in the Fig.
3. The flip flops are replaced with SEFF’s to achieve time
borrowing in order to reduce power and delay parameters.
SEFFs are designed by creating a transparency window and
delay elements are designed by using the inverter chains.The
delay elements are responsible for creating the transparency
window.The clock of the SEFF is given to the delay element
and the delayed version of the clock is obtained and fed to the
SEFF circuit.
The master and slave parts present in the SEFF are
responsible for capturing the data during the window width.
The voltage levels are changed to obtain the different power
and delay values of the SEFF.Also, the inverter chains are
modeled in order to create different window sizes.
The Ts and Tk constraints are obtained from transistor level
simulations.These are dependent on the window sizes.So these
will be the linear functions of the window sizes.The
technology and process specific constants are derived from
Matlabcurve fitting toolbox.
The power consumption model of the SEFF is created and
the technology and process dependent constants are extracted
using Matlab curve fitting toolox.The linear pipeline is created
by keeping SEFF as stages as shown in Fig. 5. The soft edges
are created by using SEFF and the hard edges by normal Dflip
flops.

0149
 TABLE I
POWER PARAMETERS (IN μW) FOR DIFFERENT VOLTAGES,
TECHNOLOGIES AND WINDOW WIDTHS

Supply Voltage SEFF window width (in ps)

(in V) with two 41.36 65.53 89.95 113.70 137.40
technologies

gpdk90nm 25.85 04.56 02.04 02.06 02.05

0.8 gpdk45nm 01.95 0.970 01.02 01.07 0.430
gpdk90nm 37.24 07.09 03.15 02.77 02.68
0.9 gpdk45nm 03.68 02.65 02.71 02.78 02.48
gpdk90nm 48.61 12.04 05.34 03.73 03.69
1.0 gpdk45nm 05.94 07.08 05.49 05.58 05.66
gpdk90nm 62.18 20.22 09.50 05.04 04.95
1.1 gpdk45nm 08.63 11.55 09.26 09.36 09.46
gpdk90nm 80.00 22.17 16.70 07.38 06.99
1.2 gpdk45nm 29.49 17.02 17.14 14.12 14.24

TABLE-II depicts that D2Q difference of nearly 4.5ns from

gpdk90nm to gpdk45nm.

TABLE II
Fig. 5. Work Methodology
D2Q DELAY (IN NS) PARAMETERS FOR DIFFERENT VOLTAGES,
TECHNOLOGIES AND WINDOW WIDTHS
The slack passing and time borrowing are seen in the
pipeline.Power and delay of the pipeline are calculated and Supply Voltage (in SEFF window width (in ps)
compared with the normal pipeline circuits.The combinational volts) with two 41.36 65.53 89.95 113.70 137.40
technologies
parts of the pipeline are designed using buffers or inverters by
appropriately designing them to obtain the required delay and gpdk90nm 06.21 0.061 0.081 0.094 0.110
to meet the setup and hold time conditions. 0.8 gpdk45nm 0.010 0.075 0.075 0.075 0.075
gpdk90nm 03.98 0.057 0.068 0.077 0.089
0.9 gpdk45nm 0.010 0.113 0.067 0.067 0.067
IV. RESULTS AND DISCUSSIONS gpdk90nm 0.157 0.054 0.061 0.067 0.075
The schematic of the SEFF is shown in the Fig. 6 which is 1.0 gpdk45nm 0.014 0.010 0.057 0.060 0.060
gpdk90nm 0.104 02.51 04.81 04.81 04.93
done in Cadence Virtuoso. 1.1 gpdk45nm 0.010 0.010 0.063 0.055 0.055
gpdk90nm 0.096 04.42 04.81 04.80 04.93
1.2 gpdk45nm 0.011 0.009 0.009 0.050 0.050

TABLE-III demonstrates the C2Q variation of nearly 20ns

in gpdk90nm and gpdk45nm.

TABLE III
C2Q DELAY (IN NS) PARAMETERS FOR DIFFERENT VOLTAGES,
TECHNOLOGIES AND WINDOW WIDTHS

Supply Voltage (in SEFF window width (in ps)

volts) with two 41.36 65.53 89.95 113.70 137.40
technologies

gpdk90nm 24.99 0.070 23.86 23.87 23.89

0.8 gpdk45nm 0.002 0.091 0.092 0.092 0.092
Fig. 6. Schematic of SEFF
gpdk90nm 22.26 0.066 23.84 23.85 23.86
0.9 gpdk45nm 0.001 0.132 0.085 0.085 0.085
The power, D2Q, C2Q of SEFF and D-Flip Flop parameters gpdk90nm 22.67 0.065 23.84 23.84 23.85
in 90nm technology are shown in Table I-Table IV 1.0 gpdk45nm 0.003 0.010 0.080 0.081 0.081
gpdk90nm 22.62 01.23 20.19 20.20 20.20
respectively. 1.1 gpdk45nm 0.003 10.02 0.086 0.078 0.078
gpdk90nm 22.61 20.58 20.19 20.19 20.20
TABLE-I illustrates that as window size increases power 1.2 gpdk45nm 0.002 10.02 10.02 0.075 0.075
also gets increased.

0150
 TABLE-IV shows the different parameters obtained for D- REFERENCES
Flip Flop at different voltages and technologies (gpdk90nm [1] S. Manne, A. Klauser, and D. Grunwald, ”Pipeline gating: Speculation
and gpdk45nm). control for energy reduction,” in Proc. Int. Symp. Comput.
Architecture, 1998, pp. 132141.
[2] H.M.Jacobson, ”Improved clock-gating through transparent pipelining,”
TABLE IV
in Proc. Int. Symp. Low Power Electron. Des., Aug. 2004, pp. 2631.
D-FLIP FLOP PARAMETERS FOR DIFFERENT VOLTAGES AND
[3] H. Jacobson, P. Bose, Z. Hu, A. Buyuktosunoglu, V. Zyuban, R.
TECHNOLOGIES
Eickemeyer, L. Eisen, J. Griswell, D. Logan, B. Sinharoy, and J.
Tendler, ”Stretching the limits of clock-gating efficiency in server-class
Supply Voltage Different parameters of D-Flip Flop processors,” in Proc. High-Performance Comput. Architecture, 2005,
(in volts) with two Power (in D2Q Delay C2Q Delay pp. 238242.
technologies μW) (in ns) (in ns) [4] H. Partovi, R. Burd, U. Salim, F. Weber, L. DiGregorio, and D. Draper,
”Flow-through latch and edge-triggered flip-flop hybrid elements,” in
gpdk90nm 03.28 0.071 0.079 Proc. Solid-State Circuits Conf., 1996, pp. 138-139.
0.8 gpdk45nm 0.990 01.79 01.81 [5] D. Ernst, K. N. Sung, S. Das, S. Pant, R. Rao, P. Toan, C. Ziesler, D.
gpdk90nm 06.49 0.069 0.078 Blaauw, T. Austin, K. Flautner, and T. Mudge, ”Razor: A low-power
0.9 gpdk45nm 09.71 10.01 10.03 pipeline based on circuit-level timing speculation,” in Proc. Int. Symp.
gpdk90nm 11.65 0.068 0.079 Microarchitecture, Dec. 2003, pp. 718.
1.0 gpdk45nm 15.63 10.01 10.03 [6] S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, K. Flautner,
gpdk90nm 20.85 02.50 01.22 and T. Mudge, ”A self-tuning DVS processor using delay-error
1.1 gpdk45nm 22.01 10.00 10.02 detection and correction,” IEEE J. Solid-State Circuits, vol. 41, no. 4,
gpdk90nm 23.26 04.51 21.74 pp. 792804, Apr. 2006.
1.2 gpdk45nm 29.30 09.99 09.99 [7] K. Choi, R. Soma, and M. Pedram, ”Fine-grained dynamic voltage and
frequency scaling for precise energy and performance tradeoff based on
the ratio of off-chip access to on-chip computation times,” IEEE Trans.
Comput. Aided Des., vol. 24, no. 1, pp. 1828, Jan. 2005.
The linear pipeline with SEFF’s is designed with 137.40ps [8] D. Harris and M. A. Horowitz, ”Skew-tolerant domino circuits,” IEEE
window width and stage delays to be 150ps.It is reported that a J. Solid-State Circuits, vol. 32, no. 11, pp. 17021711, Nov. 1997.
power reduction of nearly 68% is observed from conventional [9] V. Joshi, D. Blaauw, and D. Sylvester, ”Soft-edge flip-flops for
improved timing yield: Design and optimization,” in Proc. Int. Conf.
linear pipeline to SEFF based pipeline with a overall delay of Comput.- Aided Des., Nov. 2007, pp. 667673.
96ns nearly. [10] M. Ghasemazar and M. Pedram, ”Optimizing the Power-Delay Product
in a Linear Pipeline by opportunistic time borrowing”, IEEE
V. CONCLUSION Transcations on Computer Aided Design of Integrated Circuits And
Systems,Vol. 30,No.10,October 2011.
A library of SEFF’s are designed both in gpdk90nm and [11] Ramesh.S.R, R.Jayaparvathy, ”Probabilistic Activity Estimator and
gpdk45nm technologies in Cadence Virtuoso to reduce the Timing Analysis for LUT Based Circuits , International Journal Of
Applied Engineering Research, Vol. 10, No.13,pp 33238-33242,August
overall power of a linear pipeline.Experimental results 2015.
demonstrated that there is nearly 70% decrease in the power [12] A. Dasdan and I. Hom, ”Handling inverted temperature dependence in
from normal D-Flip Flop to SEFF which are used in linear static timing analysis,” ACM Trans. Des. Autom. Electron. Syst., vol.
11, no. 2, pp. 306324, Apr. 2006.
pipeline circuits.The optimum power is obtained at 137.40ps [13] S.R.Ramesh,Jayaparvathy.R, ”Improved Statistical Static Timing
window width. Analysis using Refactored Timing Graphs,” Journal of Computational
and Theoretical Nanoscience,Vol. 13,No. 11,pp. 8879-8884,2016.

0151