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UNIT- 2 (Notes)

8051 FAMILY MICROCONTROLLER’S INSTRUCTION SET

2.1 ASSEMBLY LANGUAGE PROGRAMMING

 PROGRAM CONSISTS OF INSTRUCTIONS

 INSTRUCTION CONSISTS OF OPCODE (Type of operation) AND OPERANDS

 OPCODE IS REFFERED AS MNEMONIC

 MNEMONIC MEANS SHORTFORM OF INSTRUCTION IN ENGLISH LANGUAGE

 EACH INSTRUCTION HAS UNIQUE MNEMONIC

 OPCODE DEFINES SPECIFIC OPERATION ALLOWED BY CPU

 OPERAND DEFINES DATA ON WHICH OPERATION HAS TO PERFORMED

 OPERAND CAN BE A DATA OR ADDRESS

2.2 ADDRESSING MODES OF 8051

 IMMEDIATE

 DIRECT

 REGISTER

 REGISTER INDIRECT

 INDEXED

2.3 INSTRUCTIONS OF 8051

 DATA TRANSFER INSTRUCTIONS

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 ARITHEMATIC INSTRUCTIONS

 LOGICAL INSTRUCTIONS

 BULLION VARIABLE INSTRUCTIONS

 PROGRAM FLOW CONTROL INSTRUCTIONS

2.4 DATA TRANSFER INSTRUCTIONS

MOV A,Rn

MOV A,direct

MOV A,@ri

MOV A,#data

MOV Rn,A

MOV Rn,direct

MOV Rn,#data

MOV direct,A

MOV direct,Rn

MOV direct1,direct2

MOV direct,@ri

MOV direct,#data

MOV @Ri,A

MOV @Ri,direct

MOV @Ri,#data

MOV DPTR,#data

MOVC A,@A+DPTR

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MOVC A,@A+PC

MOVX A,@Ri

MOVX A,@DPTR

MOVX @Ri,A

MOVX @DPTR,A

POP Direct

PUSH Direct

XCH A,Rn

XCH A,Direct

XCH A,Ri

XCHD A,@Ri

2.4 ARITHEMATIC INSTRUCTIONS

ADD A,Rn

ADD A,direct

ADD A,@Ri

ADD A,#data

ADDC A,Rn

ADDC A,direct

ADDC A,@Ri

ADDC A,#data

DAA

DEC A

DEC Rn

DEC Direct

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DEC @Ri

INC A

INC Rn

INC Direct

INC @Ri

INC DPTR

MUL AB

DIV AB

SUBB A,Rn

SUBB A,direct

SUBB A,@Ri

SUBB A,#data

2.5 LOGICAL INSTRUCTIONS (Data manipulation Instructions)

ANL A,Rn

ANL A,direct

ANL A,@Ri

ANL A,#data

ANL Direct,A

ANL Direct,#data

ORL A,Rn

ORL A,direct

ORL A,@Ri

ORL A,#data

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ORL Direct,A

ORL Direct,#data

XRL A,Rn

XRL A,direct

XRL A,@Ri

XRL A,#data

XRL Direct,A

XRL Direct,#data

CLR A

CPL A

NOP

RL A

RLC A

RR A

RRC A

SWAP A

2.6 BULLION VARIABLE INSTRUCTIONS

ANL C,b

ANL C,b-

CLR C

CLR b

CPL b

CPL C

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ORL C,b

ORL C,b-

MOV C,b

MOV b,C

SETB C

SETB b

2.7 PROGRAM FLOW INSTRUCTIONS (Execution Transfer)

ACALL ADDR 11

CJNE A,direct,REL

CJNE A,#data,REL

CJNE Rn,#data,REL

CJNE @Ri,#data,REL

DJNZ Rn,REL

DJNZ Direct,REL

LCALL ADDR 16

AJNP ADDR 11

LJMP ADDR 16

SJMP REL

JMP @A+DPTR

JC REL

JNC REL

JB b,REL

JNB b,REL

JBC b,REL

JZ REL

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JNZ REL

RET

RETI

NOTES:

1. Direct means address of the internal RAM from 00-7FH & SFRs(80HFFH)
2. Rn means registers R0-R7 of selected bank
3. Ri means RO or R1 of selected bank. R0 & R1 are used for indirectly
addressing internal data RAM which is 00-7FAH in 8051 & 00-FFH in 8052
4. Data means 8bit or 16bit number depending on register width
5. b means addressable bit in internal RAM or SFR
6. ADDR 11 means short address of 11 bits .These are 11 LSBs of address.
5 MSBs are page number (0-31)
7. ADDR 16 means long address of 16 BITS from 0000 to FFFFH
8. REL means relative address which is sign value of -128 to +127

2.8 WAP TO MOVE N bytes FROM INTERNAL RAM TO EXTERNAL RAM

 ALGORITHM
o Internal RAM is from 00H-7FH. External RAM is from 0000H-FFFFH
o Access internal RAM through address pointer R0 or R1. Use MOV
instruction for access
o Access external RAM through address pointer DPTR. Use
MOV instruction for access
o Use byte counter to determine number of bytes to be transferred.
Initialize it to N to begin with
o Define address and byte count using EQU statements

 PROGRAM

o BYTCNT: EQU 08H

o IRAMADR: EQU 40H
o ERAMADR: EQU 6000H
o MOV R2,#BYTCNT
o MOV R1,#IRAMADR
o MOV DPTR,#ERAMADR
o BACK: MOV A,@R1
o MOVX @DPTR
o INC R1
o INC DPTR
o DJNZ R2,BACK

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o RET

2.9 WAP TO FIND NUMBER OF ZEROES IN A GIVEN BYTE

 ALGORITHM

o Check each BIT of the byte to be zero by transferring it to carry flag and
using conditional jump instruction
o Initialize BIT counter to 8
o Initialize zero count to zero
o Decrement bit counter after each check
o Repeat above operations till all bits are checked
o Increment zero count if bit is found to be zero

 PROGRAM (Accumulator has the byte to be tested)

o MOV R0,#OOH
o MOV R2,#08H
o BACK: RRC A
o JC NEXT
o INC R0
o NEXT: DJNZ R2,BACK
o RET

2.10 BRANCHING AND LOOPING

 INITIALIZE PARAMETERS(INPUT PROCESSING)

 PERFORM OPERATIONS (MAIN PROCESSING)
 PREPARE FOR NEXT STEP (OPERATION)
 CHECK IF OPERATIONS ARE TO BE REPEATED IF SO LOOP ELSE END

2.11 WAP TO FIND LARGEST NUMBER FROM ARRAY OF N 8-BIT UNSIGNED NUMBERS

 ALGORITHM

o Get first number and assume it to be the largest

o Compare it with next number, if not larger assign next number as
largest
o Repeat the above steps till all numbers are over
o Number of comparisons will be N-1. N being the numbers in the array

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 PROGRAM (Assume numbers are available in internal RAM and N is10)

o IRAMADR: EQU 40H

o CMPCNT: EQU 9
o LARGEST: EQU 3FH
o MOV R0,#IRAMADR
o MOV R2,#CMPCNT
o MOV A,@R0
o MOV B,A
o BACK: INC R0
o MOV A,@R0
o CJNE A,B,NEQ
o SJMP NEXT
o NEQ: JC NEXT
o MOV B,A
o NEXT: DJNZ R2,BACK
o MOV LARGEST,B
o RET

2.11 WAP TO CONVERT TWO ASCII DECIMAL DIGITS TO TWO DIGIT PACKED BCD
NUMBERS. CHECK IF IT IS ODD OR EVEN AND STORE ZERO OR ONE IN BIT ADDRESSABLE
RAM

 ALGORITHM

o ASCII digits are from 30H to 39H

o Make higher nibble to zero for converting it to decimal digit. This can be
done by logically ANDing with zero FH
o Pack digits by positioning Ten’s digit as higher nibble and logically
ORing with unit digit
o Check for odd or even by moving LS bit to carry flag and checking it for
One or Zero

 PROGRAM
o UADR: EQU 40H
o TADR: EQU 41H
o MOV A,TADR
o ANL A,#OFH
o SWAP A
o MOV R2,A
o MOV A,UADR

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o ANL A,#0FH
o ORL A,R2
o RRC A
o MOV 0,C
o RET

2.11 WAP TO GENERATE TIME DELAYS USING TIMERS OFF 8051

 ALGORITHM

o Timer zero is used in mode 1 (16 bit Timer)

o It generates fixed time delay T1
o It is run for N cycles
o Timer 1 is used in mode 1 (16 bit timer)
o It generates a time delay of T2
o It is run for M times
o Total time delay will be T1*N+T2*M

o TCON REGISTER FORMAT

D7 D0

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

o TMOD REGISTER FORMAT

D7 D0

Gate C/T-- M1 M0 Gate C/T- M1 M0

<-------------------- Timer 1------------> <-------------------- Timer 0 ------------>

 PROGRAM

o TCON: EQU 88H

o TMOD: EQU 89H
o TL0: EQU 8AH
o TL1: EQU 8DH
o TH0: EQU 8CH
o TH1: EQU 8DH
o TR0: EQU 8CH
o TF0: EQU 8DH
o TR1: EQU 8EH
o TF1: EQU 8FH

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o CNT0: EQU 40H

o CNT1: EQU 80H
o MOV R2,#CNT0
o MOV R3,#CNT1
o MOV TCON#00
o START: MOV TMOD#01
o MOV TL0,#00
o MOV TH0,#00
o SETB TR0
o SELF: JNB TF0,SELF
o CLR TR0
o CLR TF0
o DJNZ R2,START
o AGAIN: MOV TMOD,#10H
o MOV TL1,#00
o MOV TH1,#20H
o SETB TR1
o SELF1: JNB TF1,SELF1
o CLR TR1
o CLR TF1
o DJNZ R3,AGAIN
o RET

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