LATCHES & FLIP FLOPS

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 Sequential Circuits

Inputs Outputs
Combinati
onal
Storage Logic
Elements
Next
State State

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 Latches and Flip flops

Latches and flip-flops are the basic elements for storing information.
A latch or flip-flop can store one bit of information.

Output follow the input as long as the clock

clk
input is asserted ( high/low)

Flip flops are circuits where the output

clk follows input only during the
clock transitions (rising edge/falling edge)

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Basic Concept of Storage ( Memory)

 It should be able to hold a value

 One should be able to read the value stored

 One should be able to change the value.

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Basic Concept of Storage
(one bit memory)
Q

Q’ Q Q’

 The circuit remembers Q (never changes as long as powered on)

as well as Q’.
 We can read Q by checking the output.

 You can’t decide the value!

BITS Pilani, Pilani Campus

 S R Latch

R
Q
S R Q
1 0 1
Q’
S 0 0 1

0 1 0
Q next = (R + Q’ current)
0 0 0
Q’next = ( S + Q current)
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 S R Latch

R
Q
S R Q
1 0 1
Q’
S 0 1 0

0 0 No change
Q next = (R + Q’ current)
Not
1 1 recommended
Q’next = ( S + Q current)
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 NAND Based Latch

S S R Q
Q
0 1 1
1 0 O
1 1 No Change

R Q’ 0 0 Not
Reccomm

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 CLOCKED SR LATCH
S
Q

CLK

Q’
R
CLK S R Q
0 X X No change
1 0 0 No change
1 0 1 0
1 1 0 1
1 1 1 Not to apply
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R S ’
Q S’
Q Q

CLK
Q’
Q’
S R’ Q’
R

S R Q CLK S R Q
S’ R’ Q
0 0 no change
0 1 1 0 X X No change
0 1 0
1 0 O 1 0 0 No change
1 0 1
1 1 No Change 1 0 1 0
1 1 NR
1 1 0 1
1 1 1 Not to apply.

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 D LATCH

D S’
Q

CLK

R’ Q’
CLK D Q
0 X No change
1 0 0
1 1 1

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K R Q

CP

Q’
J S

BITS Pilani, Pilani Campus

K R Q

CP

Q’
J S

RACE AROUND CONDITION

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BITS Pilani, Pilani Campus
FLIP FLOPS

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 Latches Vs Flip-flops

Latches are “transparent” (any change on the inputs is

seen at the outputs immediately).
This causes synchronization problems!
Solution: use latches to create flip-flops that can
Respond ONLY on clock transitions

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 Master Slave Configuration

D D Qin S Q
CLK C Q C
Q’in R Q’

What happens when CLK is logic 0

Master enabled and slave disabled
Slave maintains the output

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 Master Slave Configuration

D D Q S Q
CLK C Q C
Q’ R Q’

When CLK is logic 1 Master disabled and Slave enabled.

D CLK Q(t+1) Comments

Positive edge triggered Flip flop 1

0


1
0
Set
Reset

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J K Flip Flop

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 J K Flip flop

J Q J K CLK Q(t+1) Comments

0 0  Q(t) No change
0 1  0 Reset
K Q 1 0  1 Set
1 1  Q(t)' Toggle

Characteristic Table

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K Q(t)
00 01 11 10
J
0 0 1 0 0

1 1 1 0 1

Characteristic equation
Q(t+1) = J.Q‘(t) + K'.Q(t)

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 Application: Frequency Division

Q T Q(t+1)
T J Q 0 0 0
CLK 0 1 1
1 0 1
K Q'
1 1 0
High High
J QA J QB
CLK
K K

CLK

QA
QB
Divide clock frequency by 4.

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