3232 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO.
10, OCTOBER 2012
A Broadband Injection-Locking Class-E
Power Amplifier
Chi-Hsien Lin and Hong-Yeh Chang, Member, IEEE
Abstract—This paper presents a fully integrated two-stage in-
jection-locking class-E power amplifier (PA) using a GaAs 0.5- m
enhancement- and depletion-mode pseudomorphic high-electron
mobility transistor (E/D-mode PHEMT) process. The injection-
locking concept is used in this design, and the PA works as an os-
cillator whose output voltage is tuned at the input frequency. The
proposed PA achieves high power-added efficiency (PAE) and high
power gain. An autonomous circuit is also employed for the sta-
bility analysis, and the design procedure is summarized for the cir-
cuit implementation. By employing this design technique, the pro-
posed injection-locking class-E PA under continuous-wave signal
achieves a peak PAE of 59% at an output power of 26.6 dBm from
a 6-V dc supply voltage. With a Gaussian minimum-shift keying
(GMSK) modulation input signal at 3.5 GHz, the measured max-
imum PAE is 57% at an output power of 26.7 dBm. The measured
error vector magnitude is within 2.2% over all of the output power
level, and the adjacent channel power ratio is better than 40 dBc.
Under a 64-QAM modulation signal with class-AB operation, the
proposed PA achieves a peak PAE of 55% with an output power of
27 dBm.
Index Terms—Class-E power amplifier (PA), GaAs PHEMT,
monolithic microwave integrated circuit (MMIC), RF/microwaves,
stability analysis.
I. INTRODUCTION
D EMAND for wireless communication systems has been
growing in recent years. The power amplifier (PA) is a
crucial component in a radio frequency (RF) transceiver to de-
liver an appropriate output power level for driving the antenna
[1]. Since the PA has a significant dc power consumption, the
efficiency is a very important specification. A high-efficiency
PA is required for the wireless communication systems due to
the limitation of the battery capacity. In general, the PA can be
widely classified as a transconductance PA or a switching PA
according to the behavior of the active device [2]. The transcon-
ductance PA includes class-A, -AB, -B, and -C, where the active
device acts as a current source controlled by the input signal.
The switching PA includes class-D, -E, and -F, where the ac-
tive device operates as a switch to modulate the output voltage
and current waveforms, and yield high efficiency. Moreover, the
Manuscript received June 15, 2012; revised July 04, 2012; accepted July
05, 2012. Date of publication September 04, 2012; date of current version
September 27, 2012. This work was supported in part by the National Science
Council of Taiwan under Grant NSC 99-2221-E-008-097-MY3, Grant NSC
100-2221-E-008-118, and Grant NSC 101-2221-E-008-072-MY3, and by the
Chip Implementation Center (CIC), Taiwan.
The authors are with the Department of Electrical Engineering, National Cen-
tral University, Taoyuan 32001, Taiwan (e-mail: hychang@ee.ncu.edu.tw).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2012.2209456
0018-9480/$31.00 © 2012 IEEE
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output power of the switching PA can be compared with or is
higher than that of the class-A or AB with the same active de-
vice [3], [4].
Much recent research has been focused on the switching PAs
and oscillators [4]–[13], especially the class-E PA, because of its
design simplicity and high-efficiency characteristic [4]. For the
class-E PA design, large active device sizes are typically chosen
to provide sufficient output power level. Although the large
device can reduce the turn-on resistance , the input and
output capacitances increase, which increases the driving cur-
rent. Moreover, since the active device is operated as a switch,
the gate voltage is biased at the threshold voltage. Therefore,
the stringent input driving requirement also becomes a critical
issue for the class-E PA design.
In previous studies, Tsai et al. [7] and many other authors
[8]–[10] adopted a mode-locking technique to reduce the input
driving power. The concept of the mode-locking technique was
proposed in [7], and a 1.9-GHz 1-W class-E PA with a power-
added efficiency (PAE) of 48% has been demonstrated. Oh et al.
[11] and Paek et al. [12] employed the class-E power oscillator
and the injection-locking technique to substantially mitigate the
required driving power. A small-signal equivalent circuit was
proposed to predict the boundary condition for the oscillation
[11], and an injection-locking class-E PA achieves an output
power of 11 dBm with a drain efficiency of 49.3%. Although
these techniques for reducing the input driving power have been
investigated, the phenomena of these techniques in various input
levels are still difficult to predict and estimate.
In this paper, an autonomous circuit [14], [15] is employed
to predict the injection-locking phenomena, and a systematic
design procedure for the injection-locking class-E PA is devel-
oped. Through the stability analysis with the autonomous cir-
cuit, the design circuit can be easily estimated and simulated
using commercial harmonic-balance (HB) software and make
the design more efficient. Moreover, the analysis technique not
only provides a fast way to increase the accuracy, but also re-
duces the analysis complexity, in comparison with the complex
formulas in [11] and [15]. In addition, the component values of
the topology and the injection-locking phenomena can be easily
evaluated and optimized by the graphical representation of the
admittance. The simulation of the injection-locking PA agrees
with the measurement. Compared with the previous class-E PA
design in [16], the gate inductance of the output stage in
Fig. 1 is adjusted using the autonomous circuit to achieve the
startup oscillation condition with the low input power level. The
proposed PA under continuous-wave (CW) signal achieves a
power gain of 29.3 dB, a PAE of 55%, and a saturated output
power of 27.7 dBm. Also, the proposed PA with Gaussian min-
imum-shift keying (GMSK) and 64-QAM modulation signals
still demonstrates high efficiency and good modulation quality.
LIN AND CHANG: BROADBAND INJECTION-LOCKING CLASS-E POWER AMPLIFIER 3233

Fig. 1. Basic circuit of the class-E PA.

The PA has been successfully developed using the proposed de- Fig. 2. Simulated waveform of the normalized switch voltage and current.
sign methodology, and it is suitable for the various digital mod-
ulation signals due to its superior performance.
This paper is organized as follows. In Section II, the funda-
mental concepts of the conventional and the injection-locking
class-E PAs are presented. The stability analysis for the oscilla-
tion condition is also discussed, and a systematic design proce-
dure for the injection-locking PA is developed. In Section III, the
design and implementation of the proposed injection-locking
class-E PA is described. The experimental results and discus-
sions are presented in Section IV. Conclusion is provided in
Section V.

II. INJECTION-LOCKING CLASS-E PA ANALYSIS

A. The Class-E PA With Finite Inductance

The basic circuit of the class-E PA is shown in Fig. 1, where Fig. 3. Simulated normalized shunt capacitance. and normalized load re-
the transistor is operated as a switch. When the switch is turned sistance versus the RFC inductances .
off, the voltage across the switch increases since the current
flows through the shunt capacitance . When the switch
is turned on, the voltage across the switch is close to zero, can be observed that the shunt capacitor and load resis-
i.e., zero-voltage switching (ZVS) and zero-voltage derivative tance increase as the RFC inductance decreases.
switching (ZVdS). The simulated waveforms of the normalized The simulated normalized shunt capacitance and normal-
switch voltage and current are depicted in Fig. 2, which is sim- ized load resistance versus the RFC inductance
ulated using an ideal switch and lossless matching network. It are plotted in Fig. 3, where the simulated results are normal-
can be clearly seen that the nonzero switch voltage and current ized with respect to the maximum value. If the parallel induc-
do not occur simultaneously. As a result, the class-E topology tance is smaller than 20 nH, the shunt capacitance
is known as soft-switching [5]. To achieve high efficiency, the rapidly increases. Therefore, the larger device size can be se-
voltage across the transistor should be minimized when the lected for smaller turn-on resistance due to the larger shunt
transistor is conducting current or minimizing the conduction capacitance . In addition, the efficiency can be improved
current when a voltage exists across the transistor [17]. because of the smaller turn-on resistance. The output matching
In Fig. 1, the RF choke (RFC) can be infinite or fi- network is usually designed as a low-pass network to match the
nite inductance. If an infinite inductance is chosen, the PA is fundamental impedance of the maximum RF output power. The
close to the ideal class-E operation. However, a finite induc- power loss of the output match can be further reduced by in-
tance achieves higher efficiency at high output power [18]. The creasing the load resistance .
phenomenon can be observed using the equation of the shunt In general, a single-section inductance–capacitance (LC)
capacitance as follows [5]: matching network for impedance transformation as shown in
Fig. 4 can be employed in the output matching network in
Fig. 1, where , , and are the parasitic resis-
tance of the shunt capacitance, the parasitic resistance of the
series inductor, the terminal resistance (or system impedance),
(1) and and are the capacitance of the shunt capacitor
and the inductance of the series inductor, respectively. The
where is frequency, is the load resistance, is the loaded simple circuit model of the LC network can be used to anal-
quality factor, and is the RFC inductance. From (1), it ysis the power loss for the impedance transformation. The

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3234 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 10, OCTOBER 2012

Fig. 5. Equivalent circuit of the class-E PA.

The series-tuned network of the class-E network

resonates at the fundamental frequency, and the output current
becomes a sine wave through the series-tuned network.
Since the series-tuned network resonates at the operated fre-
quency, the excessive reactance serves to adjust the phase of
Fig. 4. Simulated power transfer efficiency versus with various series the series network. Therefore, the high PAE can be obtained at
inductances at 3.5 GHz. the fundamental frequency. The excessive reactance can be
positive (inductance), negative (capacitance), or zero depending
on the class-E operation [20]. The detail design of the class-E
parasitic resistance of the shunt capacitance can load network can be found in [5] and [20].
be ignored since the loss of the capacitor is very small. As- To achieve high output power, the large device and power-
sume the impedance-transformation network is operated at the combining technique are generally preferred in the PA design.
impedance matching condition. The power transfer efficiency This implies that a significant amount of input driving power
of the matching network is defined as the ratio between the is required. Therefore, the stringent input driving requirement
input RF power and the RF output power to delivered to the becomes a critical problem. To mitigate these problems, the in-
load [19], i.e., jection-locking technique is used in our PA design.

B. Injection-Locking Class-E PA
The concept of the injection-locking technique is similar
to the mode-locking technique. The mode-locking technique
makes the output of the PA tuned at the input signal frequency.
Some class-E PAs [7]–[10] have been demonstrated utilizing
the mode-locking technique to reduce the input driving power
and achieve high power gain. However, this mode-locking tech-
(2) nique is based on a cross-coupled structure and not suitable for
the single-end topology. Although the differential output can be
converted to single-ended output using a balun or transformer,
where the performance decreases due to the passive components.
The concept of the injection-locking technique was adopted
(3) in a PA by Oh [11], and the injection-locking class-E PA
achieves high PAE with low driving power. Oh’s approach is to
The simulated power transfer efficiency versus is plotted use the small-signal equivalent circuit to predict the boundary
in Fig. 4 with various series inductances at 3.5 GHz. condition of the oscillation, and the derivation of the oscillation
increases with . With a certain , increases as condition can be obtained. The equivalent circuit of the class-E
decreases. In general, a multisection LC network is used for PA is shown in Fig. 5, where the series-tuned network resonates
a smaller load resistance , especially for high-power de- at the fundamental frequency. All the components are assumed
sign with large gate periphery. However, a few inductors occupy to be lossless. The impedance at the input can be derived as
large chip area and make layout more complex, thus resulting in follows:
lower quality factor. The drain efficiency of the class-E PA can
be expressed as [18] (5)

where is the input impedance of the gate terminal and is

(4) expressed as

(6)
The drain efficiency increases as the ratio of decreases.
Moreover, the drain efficiency can be enhanced by increasing
and is
the load resistance . Therefore, the proposed class-E PA is
designed using a finite inductance of 5 nH with a higher
(7)
load resistance to enhance the efficiency.

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LIN AND CHANG: BROADBAND INJECTION-LOCKING CLASS-E POWER AMPLIFIER 3235

Fig. 6. Block diagram of the auxiliary generator in an oscillator circuit.

Fig. 7. Simulated conductance and susceptance at the node versus fre-

quency with various input powers between 4 and 12 dBm.

To satisfy the startup oscillation condition at the gate terminal,

the real part of must be negative. The negative resistance
is used to compensate for the losses in the circuit. Note that, al-
though the injection-locking class-E PA works like an oscillator,
the class-E operation at the drain terminal is still satisfied.
Fig. 8. Phenomenon of the injection-locking class-E PA with and without .
The startup oscillation condition can be easily obtained (a) Simulated admittance plots with an input power of 10 dBm. (b) Simulated
through the small-signal equivalent circuit. However, the phe- output power versus input power.
nomena of the injection-locking are difficult to predict and
estimate in various input levels, as well as the estimation of the
parasitic components in the large signal. Therefore, we adopt where the is the generator’s voltage, is the phase of
the autonomous circuit [14], [15] to analyze and simulate the auxiliary generator, and is the fundamental current of the
oscillation condition in various input levels. In Section II-C, generator.
the autonomous circuit is employed in the stability analysis and For the stability analysis, the startup oscillation condition
to estimate the oscillation condition of the PA. is applied to the admittance function at the node . The
admittance (8) can be plotted for different values of and
C. Stability Analysis , with the real and imaginary parts of the admittance
Based on the autonomous circuit, a systematic design pro- as the and axes. For the startup oscillation condition,
cedure is developed for the simulation of the injection-locking and must be satisfied. The oscilla-
class-E PA. The block diagram of autonomous circuit is shown tion will continue if . The oscillation eventually
in Fig. 6, which consists of a linear network, a nonlinear net- reaches a steady state, which occurs when the loop resistance
work, and an auxiliary generator (AG) with an ideal bandpass is zero. Therefore, the admittance function should be zero
filter (BPF) in series. The AG operates at the input frequency for the stable oscillation [21], that is,
of the class-E PA (i.e., ), and only the fundamental
signal of the AG passes the BPF. The AG is connected to the
(9)
gate terminal. From Fig. 6, the admittance at node can be ex-
pressed as [14] and

(10)

As described above, the oscillation can be easily simulated and

(8) estimated through the graphical representation of the admit-

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3236 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 10, OCTOBER 2012
Fig. 9. Schematic of the two-stage injection-locking class-E PA. The AG with an ideal BPF inside the dotted box is not a part of the PA, and it is used for the
stability analysis.
tance. Since the nonlinear network already contains the input
power term, this method is suitable for various input levels to
determine the oscillation condition. When the frequency of the
auxiliary generator is the same as the oscillation frequency, there
is a constant phase shift between the input signal and the oscil-
lator [14]. Thus, the phases of and depend on the phase
of the AG. To simply the analysis in the PA design, we let the
phase of the AG be zero for the condition without injection.
To verify the technique of the stability analysis in the injec-
tion-locking class-E PA design, the autonomous circuit is intro-
duced into the class-E PA in Fig. 1, which shows the basic circuit
of the class-E PA with the AG and ideal BPF. in Fig. 1 corre-
sponds to the linear network in Fig. 6, and the other correspond
nonlinear network. Based on the stability analysis, the oscilla-
tion condition is applied to the admittance at the node in
Fig. 6. The simulated conductance and susceptance at the node
in Fig. 1 versus frequency are plotted in Fig. 7 with various
input powers between 4 and 12 dBm. The startup oscillation
condition exists when the input power is higher than 6 dBm.
Then, the condition must be satisfied at the steady-state
oscillation. Using the above described approach, the oscilla-
tion condition can be observed from the admittance trajectories
shown in Fig. 8(a), where the solid line is for 0.3 nH, and
the dashed line is without . It can be observed that the dashed
line does not cross the origin or the imaginary part is never zero,
and the oscillation condition does not exist. Therefore, the gate
inductance is designed to provide the properly oscillating
conditions, that is the condition of . Fig. 8(b) shows
the output power versus input power, and this is in agreement
with the simulated admittance plots in Fig. 8(a). As expected,
the phenomenon of the injection-locking can be efficiently pre-
dicted through the stability analysis based on the HB simulator.
Moreover, the analysis technique not only provides a fast way to
increase the accuracy, but also reduces the analysis complexity.
The design flow of the broadband injection-locking class-E
PA is carried out under the following steps.
Step 1) Choose a proper device size based on design spec-
ifications. Since the transistor of the class-E PA is
operated as a switch, the gate voltage is biased at
the threshold voltage.
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Step 2) Use I–V curve for dc biasing selection, when the de-
vice is off, the peak drain voltage can be 3.56 times
the dc supply voltage due to the class-E operation
[5]. For the finite RFC inductance, the peak drain
voltage stress can be 2.5 times the dc supply voltage
[18].
Step 3) For a given dc supply voltage and required output
power, the load impedance can be obtained
from [5].
Step 4) For certain load impedance, the design values of the
output network can be obtained from [5]. To achieve
broad bandwidth, a reactance compensation tech-
nique can be employed in the output matching net-
work of the PA design. The detail design procedure
of the broadband class-E with the reactance com-
pensation technique can be seen in [16].
Step 5) Use the autonomous circuit to check the oscillation
condition at the gate terminal. If the oscillation con-
dition does not occur, adjust the output network and
. Note that the class-E operation at the drain ter-
minal should be satisfied or the efficiency decreases.
Step 6) Use conjugate matching for the input network to
achieve high power gain.
III. MMIC DESIGN AND IMPLEMENTATION
The proposed two-stage injection-locking class-E PA is
designed using a GaAs 0.5- m enhancement/depletion-mode
pseudomorphic high-electron mobility transistor (E/D-mode
PHEMT) process provided by the WIN Semiconductors Cor-
poration. The E-mode PHEMT device is adopted for the circuit
design due to single dc power supply. The maximum oscillation
frequency of an E-mode device is about 70 GHz, and
the unity gain frequency is about 35 GHz. The breakdown
voltage is typically 15 V, and the peak of transconductance is
500 mS/mm. Two metal layers are available for the intercon-
nection. The metal–insulator–metal (MIM) capacitor with a
unit capacitance of 600 mm , the thin-film resistor with a
unit resistance of 50 , and the spiral inductor are available
in the MMIC process [22].
LIN AND CHANG: BROADBAND INJECTION-LOCKING CLASS-E POWER AMPLIFIER 3237

The schematic of the two-stage injection-locking class-E

PA is shown in Fig. 9. Following the design procedure in
Section II-C, the design of the two-stage injection-locking
class-E PA can be carried out in following steps. The first
step is to design a conventional common-source class-E PA.
Since the finite RFC inductance is adopted in this work, the
peak drain voltage stress should be lower than 2.5 times the dc
supply voltage. With a dc supply voltage of 6 V and an output
power of 27 dBm, the load resistance is 27 based on
the load-line calculation. To achieve broadband class-E PA,
the component values of the class-E load network with the
reactance compensation technique are obtained from [16]. The
output matching network is designed as a low-pass network
to match the output impedance. The drive stage is operated in
the class-AB mode for high efficiency and high gain. The input
and the inter-stage networks are designed using the conjugate
matches for high power gain. For the input and the inter-stage
matches, two multi-selection LC networks are designed in the
low constant- region to achieve broad bandwidth.
To observe the injection-locking phenomenon, the AG with
an ideal BPF shown in Fig. 9 is introduced into the gate ter-
minal of the output stage for the analysis of the oscillation con-
dition. Based on the stability analysis, the oscillation condition
can be observed from the admittance plots as shown in Fig. 10.
To satisfy the oscillation condition, the gate inductance of
the output stage is designed as in Fig. 1. Fig. 10(a) shows
the phenomenon of the injection-locking class-E PA, where the
stable oscillation occurs for a certain range of the . The phe-
nomenon of the injection-locking with various input levels also
can be estimated as shown in Fig. 10(b). When the input power
is increased 12 dBm , the transition from the stable ampli-
fier to the injection-locking regime is due to the existence of the
oscillation condition. Since the real part of the admittance does
not reach zero as the PA is without input signal, the oscillation
condition cannot be satisfied. Thus, the PA does not oscillate
without input signal. Fig. 10(c) shows the output power versus
input power and various values of , and this is in agreement
with the simulated admittance plots in Fig. 10(a).
Since the proposed injection-locking class-E PA performs as
an injection-locking oscillator, the locking range can be esti-
mated as follows [23]:

(11)

where

(12)
Fig. 10. Phenomenon of the injection-locking class-E PA. (a) Simulated ad-
mittance plots with an input power of 0 dBm for various values of . (b) Sim-
ulated admittance plots with an of 0.5 nH for various levels of input power.
and is the injection power, is output power of the (c) Output power versus input power with various values of .
oscillator, is the oscillation frequency, and is the ex-
ternal quality factor. The locking range increases with the in-
jection power, but it decreases with the external quality factor. Finally, the in-band bypass capacitor is included in the
With a certain injection power, the locking range is limited by circuit to enhance the isolation between RF and dc, and reduce
the external quality. However, the external quality has been de- the influence of low-frequency noise sources and the possibil-
termined by the design of the class-E PA. Therefore, the locking ities of oscillations due to the biasing networks. The passive
range under the oscillation condition can be extended by in- components, including transmission lines, MIM capacitors, and
creasing the injection signal. spiral inductors, are all simulated with a full-wave EM simulator

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3238 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 10, OCTOBER 2012
Fig. 11. Chip photograph of the two-stage injection-locking class-E PA with a
chip size of 2 2 mm .
[24]. The chip photograph of the two-stage injection-locking
class-E PA is shown in Fig. 11 with a chip size of 2 2 mm .
IV. MEASUREMENT RESULTS AND DISCUSSIONS
A. Output Power and Efficiency
The measurement of the two-stage injection-locking class-E
PA are performed via on-wafer probing. The RF input signal is
generated from an Agilent E8257D analog signal generator, and
the output spectrum is measured using an Agilent E4448A spec-
trum analyzer. The drain dc voltages for the driver and output
stages are 3 and 6 V, respectively. The gate dc voltages of driver
and output stages are both biased to a threshold voltage (Vt) of
0.2 V.
The measured output power and power gain versus input
power at 3.5 GHz are shown in Fig. 12. The proposed PA
demonstrates an output power of 24.3 dBm, a peak power gain
of 29.3 dB and a saturated output power of 27.7 dBm. The PAE
versus input power is plotted in Fig. 13, and the maximum PAE
is 59% with an input power level of 2 dBm. From Figs. 12
and 13, it is clearly seen that the injection-locking phenomenon
occurs above an input power of 7 dBm. As compared with
the conventional class-E PA [16], the input driving requirement
is significantly reduced using the injection-locking technique.
When the two-stage class-E PA is locked at the input signal of
the same frequency, the output power remains approximately
constant with various input power. Moreover, the PAE de-
creases slightly with increasing the input power.
Fig. 14 shows the measured output power, power gain and
PAE versus dc supply voltage with an input power level
of 4 dBm. The PAE is higher than 51% when the dc supply
voltage is from 3 to 6.5 V. As expected, the characteristic
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Fig. 12. Simulated and measured output power and power gain versus input
power at 3.5 GHz.
Fig. 13. Simulated and measured PAE versus input power at 3.5 GHz.
of the switching PA, the PAE and drain efficiency (DE) are al-
most constant over most of the output power level [7]. How-
ever, the PAE has a slight reduction below a dc supply voltage
of 3 V, because the definition of the PAE is dominated by the
input power. At a dc supply voltage of 6 V, the PAE is about
55% with an output power of 26.5 dBm. The measured locking
ranges versus frequency with various input powers are shown in
Fig. 15, and the locking range is determined by the input power
level. As the input power level increases, the locking range in-
creases [23]. With an input power of 4 dBm, the output power
is higher than 22 dBm for a locking frequency range from 3.3
to 3.7 GHz. Moreover, the measured locking range of the pro-
posed PA can be up to 900 MHz with an input power level of
0 dBm.
B. GMSK Modulation Signal
To verify the potential of the two-stage injection-locking
class-E PA in digital communication applications, a Gaussian
minimum-shift keying (GMSK) modulation signal with a
symbol rate of 270.833 kbps is adopted. The GMSK is suit-
able for the switching PA because of the continuous-phase
frequency-shift keying modulation scheme. The GMSK mod-
ulation signal is generated using an Agilent E4438C vector
LIN AND CHANG: BROADBAND INJECTION-LOCKING CLASS-E POWER AMPLIFIER
Fig. 14. Measured output power, power gain and PAE versus dc supply voltage.
with an input power of 4 dBm.
Fig. 15. Measured locking ranges versus frequency with various input powers.
Fig. 16. Measured output power, gain, and PAE versus input power with the
GMSK modulation signal at 3.5 GHz.
signal generator. All of the dc bias conditions are the same as
the measurements in Section IV-A.
The measured output power, gain, and PAE versus input
power with the GMSK modulation signal at 3.5 GHz are plotted
in Fig. 16. The measured output power achieves 25.7 dBm with
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3239
Fig. 17. Measured (a) constellation diagram, where the measured EVM is
0.75%, and (b) modulation output spectrum, where the measured average
channel output power is 26.7 dBm.
Fig. 18. Measured EVM versus output power for the GMSK modulation.
a peak gain of 31.6 dB, and the maximum average channel
output power is 27 dBm. The maximum PAE is 57% with
an output power of 26.3 dBm and a power gain of 29.6 dB.
The measurement results, including the modulation output
spectrum and constellation diagram, are shown in Fig. 17 with
an input power level of 0 dBm. The PA features a maximum
error vector magnitude (EVM) of 0.8%, an amplitude error of
0.1% and a phase error of 0.6 . We assume that the channel
spacing and adjacent channel bandwidth are both 200 kHz, and
the measured adjacent channel power ratio (ACPR) is better
3240 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 10, OCTOBER 2012
Fig. 19. Measured EVM versus frequency with various input powers.
Fig. 20. Measured output power and PAE as a function of frequency with CW
signal under the class-AB operation.
Fig. 21. Measured power gain and drain efficiency as a function of output
power with the 64-QAM modulation signal at 3.5 GHz.
than 40 dBc. Fig. 18 shows the measured EVM versus output
power at 3.5 GHz. The EVM is within 2.2% over all of the
output power level. The measured EVM is better than 0.8%
at an output power level of higher than 0.5 W. The measured
EVM versus frequency is plotted in Fig. 19 with various input
powers, where the EVM is within 1.5% from 3.1 to 3.9 GHz.
As the input power is 6 dBm, the measured EVM at 3.3 GHz
increases due to the input sensitivity for the locking condition.
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Fig. 22. Measured (a) constellation diagram, where the measured EVM
is 3.1%, and (b) modulation output spectrum, where the measured average
channel output power is 23.7 dBm.
Fig. 23. Measured EVM and ACPR versus output power.
C. 64-QAM Modulation Signal
The two-stage class-E injection-locking PA demonstrates
good performance under the constant-envelope GMSK mod-
ulation signal. To further test its potential in nonconstant
envelope modulation schemes, the two-stage injection-locking
class-E PA is evaluated using a 64-QAM modulation signal.
To minimize the spectrum spread, a digital root raised cosine
(RRC) filter with 0.3- value to filter the baseband signal. In
general, the linearity of the PA is a critical requirement in the
digital modulation signals, especially for the high-level digital
modulation and high output power applications [25]. Therefore,
the proposed PA is operated in the class-AB mode to achieve
LIN AND CHANG: BROADBAND INJECTION-LOCKING CLASS-E POWER AMPLIFIER
TABLE I
COMPARISONS OF THE PREVIOUSLY REPORTED INJECTION-LOCKING CMOS PAS AND THIS WORK
TABLE II
COMPARISONS OF THE PREVIOUSLY REPORTED FULLY INTEGRATED STATE-OF-THE-ART GAAS PAS AND THIS WORK
good linearity. The linearity and gain of the class-AB operation
is better than that of the class-E operation because of the bias
condition. To achieve high linearity, the drain dc voltages are
all biased to 6 V, while the gate dc voltages are 0.25 V. Fig. 20
shows the measured output power and PAE versus frequency
with CW signal. Between 2.8 and 3.8 GHz, the measured output
power and PAE are better than 25 dBm and 50%, respectively.
For this bias condition, the proposed PA achieves high output
power and efficiency over the bandwidth.
Fig. 21 shows the measured power gain and drain efficiency
versus output power with the 64-QAM modulation signal at
3.5 GHz. The measured output is 24 dBm with a peak power
gain of 32.5 dB, and the peak drain efficiency is 55% with an
output power of 27 dBm. The measured modulation output spec-
trum and constellation diagram at 3.5 GHz for the 64-QAM
modulation signal are plotted in Fig. 22. The PA has a max-
imum EVM of 3.1%, an amplitude error of 2.3% and a phase
error of 3.3 . We also assume the channel spacing and adjacent
channel bandwidth are both 1 MHz, and the measured ACPR
is better than 33 dBc. Fig. 23 shows the measured EVM and
ACPR versus output power at 3.5 GHz. The EVM is within 9%
over the output power level, and the ACPR at 1-MHz offset
is below 21 dBc. Moreover, the measured EVM and ACPR
below an output power level of 25 dBm are better than 4.5%
and 30 dBc, respectively.
For the comprehensive comparison with the reported PAs, the
previously reported injection-locking PAs and this work with
the class-E operation are summarized in Table I, and the pre-
viously reported fully integrated state-of-the-art GaAs PAs and
this work with the class-AB operation are summarized Table II.
In general, the performance of a PA can be evaluated by the fol-
lowing FOMs [16],
(13)
(14)
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3241
where is output power (W), is power gain (dB), is
center frequency (GHz), and BW is bandwidth (%). Two FOM
calculations are also listed in Tables I and II. Among all the re-
ported injection-locking PAs listed in Table I, the proposed PA
demonstrates the highest FOM with high PAE and broad band-
width. When the proposed PA is operated in the class-AB mode,
the performance of the PA can be compared with the reported
state-of-the-art GaAs PAs in [16] and [26]–[29] due to its high
gain, high efficiency, and broad bandwidth. As compared with
the PA in [16], the bandwidth and the maximum PAE of this
work are smaller, since the inductance should be properly
designed to satisfy the startup oscillation condition. However,
the gain is significantly enhanced due to the injection-locking
technique. There is a design tradeoff among the bandwidth, the
efficiency, and the gain. When the proposed PA is operated in
the class-E mode with injection locking, it is especially used
for the constant-envelope modulations, such as frequency-shift
keying (FSK) and GMSK, due to the linearity. To enhance the
linearity, the class-AB operation can be adopted in the proposed
PA. Moreover, the proposed PA without linearization still fea-
tures good performance, and it is suitable for the digital modu-
lation schemes.
V. CONCLUSION
Design and analysis of a two-stage broadband injec-
tion-locking class-E PA using a 0.5- m GaAs E/D-mode
PHEMT process are presented in this paper. The phenom-
enon of the injection-locking with various input levels can
be efficiently estimated through the stability analysis with an
autonomous circuit. A systematic design procedure for the
injection-locking class-E PA is proposed and successfully
applied to the circuit design. Moreover, the proposed PA with
GMSK and 64-QAM modulation signals still demonstrates
good performance, and it is suitable for digital modulation
3242 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 10, OCTOBER 2012
schemes. The PA designed using the injection-locking tech-
nique has the potential for the modern wireless communication
applications due to its high power gain, high efficiency, and
good modulation quality.
ACKNOWLEDGMENT
The authors would like to thank K. Chen, Industrial Tech-
nology Research Institute (ITRI), Hsinchu City, Taiwan, and
A. P.-L. Chang, Taiwan Agilent, Jhongli City, Taiwan, for the
discussions and the measurement helps. The chip was fabri-
cated by the WIN Semiconductors Corporation, Taiwan. The
EDA design software was provided by the chip Implementation
Center (CIC) of Taiwan. The RF probes and the RF cables for
the on-wafer measurement were provided by the Allstron Cor-
poration, Taoyuan, Taiwan, and the Bo-Jiang Technology Cor-
poration, Tainan, Taiwan, respectively.
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Chi-Hsien Lin was born in Taichong, Taiwan,
in 1983. He received the M.S. degree in electric
engineering from National Central University,
Jhongli City, Taoyuan, Taiwan, in 2006, where he
is currently working toward the Ph.D. degree in
electrical engineering.
His research interests include the microwave and
millimeter-wave integrated circuits.
Mr. Lin received the National Central University
Outstanding Student Award in 2011 and the National
Central University Outstanding Graduate Award in
2012.
Hong-Yeh Chang (S’02–M’05) was born in
Kinmen, Taiwan, in 1973. He received the B.S. and
M.S. degrees in electric engineering from National
Central University, Jhongli City, Taoyuan, Taiwan,
in 1996 and 1998, respectively, and the Ph.D. degree
from the Graduate Institute of Communication
Engineering, National Taiwan University, Taipei,
Taiwan, in 2004.
From 1998 to 1999, he joined Chunghwa Telecom
Laboratories, Taoyuan, Taiwan, where he was
involved in the research and development of code
division multiple access (CDMA) cellular phone system. In 2004, he was a
Post-Doctoral Research Fellow with the Graduate Institute of Communication
Engineering, National Taiwan University, Taipei, Taiwan, working on research
of advanced millimeter-wave integrated circuits. He joined the faculty of the
Department of Electrical Engineering, National Central University, Jhongli
City, Taiwan, in February 2006, where he is currently an Associate Professor.
His research interests are microwave and millimeter-wave circuit and system
designs.
Dr. Chang is a member of Phi Tau Phi.