IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO.

11, NOVEMBER 2013 5215

A Class-E RF Power Amplifier With a Flat-Top

Transistor-Voltage Waveform
Arturo Mediano, Senior Member, IEEE, and Nathan O. Sokal, Life Fellow, IEEE

Abstract—This paper shows a new class-E amplifier topology

with the objective to increase the nominal class-E output power
for a given voltage and current stress on the power transistor. To
obtain that result, a parallel LC resonator is added to the load net-
work, tuned to the second harmonic of the switching frequency. A
class-E power amplifier is obtained whose transistor-voltage wave-
form peak value is 81% of the peak value of the voltage of a nominal
class-E amplifier using the same dc supply voltage. In this ampli-
fier, the peak voltage across the transistor is 3.0 times the dc supply
voltage, instead of the 3.6 times associated with nominal class-E Fig. 1. Low-order class-E amplifier.
amplifiers. A normalized design is presented, and the behavior of
the circuit is analyzed with simulation showing that the ratio of
output power versus transistor peak voltage times peak current is
20.4% better than the nominal class E. The proposed converter
and normalized design approach are verified by simulations and
measurements done on an experimental prototype.
Index Terms—Class E, efficiency, high efficiency, power ampli-
fier, transistor peak voltage.

I. INTRODUCTION
HE class-E amplifier [1]–[3] is one of the most important Fig. 2. Normalized nominal class-E voltage and current waveforms.

T switching-mode power amplifiers used in power electron-

ics [4]–[6] and radio-frequency applications [7]. In principle,
the amplifier efficiency can approach 100%, with actual values
of efficiency usually in the range of 70–93% [3].
Fig. 1 shows the most common class-E topology, namely the
low-order class E. The topology consists of a power transistor
acting as a switch to obtain high efficiency, a load resonant
circuit (C1 , C2 , L2 ), a choke L1 which acts as a dc current
source, and a load resistance Rload , to which the output power
is delivered.
High efficiency is obtained because the output circuit is de-
signed to ensure that the voltage across the switch is already at
or near zero at the instant of turn ON and the current through
the switch is at or nearly zero at turn ON.
Fig. 2 shows typical normalized voltage and current wave-
forms in a low-order class-E amplifier.
In the classical class-E amplifier [1]–[3], namely nominal in
this paper, the ratio Vsw pk /Vdd is 3.562, Pout /(Vsw pk Isw pk ) is
0.098, and Isw pk /Idd is 2.862, where Isw pk is the peak device
Manuscript received September 28, 2012; revised November 26, 2012 and
January 14, 2013; accepted January 14, 2013. Date of current version May 3,
2013. This work was supported in part by Projects TEC2010-19207 (Spanish
MICINN), DGA-FSE, and OTRI 2008/0460. Recommended for publication by
Associate Editor J. M. Alonso.
A. Mediano is with the Aragon Institute for Engineering Research, University
of Zaragoza, Zaragoza 50018, Spain (e-mail: amediano@unizar.es).
N. O. Sokal is with Design Automation, Auburndale, MA 02466-2660 USA
(e-mail: nathansokal@gmail.com).
Digital Object Identifier 10.1109/TPEL.2013.2242097
0885-8993/$31.00 © 2013 IEEE
Fig. 3. Flat-top class-E topology.
current Id (t), and Vsw pk is the peak device voltage Vd (t), which
is a limitation in some applications [8].
Previous research tried to reduce the peak voltage with zener
diodes [9], [10], with a transformer and a diode [11], or with
a transmission line transformer [12]. A similar waveform is
obtained from class EF 2 and EF 3 amplifiers but those inverters
are more complex in design [13].
In this paper, the output resonant circuit is modified, as shown
in Fig. 3, by adding a resonant parallel LC circuit (C3 , L3 ),
which is tuned to the second harmonic of the switching fre-
quency (2fo ), in series with the load. The second harmonic
yields a flat-top shape of the voltage waveform as presented
in [14] by the authors. A complete analysis of the topology is
included in this paper.
Previous publications by other authors analyze a simi-
lar topology with harmonic manipulation mainly for broad-
band or efficiency purposes [15]–[18], resonant circuits are
added to the class-E output network to obtain class-F am-
plification [17]–[19], broadband [20], [21], second-harmonic

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5216 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 11, NOVEMBER 2013

Fig. 4. Normalized class-E flat-top topology.

reduction [21], [22], and harmonic manipulation for filtering or Fig. 5. Normalized class-E flat-top HEPA screen.
efficiency purposes [23]. In this paper, a flat-top transistor volt-
age waveform is obtained with the aim to improve the output
power capability of the class E.
The advantage of a flat-top voltage waveform is that the tran- The basic strategy was to design for nominal class-E wave-
sistor peak voltage and peak current for a given output power forms with a quasi-ideal switch and to optimize that design to
are reduced from the values in nominal class E. Then, stress is deliver the specified output power from a transistor being driven
reduced, or more output power can be obtained with the same to a specified peak flat-top voltage and operating at the highest
amount of stress. Output power for a given product of peak possible efficiency. To optimize the nominal class-E design, the
voltage and peak current is 0.118 for the flat-top voltage, versus software adjusts the parameters C1 , C2 , L2 , C3 , L3 , and Rload .
0.098 in a nominal class E; flat top is better than nominal by a Minimum and maximum limit values for each of the param-
factor of 0.118/0.098 = 1.2. eters are set with ranges from 50% to 200% of the nominal
The remainder of this paper is organized as follows. values. L3 and C3 values must resonate at 2fo , as explained
Section II presents the fundamentals of the proposed circuit, earlier. The goal for the optimizer was set to provide the desired
including a normalized design approach. Section III compares output power, while making the efficiency as high as possible.
the waveforms and spectra of the proposed and classical topol- The normalized values (see Fig. 4) are shown in (1)–(4), and the
ogy. Section IV includes a design example and experimental HEPA screen is shown in Fig. 5
results to verify the proposal. The conclusions of this paper are
drawn in Section V. ωn = 1 rad/s (1)
ωn
II. FLAT-TOP VERSION OF CLASS E fn = = 0.159 Hz (2)
2π
The proposed topology is analyzed from a normalized ver- Rload(n ) = 0.9 Ω (3)
sion, to obtain a general solution for any output power, at any
switching frequency and using any dc-voltage supply. Vdd(n ) = 1 V. (4)
The normalized power amplifier, depicted in Fig. 4, operates
from a 1-V dc supply and delivers 1 W of output power; fur-
thermore, the switching device has 0.01 Ω on-resistance Rdson , The normalized results for the class-E components are in-
and the switching frequency is 1 rad/s. cluded in (5)–(13). Note that inductor values are given in
The design of the amplifier was done with the HEPA PLUS Henries (H) and capacitor values are given in Farads (F)
[24]1 optimizer software.
L1(n) = 1 × 106 H (5)
Analytical analysis and optimization is challenging because
of the many complicated interactions among the seven passive L2(n ) = 0.49 H (6)
linear circuit elements that are being adjusted [25].
L3(n ) = 0.523 H (7)
The transistor has three major device parameters, which can-
not be adjusted independently because it would change the C1(n ) = 0.225 F (8)
transistor’s operating characteristics. If the user wishes to try
C2(n ) = 50.516 F (9)
multiple different transistors, to see which performs best, it can
be done by adding the parameters for these candidate transistors C3(n ) = 0.478 F (10)
and running the optimizer to adjust the seven passive circuit
Vsw pk
elements. This procedure can be repeated for any number of = 2.9765 (11)
transistors, and then simply choose the transistor that yields the Vdd
preferred results. Isw pk
= 2.8350 (12)
Idd
1 A 20 pages document with a tutorial about HEPA software is available
at no cost for interested readers requesting it to nathansokal@gmail.com or Pout
= 0.11832. (13)
amediano@unizar.es. (Vsw pk Isw pk )

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MEDIANO AND SOKAL: CLASS-E RF POWER AMPLIFIER WITH A FLAT-TOP TRANSISTOR-VOLTAGE WAVEFORM 5217

Fig. 6. Normalized class-E flat-top HEPA waveforms.

Equations (14) and (15) can be used by designers to denor-

malize a design as shown in the example of Section IV
ωn Rload
Lj = Lj (n ) × × with j = 1, 2, and 3 (14)
ωo Rload(n )
Fig. 7. Normalized class-E flat-top versus nominal waveforms.
ωn Rload(n )
Cj = Cj (n ) × × with j = 1, 2, and 3 . (15)
ωo Rload
Fig. 6 shows the simulated normalized transistor current and TABLE I
voltage for the proposed topology; it clearly shows the obtained SUMMARY OF TYPICAL SETTINGS
flat-top voltage waveform.

III. FLAT TOP VERSUS NOMINAL CLASS E

A nominal class-E design was prepared with the same nor-
malized values for supply voltage, output power, load resistor,
and frequency (1)–(4) to be able to compare waveforms and out-
put spectrum. The component values for that nominal class-E
design are included in
L1(n ) NOM = 1 × 106 H (16)
L2(n ) NOM = 1.6239 H (17)
C1(n ) NOM = 0.2418 F (18)
C2(n ) NOM = 55.492 F. (19)
Waveforms for both topologies are plotted in Fig. 7, where
the subscript NOM refers to the nominal design and subscript
FLAT the flat-top proposal. Note that load current Iload , switch
current Isw , and device voltage Vsw are plotted with amplitudes
normalized to Idd and Vdd .
In Table I, a summary of results is included for both the flat
top and the nominal design.
The peak value of a flat-top device voltage is 81% of the peak
value of the voltage of a nominal class-E amplifier (3.0 times
the dc supply voltage instead of 3.6 times associated with the
nominal version). In Fig. 8, the peak values for some typical RF
amplifier topologies are plotted for comparison [4].
Note that, from the device stress point of view, classes A, B,
and C have a lower Vsw pk value but those topologies are not Fig. 8. Typical peak device voltage in RF amplifiers.
high-efficiency amplifiers. Class D results are better than the

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5218
Fig. 9. Typical output power capability in RF power amplifiers [4].
Fig. 10. Normalized device peak voltage and device peak current spectrum:
flat-top version (upper plots) and nominal version (lower plots).
flat-top solution at the expense of using two transistors. The flat-
top topology is clearly better than nominal class E and similar to
the class F (second harmonic). The best result is obtained from
class F (third harmonic) in addition to the second harmonic at
the expense of an additional resonant circuit in the output. That
circuit is more complex to design.
The ratio of output power versus transistor peak voltage times
peak current (output power capability) is 0.118 versus 0.098 in a
nominal class E, so more output is possible for a given amount
of stress on the transistor (see Fig. 9).
From the output power capability behavior, the best topolo-
gies are classes D and B. Those topologies have two devices,
including two gate drivers for the class D, which results in
more component cost and volume. The result for class F third
harmonic is at the cost of an additional resonator in the out-
put versus the flat top and class F second harmonic solutions.
Class F second harmonic and flat-top class-E design are similar
in the result with some advantage for the class-F solution.
As shown in Fig. 7, the output voltage and current are not
purely sinusoidal in wave shape. In Fig. 10, the harmonic content
of drain voltage and output load current (normalized) is plotted
for both the flat top and nominal class-E amplifier.
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 11, NOVEMBER 2013
Note that because the L3 C3 resonator is in series with L2 C2
and tuned to 2fo , a considerable reduction of the 2fo power
delivered to the load is obtained as shown in the high reduction
in second harmonic of output current for the flat-top version.
The 2fo is the harmonic with the largest amplitude in the
ordinary class-E circuit and such reduction is useful for com-
munications applications that need low harmonic content in the
output power.
A more sinusoidal wave shape can be obtained by adding a
low-pass filter at the amplifier’s output as in other typical ampli-
fiers but in many applications, a moderate amount of harmonic
content is allowable. Examples of such cases are chemical or
thermal conversion, industrial scientific or medical band appli-
cations where little filtering is needed, and when the output is
passed through a rectifier as with dc–dc conversion
IV. EXPERIMENTAL VALIDATION
To verify the circuit, a flat-top class-E amplifier was designed
and built. Frequency fo was chosen as 1 MHz (50% driver duty
ratio) to minimize layout and measurement parasitic effects and
high output power was not considered to avoid the need for a
low nominal load resistance so matching circuits, parasitic and
tuning are avoided. Two 50-Ω load resistors in parallel were
used as load (Rload = 25 Ω). The flat-top class-E design was
calculated with (5)–(10)
fo = 1 MHz (20)
Rload = 25 Ω. (21)
The amplifier was designed around an IRF520 N transistor
from International Rectifier with Rds(on) = 0.2 Ω and Coss =
92 pF at 25 V.
Denormalization was done with (14) and (15) and results are
included in column “THEORY” in Table II. After theoretical
components were calculated, commercial values were chosen,
which are also included in Table II. After that, simple models
for those components were chosen to take into account the
dominant parasitic effects. The parameter values for the models
were measured with an Agilent 4294 A impedance analyzer
and are also shown in Table II. As additional information, the
effective value of the components at 1 MHz is included in the
last column of the table.
Fig. 11 is the equivalent to Fig. 3 including parasitic for all
the components. A simple model for the transistor is used: an
ideal switch and the equivalent output capacitance of the device.
The design, including parasitic effects, was simulated with
HEPA and SPICE. Waveforms from the SPICE simulation for
driver gate signal Vdriver , drain voltage Vsw , and output load
voltage Vload are shown in Fig. 12. The response of the amplifier
matches the nominal waveforms as expected from the theoretical
design.
A prototype was built using a two layers FR-4 board as shown
in Fig. 13. Vdd dc bus voltage is filtered and decoupled by the
components on top of the picture. The desired capacitance for
C1 is comprised of the output capacitance of the transistor Q1
and the five capacitors in parallel as shown in Fig. 11. The layout
of those capacitors is very important to avoid ringing in drain
MEDIANO AND SOKAL: CLASS-E RF POWER AMPLIFIER WITH A FLAT-TOP TRANSISTOR-VOLTAGE WAVEFORM 5219

TABLE II
THEORETICAL AND EXPERIMENTAL VALUES OF COMPONENTS

Fig. 11. Flat-top class E and parasitic in components.

Fig. 13. Prototype class-E amplifier with flat-top voltage waveform.

Fig. 12. Simulated waveforms for the 1-MHz class-E flat-top amplifier.

waveform. Two 50 Ω loads are used in parallel through BNC

connectors.
Measurements of the prototype were done with an Agilent
DSO7104B oscilloscope and the obtained waveforms in Fig. 14
Fig. 14. Measured class-E flat-top waveforms for the 1 MHz design.
agree very well with simulation results in Fig. 12.

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5220
TABLE III
MAIN RESULTS IN THE PROTOTYPE (V d d = 12.2 V)
Additional data from measurements are included in Table III.
All measurements are in good agreement with theory. The
prototype was prepared for a higher output power in future
experiments (note the size of the components in Fig. 13) but this
experiment was done for a low output power. In that way, the
load resistance is 25 Ω, very easy to obtain paralleling two 50 Ω
laboratory loads.
A higher output power could be obtained with higher power
supply (changing transistor if necessary) or reducing the load
resistor (e.g., using a matching network). To demonstrate the
flat-top concept, the simple low-power option was chosen, re-
moving the parasitic effects from measurements.
V. CONCLUSION
A new class-E circuit with a flat-top voltage waveform on
the transistor whose peak value is 81% of the peak value of
the voltage of a nominal class-E amplifier using the same dc
supply voltage has been presented. In this amplifier, the peak
voltage across the transistor is 3.0 times the dc supply voltage
Vdd , instead of the 3.6 times associated with nominal class-E
amplifiers. To obtain that response, a parallel LC resonator is
added to the load network, tuned to the second harmonic of the
switching frequency.
A normalized design is presented, and the behavior of the
circuit is shown with simulation showing that the ratio of output
power versus transistor peak voltage times peak current is 0.118,
versus 0.098 in a nominal class E.
The usefulness of the class-E circuits can be assessed as
the ratio of output power versus transistor peak voltage times
peak current. The improvement over the nominal class E (value
0.098), made by the “flat-top” circuit (value 0.118), was 20.4%
at a cost of one inductor and one capacitor.
The amplifier is compared in waveforms and output spec-
trum with a nominal class-E topology. A prototype was built
to validate the theory and the simulation. The advantage of a
flat-top voltage waveform is that the transistor peak voltage and
peak current for a given output power are reduced; then stress is
reduced, or more output power can be obtained with the same
amount of stress. The simulation is verified by laboratory mea-
surements.
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 11, NOVEMBER 2013
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MEDIANO AND SOKAL: CLASS-E RF POWER AMPLIFIER WITH A FLAT-TOP TRANSISTOR-VOLTAGE WAVEFORM
Arturo Mediano (M’98–SM’06) received the M.Sc.
and Ph.D. degrees in electrical engineering from the
University of Zaragoza, Zaragoza, Spain, in 1990 and
1997, respectively.
Since 1990, he has been involved in R&D and
troubleshooting projects with companies in electro-
magnetic compatibility (EMI/EMC) and RF fields
for communications, industry, scientific, and medical
applications. Since 1992, he has held a teaching pro-
fessorship with special interest in EMI/EMC and RF
(HF/VHF/UHF) design for Telecom and Electrical
Engineers with the Group of Power Electronics and Microelectronics, Univer-
sity of Zaragoza. He is the author/coauthor for many publications and patents
as result of activity in research activities. He has substantial experience in col-
laboration with industries with a focus on training and consulting in RF design
and EMI/EMC design and troubleshooting. Usually, the result was directly used
in a marketed product. He has taught more than 40 courses and seminars for
industries and institutions in the fields of RF/EMI/EMC in Spain, the U.S.,
Switzerland, France, U.K., Italy, and The Netherlands. His research interest
include high-efficiency switching-mode RF power amplifiers with experience
in applications like mobile communication radios, broadcasting, through-earth
communication systems, induction heating, medical equipment, plasmas for in-
dustrial applications, and radio-frequency identification.
Dr. Mediano has been a Speaker in paper sessions and tutorials of some
of the most important symposiums and conferences related to RF and EMC
(RF EXPO, IEEE IMS, and IEEE International Symposium EMC, URSI, EPE,
ARFTG, EUROEM, IEEE RWS, EuMW, etc.). He is one of the Instructors
of Besser Associates, one of the world’s more important providers of contin-
uing education for RF and microwave professionals. He is an active member
from 1999 of the MTT-17 (HF/VHF/UHF technology) Technical Committee of
the Microwave Theory and Techniques Society and a member of the Electro-
magnetic Compatibility Society (member of the directive of the EMC Spanish
Chapter) and a member of the Education Society.
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5221
Nathan O. Sokal (M’56–SM’56–F’89–LF’94) re-
ceived the Bachelor’s and Master’s degrees in elec-
trical engineering in 1950 from the Massachusetts
Institute of Technology, Cambridge, MA, USA.
From 1950 to 1965, he held engineering and su-
pervisory positions with Holmes and Narver, Inc.,
M.I.T. Lincoln Laboratory, Mack Electronics Divi-
sion of Mack Trucks, Inc., Di/An Controls, Inc.,
and Sylvania Electronic Systems Division. He was
involved with design, manufacturing, and field in-
stallation and operation of a wide variety of analog
and digital equipment for instrumentation, control, communications, computa-
tion, and signal and data processing. In 1965, he founded Design Automation,
Auburndale, MA, USA, an electronics consulting company doing product de-
sign, design review and needed redesign, and technology development for
equipment manufacturers and government agencies, and technical consulting on
legal matters for attorneys. Much of that work was focused on high-efficiency
switching-mode power conversion and power amplification, at frequencies from
dc to 3 GHz. He contributed to the technology of high-efficiency power conver-
sion and RF power amplification.
Mr. Sokal received the Microwave Pioneer Award of the IEEE Microwave
Theory and Techniques Society, in recognition of a major, lasting contribution,
for development of the class-E RF power amplifier in 2007. In 2011, he re-
ceived the Doctoral Degree “Doctor Honoris Causa” by the Polytechnic Univer-
sity of Madrid, Spain, for inventing and developing the class-E high-efficiency
switching-mode RF power amplifier. He is a Technical Adviser to the American
Radio Relay League, on RF power amplification and dc power conversion. He is
a member of the honorary professional societies Eta Kappa Nu, The Electromag-
netics Academy, and Sigma Xi. He reviews technical manuscripts submitted for
publications and conferences: IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS, IEEE TRANSACTIONS ON ELEC-
TRON DEVICES, IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYS-
TEMS, IEEE TRANSACTIONS ON POWER ELECTRONICS, IEEE TRANSACTIONS ON
INDUSTRIAL ELECTRONICS, IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS,
Power Electronics Specialists Conference, International Symposium on Circuits
and Systems, Applied Power Electronics Conference, International Conference
on Power Electronics, Drives, and Energy Systems for Industrial Growth, and
Design Automation Conference; and Transactions on South African Institute
of Electrical Engineers, European Power Electronics (EPE) Journal, and EPE
Conference.