06 - Opamp Design

ELEC 401: Analog CMOS Integrated Circuit Design
Set 6
Opamp Design
References: “Analog Integrated Circuit Design” by D. Johns and K. Martin
and “Design of Analog CMOS Integrated Circuits” by B. Razavi
All figures in this set of slides are taken from the above books
Shahriar Mirabbasi
Department of Electrical and Computer Engineering
University of British Columbia
shahriar@ece.ubc.ca
SM 1
ELEC 401 Set 6 - Opamp Design
General Considerations
• Gain
• Small-signal bandwidth
• Large-signal performance
• Output swing
• Input common-mode range
• Linearity
• Noise/offset
• Supply rejection
SM 2
One-Stage Op Amps
SM 3
One-Stage Op Amp in Unity Gain
Configuration
SM 4
Cascode Op Amps
SM 5
Unity Gain One Stage Cascode
SM 6
Folded Cascode Op Amps
SM 7
Folded Cascode Stages
SM 8
Folded Cascode (cont.)
SM 9
Folded Cascode (cont.)
| Av | gm1 {[(gm 3 gmb3 )ro3 (ro1 || ro5 )]|| [(gm 7 gmb 7 )ro7 ro9 ]}
SM 10
Telescopic versus Folded Cascode
SM 11
Example Folded-Cascode Op Amp
SM 12
Single-Ended Output Cascode Op Amps
SM 13
Triple Cascode
Av app. (gmro)3/2
Limited Output Swing
Complex biasing
SM 14
Output Impedance Enhancement
Rout A1 g m 2 ro 2 ro1
SM 15
Gain Boosting in Cascode Stage
SM 16
Differential Gain Boosting
SM 17
SM 18
SM 19
Two-Stage Op Amps
SM 20
Single-Ended Output Two-Stage Op Amp
SM 21
Two-Stage CMOS Opamp
• Popular opamp design approach
• A good example to review many important design concepts
• Output buffer is typically used to drive resistive loads
• For capacitive loads (typical case in CMOS) buffer is not
required.
Cc
V in A1 – A2 1 V out
Differential Second Output

input stage gain stage buffer
SM 22
Two-Stage CMOS Opamp
• Popular opamp design approach
• A good example to review many important design concepts
• Output buffer is typically used to drive resistive loads
• For capacitive loads (typical case in CMOS) buffer is not
required.
Cc
V in A1 – A2 1 V out
Differential Second Output

input stage gain stage buffer
SM 22
Two-Stage CMOS Opamp Example
SM 23
Gain of the Opamp
• First Stage
Differential to single-ended
• Second Stage
Common-source stage
• Output buffer is not required when driving capacitive loads
SM 24
Gain of the Opamp
Third Stage
• Source follower
• Typical gain: between 0.7 to1

• Note: go=1/ro and GL=1/RL
• gmb is body-effect conductance (is zero if source can be tied to
substrate)
SM 25
Frequency Response
Q5
300
Vbias
vin+
Q1 Q2
vin– 300 300
CC
v1 v2
A3 1
–A2 A3 vout
150
150 i = g m1 vin
Ceq = CC 1 + A 2
Q3 Q4
SM 26
Frequency Response
Simplifying assumptions:
• CC dominates
• Ignore Q16 for the time being (it is used for lead compensation)
Miller effect results in
• At midband frequencies
SM 27
Frequency Response
• Overall gain (assuming A3 1)
which results in a unity-gain frequency of
• Note: ta is directly proportional to gm1 and inversely

proportional to CC.
SM 28
Frequency Response
• First-order model
20 log A1 A 2
Gain – 20 dB/decade
(dB)
ta gm1 CC
0 Freq
p1 ta (log)
p1
0 Freq
Phase ta
(log)
(degrees)
– 90
– 180
SM 29
Slew Rate
• Maximum rate of output change when input signal is large.
Q5
300
Vbias
vin+
Q1 Q2
vin– 300 300
CC
v1 v2
A3 1
–A2 A3 vout
150
150 i = g m1 vin
Q3 Q4
• All the bias current of Q5 goes either into Q1 or Q2.
SM 30
Slew Rate
SM 31
Slew Rate
• Normally, the designer has not much control over ta
• Slew-rate can be increased by increasing Veff1
• This is one of the reasons for using p-channel input stage:

higher slew-rate
SM 32
Systematic Offset Voltage
• To ensure inherent (systematic) offset voltage does not exist,
nominal current through Q7 should equal to that of Q6 when the
differential input is zero.
Q5 VDD Q6
Vbias 300
300
I b ia s
Q1 Q2
Vin – 300 300
Vin +
Vo ut
300
150 150
Q3 Q4 Q7
VSS
SM 33
Systematic Offset Voltage
• Avoid systematic offset by choosing:
• Found by noting
and
then setting
SM 34
N-Channel versus P-Channel Input Stage
• Complimentary opamp can be designed with an n-channel input
differential pair and p-channel second-stage
• Overall gain would be roughly the same in both designs
P-channel Advantages
• Higher slew-rate: for fixed bias current, Veff is larger (assuming
similar widths used for maximum gain)
• Higher frequency of operation: higher transconductance of
second stage which results in higher unity-gain frequency
• Lower 1/f noise: holes less likely to be trapped; p-channel
transistors have lower 1/f noise
• N-channel source follower is preferable (less voltage drop and
higher gm)
N-channel Advantage
• Lower thermal noise — thermal noise is lowered by high
transconductance of first stage
SM 35
Feedback and Opamp Compensation
Y H (s)
( s)
X 1 H (s)
• Feedback systems may oscillate

• The following two are the oscillation conditions:
| H( j )| 1
H( j ) 180
SM 36
Stable and Unstable Systems
SM 37
Time-domain response of a feedback system
SM 38
One-pole system
A0
H ( s)
1 s
0
A0
Y 1 A0
(s)
X s
1
0 1 A0
Sp 0 1 A0
Bode plot of the Loop gain
SM 39
Multi-pole system
0.1 p2 10 p1
Bode plot of the Loop gain
SM 40
Phase Margin
Loop Gain -20 dB/decade
(dB)
20 log LG (j )
0 Freq
(log)
p1 t
GM
(gain margin)
p1 t
Phase Freq
0 (log)
Loop Gain
(degrees)
–90
PM
(phase margin)
–180
SM 41
Phase Margin
j 175
H( 1
) 1 e
Y 11.5
(s)
X
Closed loop frequency response

SM 42
Phase Margin (Cont.)
PM 180 H( GX )
Phase Margin = 45
SM 43
Phase Margin = 45
SM 44
• At PM = 60o results in a small overshoot in the step response.

• If we increase PM, the system will be more stable but the time
response slows down.
SM 45
Frequency Compensation
• Push phase crossing point out

• Push gain crossing point in
SM 46
Telescopic Opamp (single-ended) -example
SM 47
Compensation (Cont.)
• Assume we need a phase margin of 45o (usually

inadequate) and other non-dominant poles are at high
frequency.
SM 48
Compensation of a two-stage opamp
Miller Effect Ceq CE (1 Av 2 )CC

1
f pE
2 Rout[CE (1 Av 2 )CC ]
SM 49
Compensating Two-Stage Opamps
Q5 Q6
300 VDD
Vbias1 300
Q1 Q2
Vin- 300 300 Vin+ Vout2
Vbias2
Q16 Cc
300
150 150
Q3 Q4 Q7
SM 50
v1 RC CC
gm1 v R1 C1 g m7 v R2 C2
in 1
• Q16 has VDS16 = 0 therefore it is hard in the triode region.
• Small signal analysis: without RC, a right-half plane zero occurs

and worsens the phase-margin.
SM 51
• Using RC (through Q16) places zero at
• Zero moved to left-half plane to aid compensation

• Good practical choice is
• satisfied by letting
SM 52
Design Procedure
Design example: Find CC with RC=0 for a 55o phase margin
– Arbitrarily choose C’C=1pF and set RC=0
– Using SPICE, find frequency t where a –125 phase shift

exists, define gain as A’
– Choose new CC so t becomes unity-gain frequency of the

loop gain, resulting in a 55o phase margin.
Achieved by setting CC=CCA’
– Might need to iterate on CC a couple of times using SPICE
SM 53
Design Procedure
Next: Choose RC according to
– Increasing t by about 20 percent, leaves zero near final t

– Check that gain continues to decrease at frequencies above the
new t
Next: If phase margin is not adequate, increase CC while leaving

RC constant.
SM 54
Design Procedure
Next: Replace RC by a transistor
SPICE can be used for iteration to fine-tune the device

dimensions and optimize the phase margin.
SM 55
Process and Temperature Independence
• Can show non-dominant pole is roughly given by
• Recall zero given by
• If RC tracks inverse of gm7 then zero will track p2:
SM 56
• Need to ensure Veff16/Veff7 is independent of process and
temperature variations
Q11 Q6
25 300
Vbias
Q12
25
Va
25 Q16 CC
Q13
Vb 300
Q7
Vb
• First set Veff13=Veff7 which makes Va=Vb

SM 57
SM 58
Stable Transconductance Biasing
SM 59
• Transconductance of Q13 (to the first order) is determined by
geometric ratios only.
• Independent of power-supply voltages, process parameters,
temperature, etc.
• For special case (W/L)15=4(W/L)13
gm13=1/RB
• Note that high-temperature will decrease mobility and hence

increase effective gate-source voltages.
• Roughly 25% increase for 100 degree increase
• Requires a start-up circuit (might have all 0 currents)
SM 60
• Transconductance of Q13 (to the first order) is determined by
geometric ratios only.
• Independent of power-supply voltages, process parameters,
temperature, etc.
• For special case (W/L)15=4(W/L)13
gm13=1/RB
• Note that high-temperature will decrease mobility and hence

increase effective gate-source voltages.
• Roughly 25% increase for 100 degree increase
• Requires a start-up circuit (might have all 0 currents)
SM 60

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06 - Opamp Design

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ELEC 401: Analog CMOS Integrated Circuit Design

Limited Output Swing

Differential Second Output

Differential Second Output

• Output buffer is not required when driving capacitive loads

• Typical gain: between 0.7 to1

Miller effect results in

which results in a unity-gain frequency of

• Note: ta is directly proportional to gm1 and inversely

• Normally, the designer has not much control over ta

• Slew-rate can be increased by increasing Veff1

• This is one of the reasons for using p-channel input stage:

• Feedback systems may oscillate

Bode plot of the Loop gain

Loop Gain -20 dB/decade

Closed loop frequency response

• At PM = 60o results in a small overshoot in the step response.

• Push phase crossing point out

• Assume we need a phase margin of 45o (usually

Miller Effect Ceq CE (1 Av 2 )CC

• Q16 has VDS16 = 0 therefore it is hard in the triode region.

• Small signal analysis: without RC, a right-half plane zero occurs

• Zero moved to left-half plane to aid compensation

– Using SPICE, find frequency t where a –125 phase shift

– Choose new CC so t becomes unity-gain frequency of the

– Might need to iterate on CC a couple of times using SPICE

– Increasing t by about 20 percent, leaves zero near final t

Next: If phase margin is not adequate, increase CC while leaving

SPICE can be used for iteration to fine-tune the device

• Recall zero given by

• If RC tracks inverse of gm7 then zero will track p2:

• First set Veff13=Veff7 which makes Va=Vb

• Note that high-temperature will decrease mobility and hence

• Note that high-temperature will decrease mobility and hence

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