Professional Documents
Culture Documents
07 - Switched Capacitors
07 - Switched Capacitors
1 of 50
1
Basic Building Blocks
Opamps
• Ideal opamps usually assumed.
• Important non-idealities
— dc gain: sets the accuracy of charge transfer, hence,
transfer-function accuracy.
— unity-gain freq, phase margin & slew-rate: sets the max
clocking frequency. A general rule is that unity-gain freq
should be 5 times (or more) higher than the clock-freq.
— dc offset: Can create dc offset at output. Circuit
techniques to combat this which also reduce 1/f noise.
2 of 50
2
Basic Building Blocks
Double-Poly Capacitors
metal
C1 metal
poly1
C p1 thin oxide
bottom plate C1
poly2 C p2 thick oxide
C p1 C p2
(substrate - ac ground)
3 of 50
3
Basic Building Blocks
Switches
Symbol n-channel
v1 v2 v1 v2
transmission
gate
v1 v2
p-channel v1 v2
4 of 50
4
Basic Building Blocks
Non-Overlapping Clocks
1 T
V on
V off 1
n–2 n–1 n n+1 t T delay
fs --1- delay
V on 2 T
V off 2
n – 3 2n – 1 2 n + 1 2 t T
• Non-overlapping clocks — both clocks are never on at
same time
• Needed to ensure charge is not inadvertently lost.
• Integer values occur at end of 1.
5 of 50
5
Switched-Capacitor Resistor Equivalent
1 2 R eq
V1 V2 V1 V2
C1
T-
Q = C 1 V 1 – V 2 every clock period R eq = -----
C1
Qx = Cx Vx (1)
• C 1 charged to V 1 and then V 2 during each clk period.
Q1 = C1 V1 – V2 (2)
• Find equivalent average current
ii.
C1 V1 – V2
I avg = i-----------------------------
- (3)
'
'
- - -
- -
,
i. T
1-
¥ea
. -
.
6 of 50
6
Switched-Capacitor Resistor Equivalent
• For equivalent resistor circuit
V1 – V2
I eq = ------------------ (4)
R eq
• Equating two, we have
T 1 (5)
R eq = ------ = ----------
C1 C1 fs
7 of 50
7
Resistor Equivalence Example /
8 of 50
8
Example :
i
Vino I
yy
-
Hut
-
•
+
but É
Vin
= -
R
= -
Rts
Parasitic-Sensitive Integrator
End of 011 :
v c2(nT)
Q1 =
C. Veil nt) indicates which
$ turns on :
1 2
( switch is
reference
,
v ci(t) v co(t)
(subtracts)
end of 0/2 : v c1(t) C1
v i(n) = v ci(nT) v o(n) = v co(nT)
9 of 50
9
Qi Gvlnt)
Parasitic-Sensitive Integrator
-
C2 -
t
C2
- t
v ci(nT – T) v ci(nT – T 2)
+
C1 v co(nT – T)
+
C1
-
-
v co(nT – T 2)
FEET/ 2
1 on 2 on
• At end of 2
10 of 50
10
Parasitic-Sensitive Integrator
• Modify above to write
C1
v o(n) = v o(n – 1) – ------ v i(n – 1) (9)
C2
and taking z-transform and re-arranging, leads to
V o(z) C1 1
H(z) ------------ = – ------ ----------- (10)
V i (z ) C2 z – 1
11 of 50
11
Typical Waveforms
1
2
t
t
v ci(t)
v cx(t)
v co(t)
12 of 50
12
Low Frequency Behavior
• From Equation (10) :
C1 1
H(z) = – ------ ----------- (11)
C2 z – 1
13 of 50
13
Low Frequency Behavior
• Above is exact but when T « 1 (i.e., at low frequencies)
j T C1 1
H(e ) – ------ --------- (14)
C2 j T
14 of 50
14
Parasitic Capacitance Effects
C p3 C p4
C2
1 2
1
v i(n)
v o(n)
C p1 C1
C p2
15 of 50
15
Parasitic-Insensitive Integrators
C2
1 2
C1
1
v ci(t) v co(t)
2
1
v i(n) = v ci(nT) v o(n) = v co(nT)
16 of 50
16
Parasitic-Insensitive Integrators
C2 C2
v ci(nT – T) v ci(nT – T 2)
+ -
C1 C1
- v co(nT – T) + v co(nT – T 2)
1 on 2 on
17 of 50
17
Parasitic-Insensitive Integrators
C p3 C p4
C2
1 2
C1
1
v i(n)
v o(n)
2
1
C p1 C p2
18 of 50
18
Parasitic-Insensitive Integrators
• C p1 is continuously being charged to v i(n) and discharged
to ground.
• 1 on — both C 1 and C p1 are charged to v i(n – 1) .
• 2 on — C p1 is discharged through the 2 switch attached
to its node and does not affect the charge accumulating
on C 2 .
• While the parasitic capacitances may slow down settling
time behavior, they do not affect the discrete-time
difference equation.
19 of 50
19
Parasitic-Insensitive Inverting Integrator
C2
1 1
C1
1
v i(n)
v o(n)
V i (z ) 2
2
V o(z)
1 1
V o( z )
C3
V 3(z)
2 2
–C 1 1 – z –1
V 1( z )
C2 z –1 1
1- ---------------
V 2( z ) ------ - V o( z )
C A 1 – z –1
–C3
V 3( z )
21 of 50
21
First-Order Filter
V in(s) V out(s)
22 of 50
22
First-Order Filter
1 1
C2 1 C3 1
2 2 2 2
CA
C1 1
V i(z)
V o(z)
–C3
–C2 1
1- ---------------
V i(z) ------ - V o( z )
CA 1 – z – 1
–C1 1 – z –1
23 of 50
23
First-Order Filter
C A 1 – z – 1 V o(z) = – C 3 V o(z) – C 2 V i(z) – C 1 1 – z – 1 V i(z) (21)
C1 C2
------- 1 – z – 1 + -------
CA CA
– ------------------------------------------------------
V o( z ) C3
H(z) ------------ = – 1
1 – z + ------- (22)
V i(z) CA
C1 + C2 C1
------------------- z – -------
CA CA
= – -----------------------------------------
C3
1 + ------- z – 1
CA
24 of 50
24
First-Order Filter
• The pole of (22) is found by equating the denominator to
zero
CA
z p = -------------------- (23)
CA + C3
25 of 50
25
First-Order Filter
• The dc gain is found by setting z = 1 which results in
–C2
H(1) = --------- (25)
C3
• Note that in a fully-differential implementation, effective
negative capacitances for C 1 , C 2 and C 3 can be achieved
by simply interchanging the input wires.
• In this way, a zero at z = – 1 could be realized by setting
C 1 = – 0.5C 2 (26)
26 of 50
26
Switch Sharing
1
C3
2
C1
CA
1 1
C2
V i(z)
V o( z )
2 2
30 of 50
27
Fully Differential Filters
• Most modern SC filters are fully differential
• Common-mode noise is rejected.
• Even order distortion terms cancel
2 3 4
v p1 = k 1 v 1 + k 2 v 1 + k 3 v 1 + k 4 v 1 +
v1 nonlinear
element
3 5
+ v diff = 2k 1 v 1 + 2k 3 v 1 + 2k 5 v 1 +
-
–v1 nonlinear
element
2 3 4
v n1 = – k 1 v 1 + k 2 v 1 – k 3 v 1 + k 4 v 1 +
31 of 50
28
Fully Differential Filters
C1
C3
1
2
2
CA 2
+ C2
1 1 +
V i(z) V (z )
1 1 - o
- C2
CA
2 2 2
C3
1
C1
32 of 50
29
Fully Differential Filters
• Switching the input connection to C 1
— equivalent to a negative C 1
C1
C3
1
2
2
CA 2
+ C2
1 1 +
V i(z) V (z )
1 1 - o
- C2
CA
2 2 2
C3
1
C1
33 of 50
30
Charge Injection
• To reduce charge injection (thereby improving distortion) ,
turn off certain switches first.
C3 1
Q6
Q5 2
C1
CA
1 1a
C2
V i(z) 1
Q1 Q4 V o(z)
2 Q2Q 3 2a
35 of 50
31
Charge Injection
• Note: 2a connected to ground while 1a connected to
virtual ground, therefore ...
— can use single n-channel transistors
— charge injection NOT signal dependent
Q CH = – W LC ox V eff = – W LC ox V GS – V t (36)
• Charge related to V GS and V t and V t related to substrate-
source voltage.
• Source of Q 3 and Q 4 remains at ground — amount of
charge injected by Q 3 Q 4 is not signal dependent and can
be considered as a dc offset.
36 of 50
32
Charge Injection Example
• Estimate dc offset due to channel-charge injection when
C 1 = 0 and C 2 = C A = 10C 3 = 10pF . ↳ =1pF
• Assume switches Q 3 Q 4 have V tn = 0.8V , W = 30 m ,
–3 2
L = 0.8 m , C ox = 1.9 10 pF m , and power supplies are
2.5V .
• Channel-charge of Q 3 Q 4 (when on) is
37 of 50
33
Charge Injection Example
• Charge transfer into C 3 given by
Q C = – C 3 v out (38)
3
which leads to
–3
÷ vout = ------------------------------------
77.5 10 pC
1pF
- = 78 mV (40)
1
µ out =V☐☐ Gd
Couts ↳
§
Cgdcout =
Coat
GFS Cgd
1 +
Cat
+
Guts 38 of 50
34
☐