Switched-Capacitor Circuits

Reference: Chapter 10 of the text

“Analog Integrated Circuit Design”
by
David Johns and Ken Martin
Chapter(14(of(the(2nd(Edi2on(of(the(text(by(Tony(Chan(Carusone,(David(Johns,(and(Ken(Mar2n(

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 Basic Building Blocks
Opamps
• Ideal opamps usually assumed.
• Important non-idealities
— dc gain: sets the accuracy of charge transfer, hence,
transfer-function accuracy.
— unity-gain freq, phase margin & slew-rate: sets the max
clocking frequency. A general rule is that unity-gain freq
should be 5 times (or more) higher than the clock-freq.
— dc offset: Can create dc offset at output. Circuit
techniques to combat this which also reduce 1/f noise.

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 Basic Building Blocks
Double-Poly Capacitors
metal
C1 metal
poly1

C p1 thin oxide
bottom plate C1
poly2 C p2 thick oxide

C p1 C p2
(substrate - ac ground)

cross-section view equivalent circuit

• Substantial parasitics with large bottom plate capacitance

(20 percent of C 1 )
• Also, metal-metal capacitors are used but they also have
parasitic capacitances.

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 Basic Building Blocks
Switches
Symbol n-channel
v1 v2 v1 v2

transmission
gate
v1 v2
p-channel v1 v2

• MOSFET switches are good switches.

— large off-resistance
— low on-resistance in the range of few tens of to a few
k (depending on transistor sizing)
• However, have non-linear parasitic capacitances.

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 Basic Building Blocks
Non-Overlapping Clocks
1 T
V on
V off 1
n–2 n–1 n n+1 t T delay
fs --1- delay
V on 2 T
V off 2
n – 3 2n – 1 2 n + 1 2 t T
• Non-overlapping clocks — both clocks are never on at
same time
• Needed to ensure charge is not inadvertently lost.
• Integer values occur at end of 1.

• End of 2 is 1/2 off integer value.

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 Switched-Capacitor Resistor Equivalent
1 2 R eq
V1 V2 V1 V2
C1
T-
Q = C 1 V 1 – V 2 every clock period R eq = -----
C1
Qx = Cx Vx (1)
• C 1 charged to V 1 and then V 2 during each clk period.
Q1 = C1 V1 – V2 (2)
• Find equivalent average current
ii.
C1 V1 – V2
I avg = i-----------------------------
- (3)
'
'
- - -
- -

,
i. T
1-
¥ea
. -
.

where T is the clock period.

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 Switched-Capacitor Resistor Equivalent
• For equivalent resistor circuit
V1 – V2
I eq = ------------------ (4)
R eq
• Equating two, we have
T 1 (5)
R eq = ------ = ----------
C1 C1 fs

• This equivalence is useful when looking at low-frequency

operation of a SC-circuit.
• For higher frequencies, discrete-time analysis is used.

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 Resistor Equivalence Example /

• What is the equivalent resistance of a 5pF capacitance

sampled at a clock frequency of 100kHz .
• Using (5), we have
1
R eq = --------------------------------------------------------- = 2M
– 12 3
5 10 100 10
• Note that a very large equivalent resistance of 2M can
be realized.
• Requires only 2 transistors, a clock and a relatively small
capacitance.
• In a typical CMOS process, such a large resistor would
normally require a huge amount of silicon area.

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Example :

i
Vino I
yy
-

Hut
-

•
+

but É
Vin
= -

R
= -

Rts
 Parasitic-Sensitive Integrator
End of 011 :
v c2(nT)
Q1 =
C. Veil nt) indicates which
$ turns on :
1 2
( switch is
reference
,

charge from Gftows from v cx(t) C2

1
G +onto Cz and cancels
,

v ci(t) v co(t)
(subtracts)
end of 0/2 : v c1(t) C1
v i(n) = v ci(nT) v o(n) = v co(nT)

• Start by looking at a simple integrator (note: this structure

is sensitive to parasitic capacitances)
• Want to find output voltage at end of 1 in relation to input
sampled at end of 1 .

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 Qi Gvlnt)
Parasitic-Sensitive Integrator
-

C2 -
t
C2
- t

v ci(nT – T) v ci(nT – T 2)
+

C1 v co(nT – T)
+
C1
-

-
v co(nT – T 2)
FEET/ 2
1 on 2 on
• At end of 2

C 2 v co(nT – T 2) = C 2 v co(nT – T) – C 1 v ci(nT – T) (6)

• But would like to know the output at end of 1
since the charges
C 2 v co(nT) = C 2 v co(nT – T 2) (7)
on
G have nowhere
to
go
when $2 is closed
• leading to
C 2 v co(nT) = C 2 v co(nT – T) – C 1 v ci(nT – T) (8)

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 Parasitic-Sensitive Integrator
• Modify above to write
C1
v o(n) = v o(n – 1) – ------ v i(n – 1) (9)
C2
and taking z-transform and re-arranging, leads to
V o(z) C1 1
H(z) ------------ = – ------ ----------- (10)
V i (z ) C2 z – 1

• Note that gain-coefficient is determined by a ratio of two

capacitance values.
• Ratios of capacitors can be set very accurately on an
integrated circuit (within 0.1 percent)
• Leads to very accurate transfer-functions.

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 Typical Waveforms
1

2
t

t
v ci(t)

v cx(t)

v co(t)

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 Low Frequency Behavior
• From Equation (10) :
C1 1
H(z) = – ------ ----------- (11)
C2 z – 1

• To find frequency response, recall

z = e j T = cos T + j sin T (12)
j T C1 1
H(e ) = – ------ ----------------------------------------------------------- (13)
C 2 cos T + j sin T – 1

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 Low Frequency Behavior
• Above is exact but when T « 1 (i.e., at low frequencies)

j T C1 1
H(e ) – ------ --------- (14)
C2 j T

• Thus, the transfer function is same as a continuous-time

integrator having a gain constant of
C1 1
KI ------ --- (15)
C2 T

which is to the first order approximation is only a function

of the integrator capacitor ratio and clock frequency.

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 Parasitic Capacitance Effects
C p3 C p4
C2

1 2
1
v i(n)
v o(n)
C p1 C1

C p2

• Accounting for parasitic capacitances, we have

C 1 + C p1 1
H(z) = – ---------------------- ----------- (16)
C2 z–1

• Thus, gain coefficient is not well controlled and partially

non-linear (due to C p1 being non-linear).

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 Parasitic-Insensitive Integrators
C2

1 2
C1
1
v ci(t) v co(t)

2
1
v i(n) = v ci(nT) v o(n) = v co(nT)

• By using 2 extra switches, integrator can be made

insensitive to parasitic capacitances
— more accurate transfer-functions
— better linearity (since non-linear capacitances become
unimportant)

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 Parasitic-Insensitive Integrators
C2 C2
v ci(nT – T) v ci(nT – T 2)
+ -
C1 C1
- v co(nT – T) + v co(nT – T 2)

1 on 2 on

• Same analysis as before except that C 1 is switched in

polarity before discharging into C 2 .
V o(z) C1 1
H(z) ------------ = ------ ----------- (17)
V i(z) C2 z – 1

• A positive integrator (rather than negative as before)

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 Parasitic-Insensitive Integrators
C p3 C p4

C2
1 2
C1
1
v i(n)
v o(n)
2
1

C p1 C p2

• C p3 has little effect since it is connected to virtual gnd

• C p4 has little effect since it is driven by output

• C p2 has little effect since it is either connected to virtual

gnd or physical gnd.

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 Parasitic-Insensitive Integrators
• C p1 is continuously being charged to v i(n) and discharged
to ground.
• 1 on — both C 1 and C p1 are charged to v i(n – 1) .
• 2 on — C p1 is discharged through the 2 switch attached
to its node and does not affect the charge accumulating
on C 2 .
• While the parasitic capacitances may slow down settling
time behavior, they do not affect the discrete-time
difference equation.

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 Parasitic-Insensitive Inverting Integrator
C2
1 1
C1
1
v i(n)
v o(n)
V i (z ) 2
2
V o(z)

• The charge on C 2 does not change when 2 turns on

C 2 v co(nT – T 2) = C 2 v co(nT – T) (18)
C 2 v co(nT) = C 2 v co(nT – T 2) – C 1 v ci(nT) (19)
• Present output depends on present input (delay-free)
V o(z) C1 z
H(z) ------------ = – ------ ----------- (20)
V i (z ) C2 z – 1
• Delay-free integrator has negative gain while delaying
integrator has positive gain.
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 Signal-Flow-Graph Analysis
C1
V 1(z)
1 2
C2 CA
V 2(z)
2 1 1

1 1
V o( z )
C3
V 3(z)
2 2

–C 1 1 – z –1
V 1( z )
C2 z –1 1
1- ---------------
V 2( z ) ------ - V o( z )
C A 1 – z –1
–C3
V 3( z )

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 First-Order Filter

V in(s) V out(s)

• Start with an active-RC structure and replace resistors

with SC equivalents.
• Analyze using discrete-time analysis.

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 First-Order Filter
1 1
C2 1 C3 1

2 2 2 2

CA
C1 1
V i(z)
V o(z)

–C3

–C2 1
1- ---------------
V i(z) ------ - V o( z )
CA 1 – z – 1

–C1 1 – z –1

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 First-Order Filter
C A 1 – z – 1 V o(z) = – C 3 V o(z) – C 2 V i(z) – C 1 1 – z – 1 V i(z) (21)

C1 C2
------- 1 – z – 1 + -------
CA CA
– ------------------------------------------------------
V o( z ) C3
H(z) ------------ = – 1
1 – z + ------- (22)
V i(z) CA

C1 + C2 C1
------------------- z – -------
CA CA
= – -----------------------------------------
C3
1 + ------- z – 1
CA

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 First-Order Filter
• The pole of (22) is found by equating the denominator to
zero
CA
z p = -------------------- (23)
CA + C3

• For positive capacitance values, this pole is restricted to

the real axis between 0 and 1
— circuit is always stable.
• The zero of (22) is given by
C1
z z = ------------------- (24)
C1 + C2

• Also restricted to real axis between 0 and 1.

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 First-Order Filter
• The dc gain is found by setting z = 1 which results in
–C2
H(1) = --------- (25)
C3
• Note that in a fully-differential implementation, effective
negative capacitances for C 1 , C 2 and C 3 can be achieved
by simply interchanging the input wires.
• In this way, a zero at z = – 1 could be realized by setting
C 1 = – 0.5C 2 (26)

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 Switch Sharing
1
C3

2
C1
CA

1 1
C2
V i(z)
V o( z )
2 2

• Share switches that are always connected to the same

potentials.

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 Fully Differential Filters
• Most modern SC filters are fully differential
• Common-mode noise is rejected.
• Even order distortion terms cancel
2 3 4
v p1 = k 1 v 1 + k 2 v 1 + k 3 v 1 + k 4 v 1 +
v1 nonlinear
element
3 5
+ v diff = 2k 1 v 1 + 2k 3 v 1 + 2k 5 v 1 +
-
–v1 nonlinear
element
2 3 4
v n1 = – k 1 v 1 + k 2 v 1 – k 3 v 1 + k 4 v 1 +

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 Fully Differential Filters
C1
C3
1

2
2
CA 2

+ C2
1 1 +
V i(z) V (z )
1 1 - o
- C2

CA
2 2 2

C3
1

C1

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 Fully Differential Filters
• Switching the input connection to C 1
— equivalent to a negative C 1
C1
C3
1

2
2
CA 2

+ C2
1 1 +
V i(z) V (z )
1 1 - o
- C2

CA
2 2 2

C3
1

C1

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 Charge Injection
• To reduce charge injection (thereby improving distortion) ,
turn off certain switches first.
C3 1
Q6

Q5 2
C1
CA
1 1a
C2
V i(z) 1
Q1 Q4 V o(z)
2 Q2Q 3 2a

• Advance 1a and 2a so that only their charge injection

affect circuit (result is a dc offset)

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 Charge Injection
• Note: 2a connected to ground while 1a connected to
virtual ground, therefore ...
— can use single n-channel transistors
— charge injection NOT signal dependent
Q CH = – W LC ox V eff = – W LC ox V GS – V t (36)
• Charge related to V GS and V t and V t related to substrate-
source voltage.
• Source of Q 3 and Q 4 remains at ground — amount of
charge injected by Q 3 Q 4 is not signal dependent and can
be considered as a dc offset.

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 Charge Injection Example
• Estimate dc offset due to channel-charge injection when
C 1 = 0 and C 2 = C A = 10C 3 = 10pF . ↳ =1pF
• Assume switches Q 3 Q 4 have V tn = 0.8V , W = 30 m ,
–3 2
L = 0.8 m , C ox = 1.9 10 pF m , and power supplies are
2.5V .
• Channel-charge of Q 3 Q 4 (when on) is

Q CH3 = Q CH4 = – 30 0.8 0.0019 2.5 – 0.8 (37)

–3
= – 77.5 10 pC

• dc feedback keeps virtual opamp input at zero volts.

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 Charge Injection Example
• Charge transfer into C 3 given by
Q C = – C 3 v out (38)
3

• We estimate half channel-charges of Q 3 , Q 4 are injected

to the virtual ground leading to
1
--- Q CH3 + Q CH4 = Q C (39)
2 3

which leads to
–3
÷ vout = ------------------------------------
77.5 10 pC
1pF
- = 78 mV (40)

• dc offset affected by the capacitor sizes, switch sizes and

power supply voltage.
"
"

1
µ out =V☐☐ Gd
Couts ↳

§
Cgdcout =

Coat
GFS Cgd
1 +

Cat
+

Guts 38 of 50
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☐