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TVS0500 5-V Flat-Clamp Surge Protection Device: 1 Features 3 Description
TVS0500 5-V Flat-Clamp Surge Protection Device: 1 Features 3 Description
TVS0500 5-V Flat-Clamp Surge Protection Device: 1 Features 3 Description
TVS0500
SLVSED2C – DECEMBER 2017 – REVISED NOVEMBER 2019
Footprint Comparison
Voltage Clamp Response to 8/20 µs Surge Event
TVS0500 Flat-Clamp
DRV Footprint
2mm x 2mm
Voltage
Conventional TVS
SMB Footprint
3.55mm x 5.3mm
10 20 30
Time ( s)
Traditional TVS
Copyright © 2018, Texas Instruments Incorporated TI Flat-Clamp
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TVS0500
SLVSED2C – DECEMBER 2017 – REVISED NOVEMBER 2019 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................... 9
2 Applications ........................................................... 1 8.4 Reliability Testing ...................................................... 9
3 Description ............................................................. 1 8.5 Device Functional Modes ......................................... 9
4 Revision History..................................................... 2 9 Application and Implementation ........................ 11
9.1 Application Information............................................ 11
5 Device Comparison Table..................................... 3
9.2 Typical Application ................................................. 11
6 Pin Configuration and Functions ......................... 4
10 Power Supply Recommendations ..................... 12
7 Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5 11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
7.2 ESD Ratings - JEDEC .............................................. 5
11.2 Layout Example .................................................... 13
7.3 ESD Ratings - IEC .................................................... 5
7.4 Recommended Operating Conditions....................... 5 12 Device and Documentation Support ................. 14
7.5 Thermal Information .................................................. 5 12.1 Receiving Notification of Documentation Updates 14
7.6 Electrical Characteristics........................................... 6 12.2 Community Resources.......................................... 14
7.7 Typical Characteristics .............................................. 7 12.3 Trademarks ........................................................... 14
12.4 Electrostatic Discharge Caution ............................ 14
8 Detailed Description .............................................. 9
12.5 Glossary ................................................................ 14
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9 13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
Changes from Revision B (February 2018) to Revision C Page
• Changed DC Breakdown Current MAX from 100 to 50 in the Specifications Absolute Maximum Ratings table ................. 5
• Changed Break-down Voltage MIN from 7.6 to 7.5 and MAX from 8.2 to 8.4 in the Specifications Electrical
Characteristics table ............................................................................................................................................................... 5
Vrwm leakage
Device Vrwm Vclamp at Ipp Ipp (8/20 µs) Package Options Polarity
(nA)
TVS0500 5 9.2 43 0.07 SON Unidirectional
TVS1400 14 18.4 43 2 SON Unidirectional
TVS1800 18 22.8 40 0.5 SON Unidirectional
TVS2200 22 27.7 40 3.2 SON Unidirectional
TVS2700 27 32.5 40 1.7 SON Unidirectional
TVS3300 33 38 35 19 WCSP, SON Unidirectional
GND 1 6 IN
GND 2 GND 5 IN
GND 3 4 IN
Pin Functions
PIN
TYPE DESCRIPTION
NAME No.
IN 4, 5, 6 I ESD and surge protected channel
1, 2, 3, exposed thermal
GND GND Ground
pad
7 Specifications
7.1 Absolute Maximum Ratings
TA = 27℃ (unless otherwise noted) (1)
MIN MAX UNIT
IEC 61000-4-5 Current (8/20 µs) 43 A
Maximum IEC 61000-4-5 Power (8/20 µs) 400 W
Surge IEC 61643-321 Current (10/1000 µs) 20 A
IEC 61643-321 Power (10/1000 µs) 180 W
IEC 61000-4-5 Current (8/20 µs) 50 A
Maximum IEC 61000-4-5 Power (8/20 µs) 80 W
Forward Surge IEC 61643-321 Current (10/1000 µs) 23 A
IEC 61643-321 Power (10/1000 µs) 60 W
EFT IEC 61000-4-4 EFT Protection 80 A
IBR DC Breakdown Current 50 mA
IF DC Forward Current 500 mA
TA Ambient Operating Temperature -40 125 °C
Tstg Storage Temperature -65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017–2019, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: TVS0500
TVS0500
SLVSED2C – DECEMBER 2017 – REVISED NOVEMBER 2019 www.ti.com
45 12 48
TVS0500 Voltage 11 -40°C 44
40 Surge Current Current (A)
10 40
Voltage (V) / Surge Current (A)
35 25°C
9 105°C 36
30 8 125°C 32
Voltage (V)
25
6 24
20
5 20
15 4 16
10 3 12
2 8
5
1 4
0 0 0
-5 -1 -4
0 10 20 30 40 50 0 10 20 30 40 50 60
Time (Ps) D001
Time (Ps) D002
125
Leakage (nA)
240
100
200
75
160
50
120
80 25
0 V Bias
40 2.5 V Bias 0
5 V Vias
0 -25
-40 -20 0 20 40 60 80 100 120 140 160 180 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) D003
Temperature (°C) D004
0.4
0
0.3
-0.0003
0.2
-0.0006
-0.0009 0.1
-0.0012 0
-1 0 1 2 3 4 5 6 7 8 9 -40 -20 0 20 40 60 80 100 120 140
Voltage (V) D005
Temperature (°C) D006
7.95 25
Ipp (A)
7.9
7.85 20
7.8
7.75 15
7.7
10
7.65
7.6 5
7.55
7.5 0
-40 -20 0 20 40 60 80 100 120 140 -50 -30 -10 10 30 50 70 90 110 130
Temperature (°C) D007
Temperature (°C) D008
Figure 7. Breakdown Voltage (1 mA) vs Temperature Figure 8. Max Surge Current (8/20 µs) vs Temperature
100
Leakage (-40qC)
90 Leakage (25qC)
80 Leakage (85qC)
Leakage (105qC)
Dynamic Leakage (mA)
70 Leakage (125qC)
60
50
40
30
20
10
0
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3
Slew Rate (V/Ps) D009
8 Detailed Description
8.1 Overview
The TVS0500 is a precision clamp with a low, flat clamping voltage during transient overvoltage events like surge
and protecting the system with zero voltage overshoot.
IN
GND
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
B2
IN
TVS0500
GND
A2
11 Layout
GND Plane
Connector Protected
I/O
I/O
I/O
Input Input
GND
GND
GND
GND
12.3 Trademarks
E2E is a trademark of Texas Instruments.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 28-Sep-2021
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TVS0500DRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1HRH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Nov-2019
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Nov-2019
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRV 6 WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A SCALE 5.500
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2.1 A
B
1.9
0.8
0.7 C
SEATING PLANE
0.08 C
(0.2) TYP
1 0.1 0.05
EXPOSED 0.00
THERMAL PAD
3
4
2X
7
1.3 1.6 0.1
6
1
4X 0.65
0.35
6X
PIN 1 ID 0.3 0.25
6X
(OPTIONAL) 0.2 0.1 C A B
0.05 C
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
(1)
1 7
6X (0.3) 6
SYMM (1.6)
(1.1)
4X (0.65)
4
3
( 0.2) VIA
TYP (1.95)
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
6X (0.45)
METAL
1 7
6X (0.3) 6
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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