Shivam Dubey LAB report file 18BEE0026

SCHOOL OF ELECTRICAL ENGINEERING

LAB MANUAL / RECORD
On

EEE 4028
VLSI DESIGN LABORATORY

Name: Shivam Dubey

Register Number: 18BEE0026
Lab Slot: L51+L52

This work is submitted in partial fulfilment of the requirement of the award of the degree of
Bachelor of Technology in EEE/EIE

Internal Examiner External Examiner

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 Shivam Dubey LAB report file 18BEE0026

INDEX

Sl.No Date Title Marks Page No.

18-
1. February- 4-BIT RIPPLE CARRY ADDER Previous report
2021
25-
2 February CARRY SAVE ARRAY MULTIPLIER Previous report
2021

4- March
3 CARRY LOOK-AHEAD ADDER Previous report
2021

18-March
4 BOUGH-WOOLEY MULTIPLIER Previous report
2021

24-March
5 WALLACE TREE MULTIPLIER Previous report
2021

01-April
6 DADDA TREE MULTIPLIER 4-9
2021

08-April
7 SQUARER DESIGN 10-18
2021

15-April
8 PIPELINED MAC DESIGN 19-25
2021

29-April
9 FIR FILTER DESIGN 26-31
2021

13-May
10 DCT DESIGN 32-36
2021

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Shivam Dubey LAB report file 18BEE0026

Objectives:

 To provide students with the background needed to design, develop,

and test digital arithmetic circuits using IEEE standard Verilog HDL.

 To provide an understanding complex arithmetic circuit design principles and

its architecture design.

Outcomes:

 After completion of this course the students will be familiar with

design and implementation of Digital Arithmetic building blocks using
Verilog HDL and Modelsim Design Flow.

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Shivam Dubey LAB report file 18BEE0026

Exp.No: 6
Date : 01-April-2021

DADDA TREE MULTIPLIER

AIM:
Design a 4-bit Dadda Tree Multiplier using Adders (Half and Full).

REQUIRED SOFTWARE:
Modelsim PE student edition 10.4a

CIRCUIT DIAGRAM:

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Verilog Design code:

module dadda_tree_mul_4bit(input[3:0] a, b, output [7:0] p);
wire[17:1] w;
assign p[0] = (a[0] & b[0]);
ha_df ha1((a[0] & b[3]), (a[1] & b[2]), w[1], w[2]);
ha_df ha2((a[1] & b[3]), (a[2] & b[2]), w[3], w[4]);
ha_df ha3((a[0] & b[2]), (a[1] & b[1]), w[5], w[6]);
fa_df fa1((a[2] & b[1]), (a[3] & b[0]), w[1], w[7], w[8]);
fa_df fa2((a[3] & b[1]), w[2], w[3], w[9], w[10]);
fa_df fa3((a[3] & b[2]), (a[2] & b[3]), w[4], w[11], w[12]);
ha_df ha4((a[0] & b[1]), (a[1] & b[0]), p[1], w[13]);
fa_df fa4((a[2] & b[0]), w[5], w[13], p[2], w[14]);
fa_df fa5(w[7], w[6], w[14], p[3], w[15]);
fa_df fa6(w[9], w[8], w[15], p[4], w[16]);
fa_df fa7(w[11], w[10], w[16], p[5], w[17]);
fa_df fa8((a[3] & b[3]), w[12], w[17], p[6], p[7]);
endmodule

Verilog test bench code:

`timescale 1ns/1ps
module dadda_tree_mul_4bit_test;
reg[3:0] a, b;
wire[7:0] p;
reg[7:0] check;
dadda_tree_mul_4bit uut(.a(a), .b(b), .p(p));
initial repeat(10) begin
a = $random;

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Shivam Dubey LAB report file 18BEE0026

b = $random;
check = a * b;
#10;
$display($time, " %d * %d = %d (%d)", a, b, p, check);
end
endmodule

SNAPSHOTS:
Design code

Test bench code

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Shivam Dubey LAB report file 18BEE0026

Output Verification

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Shivam Dubey LAB report file 18BEE0026

OUTPUT:

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Shivam Dubey LAB report file 18BEE0026

CONSOLE OUTPUT

RESULT:
Successfully the 4-bit Dadda Tree Multiplier is designed and its output verified.

INFERENCE:
In this experiment learnt about how to construct Dadda Tree Multiplier using
Half and Full Adders.

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Exp.No: 7
Date : 08-April-2021

SQUARER DESIGN

AIM:
To design a 4-bit and 6-bit Squarer using Half and Full Adders.

REQUIRED SOFTWARE:
Modelsim PE student edition 10.4a

CIRCUIT DIAGRAM:
(4 bit)

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Shivam Dubey LAB report file 18BEE0026

(6 bit)

Verilog Design code:

4 bit
module sqrr(input [3:0]a, output [7:0]p);
wire [4:1]w;
assign p[0]=a[0];
assign p[1]=1'b0;
assign p[2]=a[1]&~a[0];
ha_df ha1(a[1]&a[0],a[2]&a[0],p[3],w[1]);
fa_df fa1(a[2]&~a[1],a[3]&a[0],w[1],p[4],w[2]);
fa_df fa2(a[3]&a[1],a[2]&a[1],w[2],p[5],w[3]);
ha_df ha2(a[3]&~a[2],w[3],p[6],w[4]);
ha_df ha3(a[3]&a[2],w[4],p[7]);
endmodule

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Shivam Dubey LAB report file 18BEE0026

(6 bit)
module SQUARER_6BIT(input signed[5:0]a,output signed[12:0]p);
wire[20:1]w;
supply0 zero;
//FIRST STAGE
assign p[0]=a[0];
assign p[1]=zero;
assign p[2]=(a[1]&~a[0]);
ha_df ha1((a[1]&a[0]),(a[2]&a[0]),p[3],w[1]);
ha_df ha2((a[2]&~a[1]),(a[3]&a[0]),w[2],w[3]);
fa_df fa1((a[2]&a[1]),(a[4]&a[0]),(a[3]&a[1]),w[4],w[5]);
fa_df fa2((a[3]&~a[2]),(a[5]&a[0]),(a[4]&a[1]),w[6],w[7]);
fa_df fa3((a[3]&a[2]),(a[1]&a[5]),(a[2]&a[4]),w[8],w[9]);
ha_df ha3((a[4]&~a[3]),(a[2]&a[5]),w[10],w[11]);
ha_df ha4((a[4]&a[3]),(a[3]&a[5]),w[12],w[13]);
//SECOND STAGE
ha_df ha5(w[1],w[2],p[4],w[14]);
fa_df fa4(w[3],w[4],w[14],p[5],w[15]);
fa_df fa5(w[5],w[6],w[15],p[6],w[16]);
fa_df fa6(w[7],w[8],w[16],p[7],w[17]);
fa_df fa7(w[9],w[10],w[17],p[8],w[18]);
fa_df fa8(w[11],w[12],w[18],p[9],w[19]);
fa_df fa9((a[5]&~a[4]),w[13],w[19],p[10],w[20]);
ha_df ha6((a[5]&a[4]),w[20],p[11],p[12]);
endmodule

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Shivam Dubey LAB report file 18BEE0026

Test bench code

(4 bit)
`timescale 1ns/1ps;
module sqrr_test;
reg [3:0]a;
wire [7:0]p;
sqrr UUT(.a(a),.p(p));
reg [7:0] check;
initial repeat (10) begin
a=$random;
check=a*a;
#10;
$display($time, "%d*%d=%d(%d)",a,a,p,check);
end
endmodule
(6 bit)
module SQUARER_6BIT_TB;
reg[5:0]a;
wire[12:0]p;
reg[12:0]check;
SQUARER_6BIT uut(.a(a),.p(p));
initial repeat (12) begin
a=$random;
check=a*a;
#12 $display($time," %d*%d=%d[%d]",a,a,p,check);
end
endmodule

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Shivam Dubey LAB report file 18BEE0026

SNAPSHOTS:
Design code
(4 bit)

6 bit

Verilog test bench code

4 bit

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Shivam Dubey LAB report file 18BEE0026

6 bit

OUTPUT:
(4 bit)

(6 bit)

CONSOLE OUTPUT
(4 bit)

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Shivam Dubey LAB report file 18BEE0026

(6 bit)

Output Verification

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Shivam Dubey LAB report file 18BEE0026

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Shivam Dubey LAB report file 18BEE0026

RESULT:
Successfully the 4-bit and 6-bit Squarer is designed and its output verified.

INFERENCE:
In this experiment we learnt how to construct 4 bit and 6 bit squarer using half
and full adders.

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Shivam Dubey LAB report file 18BEE0026

Exp.No: 8
Date : 15-April-2021

PIPELINED MAC DESIGN

AIM:
To design a 4-bit pipelined MAC using Registers.

REQUIRED SOFTWARE:
Modelsim PE student edition 10.4a

CIRCUIT DIAGRAM:

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Shivam Dubey LAB report file 18BEE0026

Verilog Design code:

//Register 4 bit
module reg_4bit(input [3:0]d,input clk,rst, output reg[3:0]q);
always@(posedge clk or negedge rst)
if(!rst)
q<=4'b0000;
else
q<=d;
endmodule

//Register 8 bit
module reg_8bit(input [7:0]d,input clk,rst, output reg[7:0]q);
always@(posedge clk or negedge rst)
if(!rst)
q<=8'b00000000;
else
q<=d;
endmodule

//Register 10 bit
module reg_10bit(input [9:0]d,input clk,rst, output reg[9:0]q);
always@(posedge clk or negedge rst)
if(!rst)
q<=10'b0000000000;
else
q<=d;
endmodule

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Shivam Dubey LAB report file 18BEE0026

//MAC
module MAC(input[3:0]a,b,input clk,rst,output[9:0]y);
wire [3:0]w1, w2;
wire [7:0]w3, w4;
wire [9:0]w5, w6;
reg_4bit R1(a, clk, rst, w1);
reg_4bit R2(b, clk, rst, w2);
reg_8bit R3(w3, clk, rst, w4);
reg_10bit R4(w5, clk, rst, w6);
assign w3 = w1 * w2;
assign w5 = w4 + w6;
assign y = w6;
endmodule

Verilog test bench code:

module mac_test();
reg [3:0]a, b;
reg rst, clk;
wire [9:0]y;
MAC UUT(a, b, clk, rst, y);
initial begin
rst = 1'b0;
clk = 1'b0;
#10;
rst = 1'b1;
a = 5;

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Shivam Dubey LAB report file 18BEE0026

b = 4;
#50;
end
always #5 clk=~clk;
endmodule

SNAPSHOTS:
Design code

Test bench code

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Shivam Dubey LAB report file 18BEE0026

OUTPUT:

CONSOLE OUTPUT
(NA)

Output Verification

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Shivam Dubey LAB report file 18BEE0026

RESULT:
The Pipelined MAC is succesfully designed using registers and output is
verified.

INFERENCE:
In this experiment we learnt how to design and construct a Pipelined MAC
using registers.

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Shivam Dubey LAB report file 18BEE0026

Exp.No: 9
Date : 29-April-2021

FIR FILTER DESIGN

AIM:
To design a FIR Filter using registers.

REQUIRED SOFTWARE:
Modelsim PE student edition 10.4a

CIRCUIT DIAGRAM:

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Shivam Dubey LAB report file 18BEE0026

Verilog Design code:

module FIR(input [3:0]x, input clk, rst, output [9:0] y);
wire [3:0] w1, w2, w3, w4;
wire [7:0] w5, w6, w7, w8;
wire [9:0] w9, w10;
parameter b0 = 4'b0001;
parameter b1 = 4'b0010;
parameter b2 = 4'b0011;
parameter b3 = 4'b0100;
reg_4bit r1(x, clk, rst, w1);
reg_4bit r2(w1, clk, rst, w2);
reg_4bit r3(w2, clk, rst, w3);
reg_4bit r4(w3, clk, rst, w4);
assign w5 = b0 * w1;
assign w6 = b1 * w2;
assign w7 = b2 * w3;
assign w8 = b3 * w4;
assign w9 = w5 + w6;
assign w10 = w7 + w9;
assign y = w8 + w10;
endmodule

Verilog test bench code:

module FIR_tb;
reg clk, rst;
reg [3:0] x;
wire [9:0] y;

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Shivam Dubey LAB report file 18BEE0026

FIR UUT(x, clk, rst, y);

initial begin
clk = 1'b0;
rst = 1'b0;
#15;
rst = 1'b1;
x = 4'b0001;
#10;
x = 4'b0010;
#10;
x = 4'b0011;
#10;
x = 4'b0100;
#10;
x = 4'b0000;
end
always #5 clk = ~clk;
endmodule
SNAPSHOTS:
Design code

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Shivam Dubey LAB report file 18BEE0026

Test bench code

OUTPUT:

CONSOLE OUTPUT
(NA)

Output Verification

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Shivam Dubey LAB report file 18BEE0026

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Shivam Dubey LAB report file 18BEE0026

RESULT:
The FIR Filter is designed and the output verified.

INFERENCE:
We learnt to design a FIR Filter using registers.

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Shivam Dubey LAB report file 18BEE0026

Exp.No: 10
Date : 13-May-2021

DCT DESIGN (discrete cosine transform)

AIM:
To design a 4-bit DCT using arithmetic operators

REQUIRED SOFTWARE:
Modelsim PE student edition 10.4a

CIRCUIT DIAGRAM:

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Shivam Dubey LAB report file 18BEE0026

Verilog Design code:

module dct(input signed[3:0]a0,a1,a2,a3,output signed [11:0]y0,y1,y2,y3 );
wire signed [4:0] m0,m1,p0,p1;
wire signed [5:0] w1,w2;
parameter c1=1;
parameter c2=2;
parameter c3=3;
assign m0=a0-a3;
assign m1=a1-a2;
assign p0=a0+a3;
assign p1=a1+a2;
assign w1=p0+p1;
assign w2=p0-p1;
assign y0=w1*c2;
assign y1=(m0*c1)+(m1*c3);
assign y2=w2*c2;
assign y3=(m0*c3)-(m1*c1);
endmodule

Verilog test bench code:

module DCT_tb();
reg [3:0]a0,a1,a2,a3;
wire signed [11:0]y0,y1,y2,y3;
dct UUT(.a0(a0),.a1(a1),.a2(a2),.a3(a3),.y0(y0),.y1(y1),.y2(y2),.y3(y3));
initial repeat(10)begin
a0=1;
a1=2;

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Shivam Dubey LAB report file 18BEE0026

a2=3;
a3=4;
#10;
end
endmodule

SNAPSHOTS:
Design code

Test bench code

OUTPUT:

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Shivam Dubey LAB report file 18BEE0026

CONSOLE OUTPUT
(NA)

Output Verification

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Shivam Dubey LAB report file 18BEE0026

RESULT:
The DCT is designed and its output verified.

INFERENCE:
We learnt to design DCT using arithmetic operators.

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