Lab Session # 3

Complex Logic Design (Code Converter)

1. Introduction
In this experiment, you will get introduced to the design of multi-input to multi-output circuits. In
addition, you will design and implement code converter using Quartus II Software.

2. Objectives
By the end of this lab experiment, students will:
• Be able to build complex logic circuits
• Be familiar with the concept of code conversion.
• Fit a synthesized circuit into a Cyclone IV E FPGA on Altera DE2-115 board.
• Assign circuit inputs and outputs to specific pins on the FPGA.
• Program and configure the FPGA to test the design physically using switches and LEDs.

3. Multi-Input to Multi-Output Circuits

Multi-Input to Multi-Output circuits has more than one input and more than one output. Figure 1 shows
an example of such circuit, which has n inputs labeled w0 to wn, and m outputs labeled output0 to
outputm. A common example of Multi-Input to Multi-Output circuits is code converter circuits.

The main concept of code converters is to convert from one type of input encoding to a different output
encoding. The availability of a large variety of codes for the same information results in the use of
different codes by different digital systems. It is sometimes necessary to use the output of one system as
input to another. A conversion circuit must be inserted between the two systems if each one uses
different code to represent the same information. Thus, a code converter is a circuit that makes two
systems compatible even though if each one uses a different encoding for its input.

To convert from binary code A to binary code B, input lines must supply bit combination as specified by
code A and the circuit must generate the corresponding output bit combination of code B. A
combinational circuit performs this transformation by means of logic gates. The design procedure will be
illustrated by the next example that converts a 3-bit binary digit to Excess-3 code.

Figure 1: Multi-Input to Multi-Output Circuit

4. Design Procedure
The design of combinational circuit starts with problem definition, which is solved by designing
appropriate logic circuit. The procedure involves the following steps;

1. From the specification of the circuit, determine the required number of inputs and outputs
and assign a symbol to each one of them, if they were not given in the problem statement.
2. Derive the truth table that defines the required relationship between inputs and outputs.
3. Obtain the simplified Boolean functions using Boolean algebra for each output as a function
of input variables.
4. Draw the logic diagram (graphical design) or write a Verilog code representing your design.
5. Simulate and check the functionality of the designed circuit.
6. Fit and analyze design performance of your design and download your design to the Altera
Cyclone IV E FPGA board to physically verify correctness of the design.

Problem Statement: Designing Binary to Excess-3 Code Converter

Design a binary to Excess-3 Code Converter that takes the numbers from 0 to 7 as inputs in binary format
(000, 001,…, 111) and displays the corresponding 4-bit excess-3 code. Simulate the designed circuit using
the waveform editor to verify its functionality. Also, test your design on Altera DE2-115 Board.

Step 1: Identifying Number of Inputs and Outputs

From the specification of the circuit, we can find out that:
1. The code converter has three inputs and four outputs.
2. The three inputs are designated as A, B, and C.
3. The four outputs are specified as W, X, Y and Z.

Step 2: Truth Table Preparation

The rows in the truth table are obtained from the 2n combinations of the n input variables. The 3-bit
binary numbers range from 0 in decimal (000 in binary) up to 7 in decimal (111 in binary). Excess-3 code
range from 3 in decimal (0011 in binary) up to 10 in decimal (1010 in binary). The relationship between
binary and excess-3 codes are listed in Table 1.
 Table 1: Truth Table for Binary to Excess-3 Code Converter

Inputs Binary Outputs Excess-3 Code

A B C W X Y Z

0 0 0 0 0 1 1

0 0 1 0 1 0 0

0 1 0 0 1 0 1

0 1 1 0 1 1 0

1 0 0 0 1 1 1

1 0 1 1 0 0 0

1 1 0 1 0 0 1

1 1 1 1 0 1 0

Step 3: Deriving Simplified Boolean Expressions

1. From Table 1, take one output column, to which you will develop the logic expression for.
2. Find the minterms from the output column you have chosen (rows having value 1). For example,
output W in table 1 has three 1's; therefore, the logic expression for W has three minterms (if the
is to be represented in sum of product form).
3. Use Boolean Algebra to simplify the logic expression for the simplest SOP. You may alternatively
use any other method to simply this expression such as k-map or computer based simplification
program. The following example shows how output W expression is simplified using Boolean
Algebra properties.

Example:
For the output W:

W = A B' C + A B C' + A B C

W = ( A B' C + A B C ) + ( A B C' + A B C )

W = ( A ( B' + B ) C ) + ( A B ( C' + C ) )

W=(A(1)C)+(AB(1))

W=(AC)+(AB)

W=AC+AB

In order to complete the design of Excess-3 converter circuit, you need to find logic
expressions for each output. Derive the expressions for X, Y, and Z by yourself.
For the output X:

For the output Y:

For the output Z:

Step 4: Design Entry
1. You can either implement the design entry as Block Diagram/Schematic or Verilog.
2. Implement your design in Verilog using the Quartus II Software.
3. Part of the code is given below. Complete the code and save.

module Excess3 ( A, …….., W, … );

input A, … ;
output W, … ;

assign W = (A & C ) | (A & B);

…
…
…

endmodule

Step 5: Simulation
1. Synthesize your design for the implemented circuit (refer to Section 3.2.5 in Lab Session#1).
2. Perform Functional Simulation (refer to Section 3.4 in Lab Session#1).

Step 6: Fit and Program Cyclone IV E FPGA on Altera DE2-115 Board

In this step, Quartus II Software will be used to:
1. Fit a synthesized circuit into a Cyclone IV E FPGA on Altera UP2 board.
2. Assign circuit inputs and outputs to specific pins on the FPGA.
3. Program and configure the FPGA to test the implemented design physically using switches and
LEDs.

Quartus II Software will generate additional files to allow the above mentioned tasks. These files are
listed in Table 2.

Table 2: Files generated by Quartus

Stage File Extension Expansion

.flow.rpt
Compilation (in main project Folder) Compilation Flow Report

.fit.rpt
Fitting (in main project Folder) Fitter Report
 .sta.rpt
Timing Analysis (in main project Folder) Timing Analyzer report file

Programming and .sof Assembler report – Stores device programming options and
Configuration (in main project Folder) information - Binary file for programming a Cyclone IV E device

Fitting and Timing Analysis

i. Save the Circuitg.bdf file by clicking on the Floppy Icon in the top menu bar.
ii. Perform Full compilation by clicking on icon that looks like a purple triangle in the
processing toolbar, as shown in Figure 2.
iii. Compilation Flow summary window (*.flow.rpt) will appear showing the number of
logic elements used by the design along with a message window identifying the longest
propagation delay paths. These two parameters are design performance measures.

iv. Record the following information for your design:

• Number of logic elements used by the design: ……...……………..

• Longest propagation delay: ………………………….……………………..

Figure 2: Processing Icons of the Top Menu Bar

Pin Assignment
DE2-115 board has hardwired connections between FPGA pins and other components available on the
board such as LEDs, switch…etc. These pins should be assigned to inputs and outputs of the circuit to
facilitate the verification of the downloaded design. To do this, follow the following steps:
i. List all the input and output signals of your design in Table 3.
ii. Refer to the pin configuration sheet for DE2-115 Board, provided to you by your
lab instructor.
iii. In order to test the circuit physically on DE2-115 Board, you need to assign inputs
and outputs to physical resources available on the board to supply input data and
observe output value. In this experiment, we will use switches (3 switches) to
supply inputs, and display the output values on LEDs (4 LEDs).
iv. Table 3 below shows how to assign input/output of your design to switches and LEDs. In
the table, a single input (i.e., A) and a single output (i.e., Z) are shown to be assigned to
pins on the board. Complete the pin assignment in the table for the remaining
inputs/outputs of your design.

Table 3: Pin Assignment

Input Selected DE2-115 Output Selected DE2-115
Signal Switch Cyclone IV E Pin Signal LED Cyclone IV E Pin
Pin
A SW2 AC27 LEDG3
SW1 LEDG2
SW0 LEDG1
Z LEDG0 E21

v. Use Quartus II Software to assign the inputs/outputs to the corresponding pins by

performing the following steps:
1. Select Assignments (top menu bar) → Pin Planner. The Pin Planner window
opens.
2. You will find a table at the bottom of the Pin Planner window. We care for the
presence of three columns (Node Name, Direction, Location).
• Node Name: Holds a list of all the nodes (inputs/outputs) in your
design
• Direction: Indicated whether this node is an input or an output
• Location: Holds the desired pin number (as specified in Table 3), which
indicated its location on Cyclone IV E DE2-115 Board.
• Both Node Name and Direction will be filled automatically by the
Quartus II Software.
• You have to enter the pin number in the Location field for every node
(as specified in Table 3)
3. Choose a row with a Node Name and under the column Location, Double-Click
and choose the allocated pin number.
4. Continue this process for all the input and output nodes
5. Close the Pin Planner window.
6. Recompile the circuit, so that it will be compiled with the correct pin
assignments.

Programming and Configuration

i. To perform the Download, and download the binary file of your design (.sof) to the
DE2-115 Board, click on the Programmer icon in the processing toolbar, as shown in
Figure 2.
ii. A new (Programmer) window opens.
iii. Make sure Hardware is setup correctly by the presence of USB-Blaster [USB0] at the
top left corner of the window (indicated by number 1 in Figure 5).
• If it shows No Hardware (as indicated by 3 in Figure 3), you will not be able to
start the downloading process (Start button will be disabled, as indicated by 1
in Figure 3).
• Follow these steps to set it up:
1. Click on Hardware Setup (indicated by 2 in Figure 3).
2. Hardware Setup window will appear (Figure 4).
 3. Click on No Hardware → Change it to USB-Blaster [USB0] (as
indicated by 1 in Figure 4)
4. Click on Close (as indicated by 2 in Figure 4)
5. Make sure the USB-Blaster [USB0] appears now at the top left corner
(as indicated by 1 in Figure 5)
iv. Check Program/Configure option (as indicated by 2 in Figure 5).
v. Make sure the correct (.sof) file name appears.
• If wrong (.sof) file name appears, or if it doesn’t appear, you can add it by
clicking Add File on the left side of the windows, and browsing for it under
output_files directory/folder located in the main Project directory/folder.
vi. Click on Start (as indicated by 3 in Figure 5).
vii. The progress of downloading is indicated by % on the top right corner of the window.
viii. Once the download process finish and show 100% Successful (as indicated by 4 in
Figure 5), check your design by setting input values using switches and observing the
output on the LEDs of the Altera DE2-115 Board.

Figure 3: No Hardware Setup

Figure 4: Hardware Setup Window

Figure 5: Downloading Process
Student Name: Date:
Student ID:

Lab Exercise # 3

Problem Statement:
Design the Excess-3 code converter circuit using Quartus II Graphic Editor, Synthesize it and test its
functionality correctness (Functional Simulation and Programming Altera DE2-115 Board).

Procedure:
1. Create a Block Diagram/Schematic design file for the given circuit (refer to Section 3.2 in Lab
Session#1).
2. Synthesize it (refer to Section 3.2.5 in Lab Session#1).
3. Perform a Functional Simulation (refer to Section 3.4 in Lab Session#1) to test your design for all
the possible test cases (Table 1).
4. Download your design to Altera DE2-115 Board to check and verify its functionality correctness.
5. Print your design files and simulation waveforms.

Ask your engineer to check your results, write his/her comments and sign below:

………………………………………………………………………………………………………………………...…………………………...……….
……………………………………………………………………………………………………………………...………………………...…………….
…………………………………………………………………………………………………………………...…………………………………………

Engineer Signature
……..……………..

Attachments:
Please attach with the lab exercise sheet printouts of the files indicated below. Don't forget to
write your Name and ID Number as comments in every file before printing.

1. Verilog code (*.v file).

2. Waveform file (*.sim.vwf file)
3. Graphical design file (*.bdf file)
4. Symbol file (*.bsf)
5. Waveform file (*.sim.vwf file)