IEEE 1149.

1 JTAG
Boundary Scan Standard

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 Purpose of Standard

• Allow test instructions and test data to be serially

fed into a component-under-test (CUT).
– Allows reading out of test results.
– Allows RUNBIST command as an instruction.
• JTAG can operate at chip, PCB, & system levels.
• Allows control of tri-state signals during testing.
• Allows other chips collect responses from CUT.
• Allows system interconnects be tested separately
from components.

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 History
• 1985
– Joint European Test Action Group (JETAG, Philips)
• 1986
– VHSIC Element-Test & Maintenance (ETM) bus standard
(IBM et al.)
– VHSIC Test & Maintenance (TM) Bus structure (IBM et al.)
• 1988
– Joint Test Action Group (JTAG) proposed Boundary Scan
Standard
• 1990
– Boundary Scan approved as IEEE Std. 1149.1-1990
– Boundary Scan Description Language (BSDL) proposed
by HP

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• 1993
– 1149.1a-1993 approved to replace 1149.1-1990
• 1994
– 1149.1b BSDL approved
• 1995
– 1149.5 (Module Test and Maintenance Bus) approved

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 Basic Chip Architecture for 1149.1

Boundary Scan Boundary Scan

Cell Path

I/O Pins Internal I/O Pins

Logic

Sin Sout

TDI Miscellaneous Registers

M
U
Instruction Register
X TDO
TRST* Bypass Register

TAP
TMS Controller TCK

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• Test Access Port (TAP)
• TAP controller
– A finite-state machine with 16 states.
• Test Data Registers
– Mandatory
• Boundary scan register
• Bypass register
• Instruction register
– Optional
• Device-id register
• Design-specific registers
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• Signals:
– TDI: Test Data In
– TDO: Test Data Out
– TMS: Test Mode Selection
– TCK: Test Clock
– TRST* (optional): Test Reset

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• Basic operation:
– Instruction sent (serially) over TDI into
instruction register.
– Selected test circuitry configured to respond
to instruction.
– Test instruction executed.
– Test results shifted out through TDO.
• New test data on TDI may be shifted in at
the same time.

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 Elementary Boundary Scan Cell

SOUT

IN 0 M OUT
U
1 X

0 M
U Mode
1 X ID Q ID Q
QA QB

SIN
ShiftDR ClockDR UpdateDR

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• Operation modes:
– Normal: Mode = 0;
IN → OUT

– Scan: ShiftDR = 1, ClockDR;

TDI → ... → SIN → SOUT → ... → TDO

– Capture: ShiftDR = 0, ClcokDR;

IN → QA, OUT driven by IN or QB

– Update: Mode = 1, UpdateDR;

QA → OUT

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 State Diagram of TAP Controller

Control of data registers Control of instruction registers

1 Test-Logic-Reset
1
0
1 1
0 Run-test/idle Select-DR-Scan Select-IR-Scan
0 0
1 1
Capture-DR Capture-IR
0 0
Shift-DR Shift-IR 1
0 0
1 1
1 1
Exit1-DR Exit1-IR
0 0
Pause-DR Pause-IR
0 0
1 1
0 0
Exit2-DR Exit2-IR
1 1
Update-DR Update-IR
1 0 1 0

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 States of TAP Controller

• Test-Logic-Reset: normal mode

• Run-Test/Idle: wait for internal test such as BIST
• Select-DR-Scan: initiate a data-scan sequence
• Capture-DR: load test data in parallel
• Shift-DR: load test data in series
• Exit1-DR: finish phase-1 shifting of data
• Pause-DR: temporarily hold the scan operation
(allow the bus master to reload data)
• Exit2-DR: finish phase-2 shifting of data
• Update-DR: parallel load from associated shift
registers

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 Instruction Set

• EXTEST
– Test interconnection between chips on board.

• SAMPLE/PRELOAD
– Sample and shift out data, or shift in data only.

• BYPASS
– Bypass data through a chip.

• Optional instructions
– INTEST, RUNBIST, CLAMP, IDCODE, HIGH-Z,
USERCODE.

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 EXTEST

Chip1 Chip2

Internal 0 Internal
1. Shift-DR (Chip1) Logic Logic
TDI Registers TDO TDI Registers
TDO
TAP Controller TAP Controller

Internal Internal
2. Update-DR (Chip1) 0 0

Logic Logic
3. Capture-DR (Chip2)
TDI Registers TDO TDI Registers
TDO
TAP Controller TAP Controller

Internal 0 Internal
4. Shift-DR (Chip2) Logic Logic

TDI Registers TDO TDI Registers

TDO
TAP Controller TAP Controller

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 SAMPLE/PRELOAD

Input
M Internal M
SAMPLE Output
U Logic U
QA QB X X
QA QB

SIN SOUT
Input
M Internal M
PRELOAD Output
U Logic U
QA QB X X
QA QB

SIN SOUT

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 BYPASS

Internal
Logic

Bypass
TDI Register TDO
(1 bit)

TAP Controller

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 INTEST

0
Internal Internal
0
Logic Logic
1.Shift-DR 2.Update-DR
TDI Registers TDO Registers TDO
TDI
TAP Controller TAP Controller

0
Internal 0 Internal
Logic 4. Shift-DR Logic
3.Capture-DR
TDI Registers TDO TDI Registers TDO

TAP Controller TAP Controller

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 Test Bus Configuration

Application chips Application chips

TDI TDI
TCK TCK
TMS #1 TMS #1
Bus TDO Bus TDO

master master
TD0 TDI
TDI TDI
TD0 TCK
TCK TMS1 #2
#2 TMS2 TMS
TDI TMS
TDO TDO
TMS TMSN
TCK TCK

TDI TDI
TCK TCK
#N TMS #N
TMS
TDO TDO

Ring configuration Star configuration

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