electronics

Article
Synchronization and Sampling Time Analysis of
Feedback Loop for FPGA-Based PMSM Drive System
Ipsita Mishra 1, *, Ravi Nath Tripathi 2,3 and Tsuyoshi Hanamoto 1
1 Department of Life Science and System Engineering, Graduate School of Life Science and Systems
Engineering, Kyushu Institute of Technology, Fukuoka 808-0196, Japan; hanamoto@life.kyutech.ac.jp
2 Next Generation Power Electronics Research Center, Kyushu Institute of Technology,
Fukuoka 808-0196, Japan; tripathi.ravi@kuas.ac.jp
3 Nagamori Actuator Research Center, Kyoto University of Advanced Science, Kyoto 6168577, Japan
* Correspondence: mishra.ipsita530@mail.kyutech.jp




Received: 28 September 2020; Accepted: 11 November 2020; Published: 13 November 2020


Abstract: The proportional-integral (PI)-based control for the motor drive system is commonly
used in industrial applications. However, motor drive system development and prototyping are
tedious tasks especially considering a field programmable gate array (FPGA)-based real-time system
implementation. In addition, the time-synchronization of the feedback control loop is another
vital aspect concerning sampling time for the discrete-time controller. This paper presents an
FPGA-based design and development of a permanent magnet synchronous motor (PMSM) drive
system considering the impact of time-synchronization corresponding to the sampling time criteria
for a feedback control loop. Furthermore, the repercussion of time-synchronization is examined for
the transient conditions due to a step change in load as well as motor speed. The field-oriented control
(FOC) of the PMSM drive system is designed and implemented for the system authentication using
a digital model integration approach provided by the Xilinx system generator (XSG) and VIVADO
platform. Moreover, harmonic distortion in the motor current is considered for an in-depth analysis
of the system performance corresponding to sampling time as well as switching frequencies.

Keywords: field programmable gate array; field-oriented control; permanent magnet synchronous
motor; Xilinx system generator; time-synchronization

1. Introduction
The energy conversion is an essential part of an electrical power system. The electrical motors
are one of the major parts of electromechanical energy conversion (EMEC) system that is used for
conversion of electrical energy into mechanical energy. The motors have been used in a wide variety
of applications from industrial systems to domestic appliances [1–4]. Due to the advantages such as
high power density, high torque to weight ratio, higher efficiency and lower maintenance cost the
permanent magnet synchronous motor (PMSM) has been used in low power range applications such
as robotics, actuators and machine tools as well as in high power applications for industrial drives,
vehicular propulsions, aerospace system and traction [5–8].
The controlled operation of a motor is highly essential corresponding to system applications
to achieve the desired motor speed and smooth transition considering the change in motor load
conditions. Several linear and nonlinear controls have studied and implemented PMSM speed control.
The nonlinear controls such as hysteresis control and predictive control are implemented for the
motor drive system [9–11]. These controllers have their own advantage; however, they have a better
performance at higher sampling time. In the linear control such as the proportional-integral (PI)-based
field-oriented control (FOC) PMSM drive has been implemented for industrial applications because of

Electronics 2020, 9, 1906; doi:10.3390/electronics9111906 www.mdpi.com/journal/electronics

Electronics 2020, 9, 1906 2 of 19

its simple structure and reliability [12,13]. This controller implementation reproduces the dynamic
behavior of the PMSM similar to that of the DC motor [14].
The control algorithm for the motor drive system has been developed using digital signal
processors (DSPs) [15–17]. However, the DSP-based implementations suffer from long execution
time and high memory allocation of the CPU. Considering the above demerits of the DSP, the field
programmable gate array (FPGA) having advantages of parallel processing, programmable hard-wired
feature, fast computation ability, shorter design cycle and an embedded processor, is more effective
for the controller execution [18–20]. In [21], an FPGA-based FOC for PMSM drive is developed,
and for the FPGA-based architecture for the sensor, less speed control of PMSM is presented
in [22]. FPGA-based PMSM drive system development has not been scrutinized considering
time-synchronization for a feedback control loop concerning its implications on system performance
especially in transient conditions.
The feedback control loop of the motor drive system consists of a speed controller (outer control
loop) and a current controller (inner control loop). The time constant of the speed controller loop is
different to the current control loop [23]. The performance of the motor drive system is governed by
the bandwidth of the current control and switching frequency selection is crucial to achieve the desired
bandwidth [24,25]. However, the increase in switching frequency will ultimately lead to the higher
system losses.
Besides the switching frequency, the digital implementation of control involves the vital role of
sampling frequency for the performance of a motor drive system [26]. Nevertheless, the sampling
frequency is having a vital impact on system performance especially during the transient condition.
There are no specific criteria available to decide the appropriate selection of sampling frequency. In [26],
a lower limit is mentioned corresponding to a specific control and the bandwidth can be taken as one
sixth of the sampling frequency. Furthermore, the digital delay of the control loop that consists of the
throughput time of the AD converter, delay introduced by the converter in terms of dead time and
computation time for the control execution constrained the controller bandwidth [24]. Consequently,
the role of sampling frequency involves more complexity considering the performance of a motor
drive system.
In general, the sampling rate of the speed controller is slower compared to that of the sampling
rate of the current controller. As the control loops operate at different data sampling rate, the impact
of time synchronization between these controllers is a crucial concern considering the transient
conditions corresponding to the sampling rates. The motor speed is related to mechanical parameter
and the sampling rate is predefined corresponding to the encoder setting. The sampling rate of the
motor current is possible to control, corresponding to the maximum possible throughput rate of the
AD converter. Consequently, the performance of the current control loop can be influenced under
transient condition.
In the case of a motor drive system, the impact of sampling frequencies (throughput rates) is not
yet analyzed categorically. The impact of sampling frequencies is required to probe the performance of
the controller under transient conditions because the higher throughput rate will not necessarily result
in improved performance. In addition, the indirect impact of throughput rate on speed controller is also
one of the key points corresponding to a change in the reference speed of the motor. The repercussion
of time synchronization on control loops corresponding to sampling frequencies is another crucial
concern considering the transient conditions: change in reference speed and load disturbance.
This paper presents an FPGA-based design and development of a PMSM drive system considering
the impact of time-synchronization for feedback control loops corresponding to sampling frequencies.
A step-by-step and case-by-case time synchronization methodology is considered to analyze the
repercussion of sampling frequencies corresponding to feedback control loop synchronization.
The harmonics in a motor current are also taken into account for different switching frequencies and
sampling frequencies correspondingly. Furthermore, a step change in reference speed as well as load
disturbance is introduced to investigate the transient/dynamic behavior of the system. The controller is
Electronics 2020, 9, 1906 3 of 19

developed in the Xilinx system generator (XSG) environment integrated with the MATLAB/Simulink
for the FPGA-based experimental system implementation.
The paper is organized as follows: Section 2 describes the mathematical model of PMSM,
the controller designing and the step by step XSG based system implementation. The FPGA based
system implementation is described in the Section 3. The experimental validation of the system
performance is explained in the Section 4. Finally, the conclusions of the paper are presented in
Section 5.

2. PMSM Drive
The motor structure consists of stator and rotor parts. The rotor part is responsible for the
generation of the rotating magnetic field. The interaction between the rotor flux and the stator flux
provides the desired torque. The stator dynamic equations in the rotating dq reference frame is give as:

did Rs 1
= − id + ωe iq + vd (1)
dt Ls Ls

diq Rs 1 ϕωe
=− iq − ωe id + vq − (2)
dt Ls Ls Ls
The id and iq represent the stator current components in dq frame. Ls and Rs represents the stator
winding inductance and resistance. vd and vq are the stator voltage component in the dq rotating
frame corresponding to the three-phase stator voltage. The rotor electrical angular speed and the flux
produced by the rotor magnet are represented by ωe and ϕ.
In case of the surface permanent magnet synchronous motor (SPMSM) the q axis current component
is only responsible for the generation of the required torque. Mathematically the electromagnetic
torque Te generation is given by:
3
Te = ϕiq (3)
2
The mechanical dynamics of the motor have slower response compared to that of the electrical
dynamics. Mathematically the mechanical dynamics of the motor can be described as:

dωm 1
= {Te − Tl − Bωm } (4)
dt J

where ωm is the rotor angular mechanical speed, Tl is the mechanical load torque, J is the moment of
inertia and B is the viscous friction coefficient. The rotor electrical angular speed ωe and the electrical
angular position θe are given by:
ωe = pp ωm (5)
Z
θe = pp ωm dt (6)

where, pp represents the number of pole pairs of the motor.

2.1. Field Oriented Control

The field-oriented control for the speed control of the PMSM is presented in the Figure 1. The FOC
is a simple vector control which can control both the phase as well as the phase current magnitude
of the motor. The implementation methodology of the control includes a speed control loop and the
current control loop. Finally, the switching signal is generated for the power devices of the inverter.
Electronics 2020, 9, 1906 4 of 19
Electronics 2020, 9, x 4 of 19

Figure 1.
Figure 1. Field-oriented control
Field-oriented (FOC)-based
control permanent
(FOC)-based magnet
permanent synchronous
magnet motormotor
synchronous (PMSM) drive
(PMSM)
system.
drive system.

evaluates the
The speed control loop evaluates the reference
reference quadrature
quadrature axis currentiiqref
axis current qref to control the current

magnitude corresponding
magnitude correspondingtotothethe
speedspeed
andand
loadload torque
torque of the of the motor.
motor. The iqrefThe
in the iqrefstationary
in the stationary
reference
reference
frame frame is by
is evaluated evaluated
feeding by
thefeeding the speed
speed error signalerror signal
through through PIThe
PI controller. controller.
equationThe equation
involved for
involved
the for the
generation ofgeneration of the
the reference reference
current signalcurrent
is givensignal
as: is given as:
 K ω 
*
i∗qiq== KKpω + Kiiω ω
ωer
ss  er
pω + (7)
(7)


where ss is the Laplace

where Laplace operator
operator andand ωωerer is the error between the reference speed ω* ω* and the measured
speed, represented as:
ωer = ω∗* − ωe (8)
ωer = ω − ωe (8)
id and iq are obtained from the sensed three phase current of motor using the Clarke’s and Park’s
id and iq are obtained
id and iq from the sensed arethree phase current ofimotor using the Clarke’s and Park’s
Transformations. are compared the reference current dref and iqref, respectively. idref is kept
Transformations.
as zero, as the motor id and iq arefor
torque compared
a SPMSM are the reference
depends upon the current idref and axis
quadrature iqref, respectively.
current [27]. iThe
dref is kept
error
as zero, as the motor torque for a SPMSM depends upon the quadrature
signals ider and iqer are converted to the equivalent voltages vd and vq , respectively through axis current [27]. Thethe error
PI
signals ider and iqer are converted to the equivalent voltages vd and vq, respectively through the PI
controller. The following represent the d-q axis reference voltage equations:
controller. The following represent the d-q axis reference voltage equations:
K
 
vd = Kpd + K idid ider (9)
vd =  K pd + s  ider (9)
 s 
ider = i∗d − id (10)
ider = id* − id ! (10)
Kiq
vq = Kpq + i (11)
 Ksiq  qer
vq =  K pq +  iqer (11)
 = iq −siq 
∗
iqer (12)

2.2. Controller Design in XSG iqer = iq* − iq (12)

XSG is a digital designing tool integrated with the MATLAB/Simulink and can be used for the
2.2. Controllersystem
FPGA-based Designdevelopment.
in XSG The model-based design in XSG has the functionality for automatic
generation of the hardware description language (HDL) code that can be readily used for the real-time
XSG is a digital designing tool integrated with the MATLAB/Simulink and can be used for the
operation of FPGA-based system. FOC-based speed control of the PMSM drive system is designed
FPGA-based system development. The model-based design in XSG has the functionality for
and modelled in MATLAB/Simulink using XSG blockset. The modelling of the FOC is considered in
automatic generation of the hardware description language (HDL) code that can be readily used for
three parts which is explained in detail.
the real-time operation of FPGA-based system. FOC-based speed control of the PMSM drive system
Electronics 2020, 9, x 5 of 19

is designed and modelled in MATLAB/Simulink using XSG blockset. The modelling of the FOC is
Electronics 2020, 9, 1906 5 of 19
considered in three parts which is explained in detail.

2.2.1.
2.2.1. Outer
Outer Speed
Speed Control
Control Loop
Loop
The
The outer
outer control
controlloop
loopofofthe
theFOC
FOC consists
consistsof of
a PIa controller to regulate
PI controller the motor
to regulate speed.
the motor The
speed.
implementation of the speed controller in XSG is presented in the Figure 2a. The
The implementation of the speed controller in XSG is presented in the Figure 2a. The PI controller PI controller
implementation
implementation in in FPGA
FPGA using
using discrete-time
discrete-time domain
domain platform
platform ofof XSG,
XSG, requires
requires the
the discretization
discretization of
of
dynamic Equation (7).
dynamic Equation (7). Euler’s forward method is used [28] for the discretization ofcontroller.
Euler’s forward method is used [28] for the discretization of the The
the controller.
discretized equation
The discretized for the
equation forPI
thecontrol is presented
PI control as: as:
is presented
i* (k ) = K ω (k ) + g ( k )
i∗q (qk) = Kpωpωωerer(k) + gωω (k) (13)
gωg(ωk()k =) =ggωω((kk−−11)) ++KKiωiωTsTωserω(erk()k) (13)

where
where ii∗qq*(k) andωωer(k)
(k) and (k) are
arethe
thereference
referenceq qaxis
axisstator
stator current
current and
and speed
speed error
error at the
at the instant
instant k. gωk.(k)
gωis
(k)the
is
er
the output of the integral control at the instant k. Ts is the sampling time.
output of the integral control at the instant k. Ts is the sampling time.

(a) (c)

(b) (d)

Figure 2. PMSM
Figure 2. PMSM drive
drivesystem
systemmodel
modelforforFOC
FOC inin a Xilinx
a Xilinx system
system generator
generator (XSG)
(XSG) (a) speed
(a) speed control
control loop
loop (b) abc-dq transformation (c) current control loop (d) dq-abc transformation.
(b) abc-dq transformation (c) current control loop (d) dq-abc transformation.

Inner Current
2.2.2. Inner Current Control
Control Loop

The control of the dc dc motor

motor is
is easier
easier as
asthe
thespeed
speedisisdirectly
directlyproportional
proportional to
tothe
thecurrent.
current.However,
However,
in case of the ac motor in in order
order to achieve
achieve similar
similar kind
kind of
of behavior,
behavior, the co-ordinate transformation is
an essential
essential part
partofofthe
thecontroller design.
controller Initially,
design. abc-dq
Initially, transformation
abc-dq is performed
transformation using an
is performed enable
using an
signal for
enable conversion
signal form three
for conversion formphase to phase
three two phase system
to two phaseabc-αβ,
systemand subsequently,
abc-αβ, the conversion
and subsequently, the
of two-phase
conversion of system
two-phase to synchronously rotating frame
system to synchronously αβ-dq
rotating transformation
frame using sin-cos
αβ-dq transformation shown
using in
sin-cos
the Figure
shown 2b.Figure 2b.
in the
Electronics 2020, 9, 1906 6 of 19
Electronics 2020, 9, x 6 of 19

inner current control loop, two PI controllers are used as shown

In the inner shown in Figure
Figure 2c
2c to
to generate
generate
an equivalent voltage quantity for generation of switching signals. Similar
Similar to
to the
the speed
speed PI
PI controller,
controller,
the current
current PI
PI controller
controller is
is represented
represented for
for dq
dqquantity
quantityin
inthe
thediscrete-time
discrete-timedomain
domainas:as:
v ( k ) = K ider ( k ) + g d ( k )
vd (dk) = Kpdpdider (k) + gd (k) (14)
) =g g(dk( k−−11) +K (14)
gdg(kd )( k= d )+ Kid Tssiiderder( (kk))
id T

vq (k ) = K pqiqer (k ) + gq (k )
vq (k) = Kpq iqer (k) + gq (k) (15)
) =gg(qk(k−−11)
gqg(kq )(k= )+ +KiqT
Kiq iqer((kk))
Tssiqer
(15)
q

where vvdd(k) and vvqq(k) are the

where the stator
stator reference
reference voltage
voltageat atthe instantk.k.ider
theinstant and iiqer
ider(k) and qer(k) are the current

error signal
signal at the instant k.
the instant k. gdd (k) and ggqq (k)
(k) and (k) are
are the
the output
output ofof the
the integral
integral control
control atat the
the instant k.
instant k.
Further,
Further,dq-abc
dq-abctransformation
transformation is performed,
is performed, as shown in Figure
as shown 2d to 2d
in Figure convert into three
to convert intophase
threevoltage
phase
quantity for the generation
voltage quantity of the switching
for the generation signal. signal.
of the switching

2.2.3. Switching Signal

2.2.3. Switching Signal Generation
Generation
The
The SineSinetriangle
trianglepulse width
pulse widthmodulation
modulation(SPWM) is considered
(SPWM) for the generation
is considered of the switching
for the generation of the
signal. The switching signal is generated using a PWM technique that requires
switching signal. The switching signal is generated using a PWM technique that requires a carrier a carrier wave and
modulating wave. The triangular waveform as a carrier signal
wave and modulating wave. The triangular waveform as a carrier signal of frequency of frequency f , is generated
sw fsw, is generated by
using the fundamental
by using the fundamental blockset of theofXSG,
blockset as shown
the XSG, in Figure
as shown 3. The sinusoidal
in Figure three phase
3. The sinusoidal threevoltage
phase
waveform as a modulating signal is compared with the triangular wave
voltage waveform as a modulating signal is compared with the triangular wave to generate the to generate the switching
pulses for apulses
switching three-phase
for a inverter
three-phasesystem. A free
inverter running
system. A up counter
free running block
upiscounter
used to block
generate a ramp
is used to
signal. If the counter count for the ramp signal is greater than the desired triangular
generate a ramp signal. If the counter count for the ramp signal is greater than the desired triangular wave frequency
the
wavecounter will be
frequency reset.
the Afterwards,
counter the counter
will be reset. output the
Afterwards, is compared to that of
counter output is the half of the
compared triangular
to that of the
wave
half offrequency.
the triangular Finally,
wave anfrequency.
up/down counter is used
Finally, an to perform
up/down counterthe is increment
used to performwhen the the increment
value is 1
and
when decrement
the valuewhen thedecrement
is 1 and value is zero.
when For the
the generation
value is zero. of the
For switching
the generation signal,
of the the carrier wave
switching signal,is
compared to that of incoming reference voltage signal and updated immediately.
the carrier wave is compared to that of incoming reference voltage signal and updated immediately. The Inverter used
for
Thethe experimental
Inverter used for validation has an inbuilt
the experimental inversion
validation has circuit withinversion
an inbuilt dead timecircuit
compensation
with dead fortime
the
PWM signal. Therefore, the switching signals are only generated for the upper
compensation for the PWM signal. Therefore, the switching signals are only generated for the upper half power devices of
the inverter.
half power devices of the inverter.

Figure 3. Switching
Figure 3. Switching pulse
pulse generation.
generation.

3. FPGA System Implementation

3. FPGA System Implementation
The feedback control implementation of the PMSM drive system requires sensing of the control
The feedback control implementation of the PMSM drive system requires sensing of the control
parameters: motor speed and current. Further, the sensed parameters are needed to feed to the control
parameters: motor speed and current. Further, the sensed parameters are needed to feed to the
environment. Analog to digital converter (ADC) is used to feed the sensed control parameters to the
control environment. Analog to digital converter (ADC) is used to feed the sensed control parameters
to the digital control environment. PMSM drive system in Figure 4 is designed and developed using
the digital control environment of FPGA. The encoder unit has the purpose to sense the rotor angular
Electronics 2020, 9, 1906 7 of 19

Electronics 2020, 9, x 7 of 19
Electronics 2020, 9, x 7 of 19
digital control environment. PMSM drive system in Figure 4 is designed and developed using the
speed
digitaland angular
control position byofgenerating
environment FPGA. The pulses withunit
encoder a resolution of 2048 counts
has the purpose to sensepertherevolution. The
rotor angular
speed
positionand angular
andangular position
speed detector by generating pulses with a resolution of 2048 counts per revolution. The
speed and position calculates the speed
by generating pulsesand
withrotor positions using
a resolution of 2048 the encoder
counts perpulses. The
revolution.
position
motor and speed
current sensed detector
through calculates
a currentthe speedand
sensor andfedrotor
to positions
the FPGA using the an
through encoder
ADC pulses.
as shown Thein
The position and
motor4.current
speed detector
sensed through
calculates
a current
the speed
sensor andthe
and the
rotor positions
fedPItocontroller
FPGAunit.
through
using the encoder
an ADC as along
pulses.
shownwithin
Figure
The motor These
currentcurrents
sensed are further
through apassed
currentthrough
sensor and fed to the FPGA The control
through an ADCunit
Figure
the ADC- 4. These
digital currents
to analog areconverter
further passed
(DAC) through theunit
interface PI controller
and PWM unit. The control
generation unit unit
is along within
as shown
programmed
Figure
the 4. These
ADC- digital currents
to analog areconverter
further passed
(DAC) through the
interface PI and
unit controller
PWM unit. The control
generation unit isunit along with
programmed
to
thethe FPGA
ADC- board.
digital to The DAC
analog interface
converter (DAC) unit is usedunit
interface to and
convert
PWM the controlled
generation unitparameters
is into an
programmed
to the signal,
analog FPGA board.and it The
is DAC interface
measured and unit is used
recorded to convert
through memorythe controlled
Hi-corder parameters
for monitoring anto
into and
the FPGA
analog board.
signal, Theit DAC
and interfaceand
is measured unitrecorded
is used tothrough
convert memory
the controlled parameters
Hi-corder into an analog
for monitoring and
validation.
signal, and it is measured and recorded through memory Hi-corder for monitoring and validation.
validation.

Figure 4. Field programmable

programmablegate
gatearray
array(FPGA) implementation of the PMSM drive system.
Figure 4. Field
Figure 4. Field programmable gate array (FPGA)implementation
(FPGA) implementationof
ofthe
thePMSM
PMSMdrive
drivesystem.
system.

3.1. ADC Interface

3.1.
3.1.ADC
ADCInterface
Interface
An interface program is developed for the operation of ADC to feedback the signal to FPGA.
An
Aninterface
interface program
program is
is developed
developed for
for the operation
thethe
operation of ADC
of ADC to to feedback
feedback the
the signal
signaltotoFPGA.
FPGA.
The schematic diagram in Figure 5 represents ADC interfacing and pin configuration of PMOD
The schematic
The schematic diagram
diagram in Figure
in Figure 5 represents the ADC interfacing and pin configuration of PMOD
(Peripheral Module) AD1. PMOD5 AD1 represents the ADCofinterfacing
is consisting and pin configuration
a 12-bit, two-channel AD7476A of ADC PMOD with
(Peripheral
(Peripheral Module)
Module) AD1.
AD1. PMOD
PMOD AD1
AD1 is
is consisting
consisting of
of a
a 12-bit,
12-bit, two-channel
two-channel AD7476A
AD7476A ADC
ADC with
with
maximum possible sampling rate up to 1MSPS [29]. PMOD AD1 has six input pins that is for two
maximum
maximumpossible sampling rate up toto 1MSPS
1MSPS [29]. PMOD AD1 AD1 has
has six input
input pins
pinsthat
thatisisfor
fortwotwo
analog inputpossible
signals sampling
(ia and ib )ratewithup their respective[29]. PMOD
ground pins and a six
power supply pin (VCC) with
analog input signals (i a and ib) with their respective ground pins and a power supply pin (VCC) with
analog input signals (ia and ib) with their respective ground pins and a power supply pin (VCC) with
its respective ground pin (GND). Similarly, the PMOD AD1 has six output pins that are connected to
its
itsrespective
respectiveground
groundpin pin(GND).
(GND). Similarly,
Similarly, the the PMOD
PMOD AD1 AD1 has
has six
six output
outputpins
pinsthat
thatare
areconnected
connectedtoto
the FPGA,
the FPGA, consisting
consisting of
of aaclock
clock pin
pin (Clk),
(Clk),chip
chipselect (CS)
select (CS)pin, two
pin, twodigital data
digital output
data pinspins
output (D1 (D and D2 )
and
the FPGA, consisting of a clock pin (Clk), chip select (CS) pin, two digital data output pins (D 1 1and
and a
DD2)2)andVCC with its respective GND.
andaaVCC
VCCwith
withits
itsrespective
respective GND.
GND.

Figure
Figure 5.
Figure5. PMOD(Peripheral
5.PMOD (PeripheralModule)
Module)AD1
Module) AD1with
AD1 withan
with ananalog
an analogto
analog todigital
to digitalconverter
digital converter(ADC)
converter (ADC)interface.
(ADC) interface.
interface.
Clk and CS signals are provided from FPGA using the ADC interface program block as shown in
Clkand
Clk andCS CSsignals
signals are
are provided
provided from
from FPGA
FPGA using
using the
the ADC
ADC interface
interface program
programblock
blockasasshown
shown
Figure 5. The conversion and anddatadata
acquisition process is governed by thebyCSthe
signal. The falling edge of
in Figure 5. The conversion and data acquisition process is governed by the CS signal. Thefalling
in Figure 5. The conversion acquisition process is governed CS signal. The falling
edgeofofthe
edge theCS CSinitializes
initializes the
the sampling
sampling ofof data
data as
as well
well as
as the
the data
data conversion.
conversion. The
Thedigitized
digitizeddata
dataDD1 1
andDD2 2are
and aresynchronized
synchronized at at the
the rate
rate of
of sampling
sampling frequency
frequency using
using the
the start
start signal
signal through
throughthetheADC
ADC
Electronics 2020, 9, 1906 8 of 19

Electronics 2020, 9, x 8 of 19
the CS initializes the sampling of data as well as the data conversion. The digitized data D1 and D2 are
synchronized
interface and atit the rate of sampling
generates frequency
the CS signal using the start
corresponding to signal through
the start signal thecondition.
ADC interface
Onceand
theit
generates the
acquisition CS signal
following thecorresponding to the
sampling as well as start signal condition.
conversion Once
of the analog theisacquisition
data completed,following the
it generates
sampling as well as conversion of the analog data is completed, it generates a done
a done signal as shown in Figure 5. The AD converter works at 1MSPS and following the requirement signal as shown in
Figure 5. The AD converter works at 1MSPS and following the requirement for the implementation
for the implementation of the control algorithm the sampling frequency is specified using the start of
the control algorithm the sampling frequency is specified using the start signal.
signal.

3.2. Timing
3.2. TimingDiagram
Diagram ofof Closed
Closed Loop
Loop
The sampled digitized data of the feedback control parameters are further used for the control
The sampled digitized data of the feedback control parameters are further used for the control
algorithm of
algorithm of motor
motordrive
drivesystem.
system.The control
The algorithm
control consists
algorithm of a speed
consists control
of a speed unit, current
control control
unit, current
unit and PWM generation unit. The control algorithm execution is required to be
control unit and PWM generation unit. The control algorithm execution is required to be completed completed within
a pre-specified
within sampling
a pre-specified time interval.
sampling The crucial
time interval. The factors
crucial are sampling
factors time as well
are sampling timeasasexecution
well as
execution of control algorithm in a synchronized way to generate the PWM switchingThe
of control algorithm in a synchronized way to generate the PWM switching signals. sampling
signals. The
sampling time at least should be half the carrier time (minimum sampling frequency should the
time at least should be half the carrier time (minimum sampling frequency should be double of be
carrier of
double frequency)
the carrierasfrequency)
represented in Figure 6a.in In
as represented addition,
Figure 6a. In the sampling
addition, frequencyfrequency
the sampling can be taken
can
higher;
be takenhowever, the impact
higher; however, theof lowerof
impact sampling time fortime
lower sampling the same
for thecarrier
same frequency may notmay
carrier frequency always
not
be advantageous.
always be advantageous.

(a)

(b)

Figure
Figure 6.
6. Control
Controlloop
looptiming
timingcriteria:
criteria:(a)
(a)sampling
samplingtime
timecriteria
criteriawith
withrespect
respectto
tocarrier
carrierfrequency
frequency(b)
(b)
execution
execution timing
timing diagram.
diagram.

The control
The control algorithm
algorithmisis required
requiredto to be
be executed
executedinin aa sequential
sequentialwayway asas the
the output
output ofof the
the outer
outer
control loop
control loop generates
generates the
the reference
reference quantity
quantity andand feeds
feeds to
to the
the inner
inner control
control loop.
loop. The
Theperformance
performanceof of
the system
the system is is dependent
dependent on on the
the controller
controller bandwidth.
bandwidth. The
Theinner
innercontrol
controlloop
loop has
has aa dominant
dominant impact
impact
on
on the
the outer
outer control
control loop;
loop; therefore,
therefore, the
the bandwidth
bandwidth of of the
the inner
inner control
control loop
loop should
should bebe higher
higher toto
accommodate
accommodate the the bandwidth
bandwidth of of the
the outer
outer control
control loop.
loop. Furthermore,
Furthermore, the the execution
execution timing
timing can
can be
be
crucial
crucial and and may
may have
have significant
significant impact
impact on on the
the system’s
system’s performance.
performance. The Theenabled
enabledsignals
signals(done,
(done,
sig.1–sig.
sig.1–sig. n) n)are
aregenerated
generated with
with on
on time
time TTenenfor
forthe
theexecution
executionof ofcontrol
controlalgorithm.
algorithm.AAbuffer
bufferdelay
delaytime
time
of
of TTddisisinserted
insertedfor
forthe
thesuccessive
successiveenabled
enabledsignals
signalsto
toavoid
avoidoverlapping.
overlapping.

3.3. Time Synchronization

A time synchronization for the execution of entire control algorithm is crucial for the system
performance. As the output of one unit is responsible for the next, a sequential time synchronization
is used to perform the computation of the control algorithm within a sampling time.
Electronics 2020, 9, 1906 9 of 19

3.3. Time Synchronization

A time synchronization for the execution of entire control algorithm is crucial for the system
performance. As the output of one unit is responsible for the next, a sequential time synchronization is
Electronics 2020, 9, x 9 of 19
used to perform the computation of the control algorithm within a sampling time.
The timing diagram
The timing diagram in inFigure
Figure6b 6bisisused
usedforforthethe implementation
implementation of of
thethe control
control algorithm
algorithm in
in the
the FPGA. The start signal width is defined by sampling time T with
FPGA. The start signal width is defined by sampling time Ts swith on time of 1µs following the on time of 1µs following the
throughput
throughputtime timeofofADC.
ADC.Consequently,
Consequently, thethedone
donesignal waswas
signal switched to a high
switched state state
to a high following the quite
following the
time of 400 ns after the start signal switched to the low state. Following the
quite time of 400 ns after the start signal switched to the low state. Following the done signal, done signal, the enabled
the
signals
enabledare generated
signals for the time-synchronized
are generated executionexecution
for the time-synchronized of the control
of thealgorithm.
control algorithm.
There
There are various possibilities to generate the enabled signals to perform time-synchronization
are various possibilities to generate the enabled signals to perform time-synchronization
corresponding
correspondingtotothe thesampling
sampling time.
time.InIn
this study,
this study,enabled
enabledsignals withwith
signals on time
on T en ofT0.5
time µs and a buffer
en of 0.5 µs and a
delay
buffertimedelay Td time
of 2.5 Tµs in between consecutive signals are considered for the time-synchronization
d of 2.5 µs in between consecutive signals are considered for the time-
analysis
synchronization analysis of the The
of the control algorithm. enabled
control signal (done)
algorithm. enablessignal
The enabled the speed
(done)controller
enablesloop theasspeed
well
as abc to dq conversion simultaneously to perform parallel computation
controller loop as well as abc to dq conversion simultaneously to perform parallel computation as as shown in the Figure 7.
Further,
shown in a methodological approach
the Figure 7. Further, a is considered by using
methodological the different
approach combination
is considered by using of enabled input
the different
signals for the computation of the current controller unit and dq to abc conversion.
combination of enabled input signals for the computation of the current controller unit and dq to There are three
abc
cases considered for the analysis of the effect of the time synchronization, as
conversion. There are three cases considered for the analysis of the effect of the time synchronization,shown in the Figure 8,
for the computation
as shown in the Figure of current controller
8, for the computation unit and dq to abc
of current conversion.
controller unit and dq to abc conversion.

Figure 7.
Figure 7. Time synchronizations for
Time synchronizations for the
the system
system implementation.
implementation.

Case I:I:
Case
In case I, the done signal enables the speed PI controller and abc–dq conversion. Further, the
In case I, the done signal enables the speed PI controller and abc–dq conversion. Further,
enable1 signal with Ten of 0.5 µs and Td of 2.5 µs from the done signal is used to enable the current PI
the enable1 signal with Ten of 0.5 µs and Td of 2.5 µs from the done signal is used to enable the current
control. Similarly, the enable 2 signal with Ten of 0.5 µs and Td of 5.5 µs from the enable1 signal is
PI control. Similarly, the enable 2 signal with Ten of 0.5 µs and Td of 5.5 µs from the enable1 signal is
considered to enable the dq–abc conversion. The timing diagram executing case I is represented in
considered to enable the dq–abc conversion. The timing diagram executing case I is represented in
Figure 8a.
Figure 8a.
Case II:
Case InII: this case, similar to case I, the done signal enables the speed PI controller and abc–dq
conversion, and the enable1 signal with Ten of 0.5 µs and Td of 5.5 µs from done signal is used to
In this case, similar to case I, the done signal enables the speed PI controller and abc–dq conversion,
enable the current PI controller. Further, the enable2 signal with Ten of 0.5 µs and Td of 5.5 µs from
and the enable1 signal with Ten of 0.5 µs and Td of 5.5 µs from done signal is used to enable the current
the enable1 signal enables the dq–abc transformations. The timing diagram for case II is shown in
PI controller. Further, the enable2 signal with Ten of 0.5 µs and Td of 5.5 µs from the enable1 signal
Figure 8b.
enables the dq–abc transformations. The timing diagram for case II is shown in Figure 8b.
Case III:
Case Similar
III: to case I and II the enable1 with Ten of 0.5 µs and Td of 8.5 µs is used as an enable signal
for the
Similar to controller
current case I and loop
II theand the enable2
enable1 with
with Ten Ten µs
of 0.5 of and
0.5 µs Tdand Td of
of 8.5 µs 5.5 µs enables
is used the dq signal
as an enable to abc
transformation.
for The timing
the current controller loopdiagram
and thecorresponding
enable2 with Tto case
of 0.5III
µsisand
shown
T ofin5.5
theµsFigure 8c.the dq to abc
enables
en d
transformation. The timing diagram corresponding to case III is shown in the Figure 8c.

(a)
 Electronics 2020, 9, 1906 10 of 19
Electronics 2020, 9, x 10 of 20

(a)

(b)

(c)

Figure
Figure8.8.(a)
(a)Case
CaseI,I,(b)
(b)Case
CaseII,
II,(c)
(c)Case
CaseIII.
III.

4.4.Experimental
ExperimentalResults
Resultsand
andDiscussion
Discussion
Anexperimental
An experimentalsystem systemisisdeveloped
developedas asshown
shownin inFigure
Figure99for forthe
theanalysis
analysisandandvalidation
validationof ofthe
the
time synchronization
time synchronizationforfor the the
FPGA-based
FPGA-based PMSMPMSM drive system.
drive The three cases
system. The of time synchronization
three cases of time
methodology as discussed in Section 3 are considered for feedback
synchronization methodology as discussed in Section 3 are considered for feedback control control loop analysis. Sampling
loop
frequencies
analysis. of 25, frequencies
Sampling 50 and 100ofkHz areand
25, 50 used
100forkHztheareextensive
used for the analysis of impacts
extensive analysisdue to time
of impacts
synchronization.
due The delay time
to time synchronization. The for casetime
delay II and
forcase
caseIII is more
II and casethanIII isofmore
10 µs;than
therefore, only
of 10 μs; case I is
therefore,
considered corresponding to the sampling frequency of 100 kHz. A step
only case I is considered corresponding to the sampling frequency of 100 kHz. A step change in speed change in speed reference
and motorand
reference load condition
motor load (load disturbance)
condition is introduced
(load disturbance) is to demonstrate
introduced the system performance
to demonstrate the system
under transient
performance conditions
under and examine
transient conditionsthe effect
and of time synchronization
examine the effect ofcorresponding to different
time synchronization
sampling frequencies. The system parameters and the component
corresponding to different sampling frequencies. The system parameters and the component specifications are explained in the
Tables 1 and 2.are
specifications The samplinginfrequency
explained the Tables of 1the
andspeed controller
2. The sampling is same as the of
frequency current controller.
the speed Kp and
controller is
K
same
i value for both the speed controller and the current controller are kept constant
as the current controller. Kp and Ki value for both the speed controller and the current controller for all the cases as
explained
are in the Table
kept constant 3. However,
for all the cases asconsidering
explainedthe in different
the Tablesampling
3. However, frequency, the sampling
considering time Ts
the different
is multiplied
sampling with thethe
frequency, Ki .sampling
The clocktime
frequency consideredwith
Ts is multiplied for the
the FPGA-based
Ki. The clocksystemfrequencyimplementation
considered
is 100
for the MHz.
FPGA-based system implementation is 100 MHz.

Table 1. System parameters.

Table 1. System parameters.
Parameters
Parameters Values
Values
Dc Voltage Vdc [V] Vdc [V]
Dc Voltage 80
80
MotorMotor rated [W]
rated power power [W] 400
400
Rated Rated
torque torque
Te [Nm]Te [Nm] 1.27
1.27
Stator Stator resistance
resistance Rs [Ω] Rs [Ω] 0.96
0.96
Stator inductance Ls [H] 4.3 × 10−3
Stator inductance Ls [H] 4.3 × 10−3
Permanent magnet flux φ [Wb] 0.047
Permanent magnet flux ϕ [Wb] 2 0.047
Rotor inertia J [Kg-m ] 5.3 × 10−5
Rotor inertia
Coefficient J [Kg-m
of viscous
2]
friction B [Nm/(rad/s)] 1 ××10
5.3 10−5−5
No of pole pairs [pp]
Coefficient of viscous friction B [Nm/(rad/s)] 1 ×410−5
No of pole pairs [pp ] 4
Table 2. Specifications of the system.

Components Specifications
Three phase VSI STEVAL-IHM023V3, 1 kW
DC voltage supply ST5360318
Three phase rectifier S15VT60-4000
Electronics 2020, 9, 1906 11 of 19

Table 2. Specifications of the system.

Components Specifications
Three phase VSI STEVAL-IHM023V3, 1 kW
DC voltage supply ST5360318
Three phase rectifier S15VT60-4000
Electronic load LSA-165
Back EMF load PR-18-5A
Current sensor ACS723
Isolator ADuM3440
ADC PMOD AD1
DAC PMOD DA4
FPGA board ARTY Z7-Xc7z020

Electronics 2020, 9, x 11 of 19
Table 3. Controller parameters.
Table 3. Controller parameters.
Controller Parameters Values
Controller
Kpω Parameters Values
0.45
Kiω Kpω 0.45
30
Kpd , Kpq
Kiω 30
5
Kpd, Kpq 5
Kid , Kiq 20
Kid, Kiq 20

Figure9.9. Experimental
Figure Experimental Setup.
Setup.

Theno
The noload
loadspeed
speedresponse
responsecorresponding
correspondingtoto the
the motor
motor startup
startup and
and stop
stop is shown
is shown in the
in the Figure
Figure 10.
10. The speed reference is changed from 0 to 300 rpm (start-up) and 300 to 0 rpm
The speed reference is changed from 0 to 300 rpm (start-up) and 300 to 0 rpm (stop). (stop).

1200
1000
800
(rpm)

600
400
200
0
 Figure 9. Experimental Setup.

The no load speed response corresponding to the motor startup and stop is shown in the Figure
10. The speed reference is changed from 0 to 300 rpm (start-up) and 300 to 0 rpm (stop).
Electronics 2020, 9, 1906 12 of 19

1200
1000
800

(rpm)
600
400
200
0
0 2 4 6 8
-200
Time(s)

Figure 10. Motor speed response.

Figure 10. Motor speed response.
4.1. Change in Reference Speed
4.1. Change in Reference
The motor system Speed
can go under the condition of speed change, and the transient performance
of the
Themotor
motordrivesystemsystem
can gois of concern
under to attain the
the condition new speed
of speed change, smoothly
and the with a lower
transient settling time.
performance of
A step change in the reference speed from 900 to 1500 rpm (low
the motor drive system is of concern to attain the new speed smoothly with a lower settlingto high speed) and 1500 to time.
900 rpm
A
(high
step to
change
Electronics
low speed)
2020,in9, the
is considered to demonstrate and analyze the performance
x reference speed from 900 to 1500 rpm (low to high speed) and 1500 to 90012rpm
for time synchronization
of 19
cases as
(high to well
lowasspeed)
sampling is frequencies.
considered The to switching
demonstrate frequency of 5 kHzthe
and analyze is used for the power
performance fordevices
time
of the inverter
The speedcorresponding
synchronization regulation
cases as well tosampling
of as
PMSM different sampling
in Figures 11–13
frequencies.time.
isThe
demonstrated for the sampling
switching frequency of 5 kHzfrequency
is used forof
25, 50The
and speed
100 regulation
kHz. The of PMSM
settling time in Figures
performance 11–13of
the power devices of the inverter corresponding to different sampling time. is demonstrated
speed regulation for
is the sampling
better for 25 frequency
and 50 kHz as of
25, 50 and 100 kHz. The settling time performance of speed regulation
compared to 100 kHz for the case I of time synchronization. Further, the speed regulation is better for 25 and 50 kHz as
compared to 100
performance has kHz for theincase
improved case I of
II time synchronization.
and case III for 50 kHz. Further, the speed
The settling timeregulation
performanceperformance
of speed
has improved in case II and case III for 50 kHz. The settling time
regulation is summarized in Table 4 in terms of time required to attain the steady state. performance of speed regulation is
summarized in Table 4 in terms of time required to attain the steady state.

2500 2500 _ref i_q

_ref i_q
ref , (rpm),iq(A)*1500
ref , (rpm),iq(A)*1500

2000 2000

1500 1500

1000 1000

500 500

0
0
0 2 4 6 8
0 2 4 6 8
Time(s)
Time(s)

(a) (b)
2500 _ref i_q
ref , (rpm),iq(A)*1500

2000

1500

1000

500

0
0 2 4 6 8
Time(s)
(c)

Figure
Figure 11.
11. Speed
Speed response of PMSM
response of PMSMat
at25
25kHz
kHzsampling
samplingfrequency
frequency(a)(a) case
case I, (b)
I, (b) case
case II and
II and (c) (c)
casecase
III.
III.

2500 _ref i_q

2500 _ref i_q
ref , (rpm),iq(A)*1500

2000
ref , (rpm),iq(A)*1500

2000

1500 1500

1000 1000

500 500

0 0
0 2 4 6 8 0 2 4 6 8
Time(s)
 0
0 2 4 6 8
Time(s)
(c)

Figure 11. Speed response of PMSM at 25 kHz sampling frequency (a) case I, (b) case II and (c) case
III.2020, 9, 1906
Electronics 13 of 19

2500 _ref i_q

2500 _ref i_q

ref , (rpm),iq(A)*1500
2000
ref , (rpm),iq(A)*1500

2000

1500 1500

1000 1000

500 500

0 0
0 2 4 6 8 0 2 4 6 8
Time(s)
Time(s)

(a) (b)
2500 _ref i_q
ref , (rpm),iq(A)*1500

2000

1500

1000

500

0
0 2 4 6 8
Time(s)
(c)

Figure
Electronics
Figure 12.9,
2020,
12. Speed
x
Speed responseofofPMSM
response PMSMatat5050kHz
kHzsampling
samplingfrequency
frequency(a)
(a)case
caseI,I,(b)
(b)case
caseIIIIand
and(c)
(c)case
case
13 of 19
III.
III.
2500 _ref i_q
ref , (rpm),iq(A)*1500

2000

1500

1000

500

0
0 2 4 6 8
Time(s)

Figure13.
Figure 13.Speed
Speed response
response of
of PMSM
PMSM at
at 100
100 kHz
kHzsampling
samplingfrequency
frequency(case
(caseI).I).

Table4.4.Speed
Table Speedresponse
response corresponding to the
corresponding to the change
changeof
ofreference
referencespeed.
speed.

Case
CaseII Case
CaseIIII Case IIIIII
Case
SamplingFrequency
Sampling Frequency (kHz)
(kHz)
Low-High High-Low Low-High High-Low Low-High High-Low
Low-High High-Low Low-High High-Low Low-High High-Low
25 1s 1.1 s 1.5 s 1.1 s 1.05 s 1.5 s
25
50 1 ss
1.25 1.1ss
0.7 11.5
s s 1.1s s
0.9 1.05
1.1 s s 0.81.5
s s
50
100 1.25s s
1.5 0.7ss
1.2 -1 s 0.9
- s -1.1 s -0.8 s
100 1.5 s 1.2 s - - - -

4.2. Change in Load Condition

4.2. Change in Load Condition
The motor system can go under the load disturbance condition as well, and the transient
The motor
performance of system
motor drivecan system
go under is ofthe load to
concern disturbance condition
attain the desired as well,
reference speed and the transient
smoothly with
performance of motor
a lower settling time. Adrive systeministhe
step change ofelectronic
concern load to attain the desired
to introduce a loadreference
disturbance speed smoothly
is employed
thataultimately
with results
lower settling in a motor
time. A stepcurrent
change change
in thefrom 0.5 to 1load
electronic A (low to high) and
to introduce 1 to 0.5
a load A (high to is
disturbance
low). Thethat
employed switching frequency
ultimately resultsofin5akHz motoris used to analyze
current changethe system
from 0.5 tobehavior.
1 A (lowThe speedand
to high) regulation
1 to 0.5 A
(high to low). The switching frequency of 5 kHz is used to analyze the system behavior. Theofspeed
of PMSM under load disturbance in Figures 14–16 is demonstrated for the sampling frequency 25,
50 and 100
regulation of kHz.
PMSM Theunder
settling time
load performance
disturbance of 100 kHz
in Figures 14–16sampling frequency is
is demonstrated forbest
the for time
sampling
synchronization in case I from low to high as well as high to low. Further,
frequency of 25, 50 and 100 kHz. The settling time performance of 100 kHz sampling frequency is the speed regulation
performance
best has improved in in
for time synchronization case II and
case caselow
I from III for
to 50 kHz
high ascompared
well as highto 25tokHz
low.and becomethe
Further, almost
speed
same as performance of 100 kHz in case I. The settling time performance
regulation performance has improved in case II and case III for 50 kHz compared to 25 kHz and become of speed under load
disturbance is summarized in Table 5 considering the time required to attain the steady state.

2500 _ref i_q 2500 _ref i_q

),iq(A)*1500

),iq(A)*1500

2000 2000

1500 1500
 25 1s 1.1 s 1.5 s 1.1 s 1.05 s 1.5 s
50 1.25 s 0.7 s 1s 0.9 s 1.1 s 0.8 s
100 1.5 s 1.2 s - - - -

4.2. Change in Load Condition

Electronics 2020, 9, 1906 14 of 19
The motor system can go under the load disturbance condition as well, and the transient
performance of motor drive system is of concern to attain the desired reference speed smoothly with
almost same
a lower as performance
settling of 100 kHz
time. A step change in theinelectronic
case I. The settling
load time performance
to introduce of speed
a load disturbance under load
is employed
that ultimately
disturbance results in a motor
is summarized current
in Table change from
5 considering 0.5 torequired
the time 1 A (lowtotoattain
high) the
andsteady
1 to 0.5state.
A (high to
low). The switching frequency of 5 kHz is used to analyze the system behavior. The speed regulation
of PMSM underTable 5. Speed response
load disturbance corresponding
in Figures to the change offor
14–16 is demonstrated load
thedisturbance.
sampling frequency of 25,
50 and 100 kHz. The settling time performance of 100 kHz sampling frequency is best for time
Case I Case II Case III
synchronization
Sampling Frequency in case
(kHz)I from low to high as well as high to low. Further, the speed regulation
performance has improved in Low-High High-Low
case II and case III for 50Low-High
kHz compared High-Low
to 25 kHzLow-High
and become High-Low
almost
same as performance of 100 kHz in case I. The settling time performance of speed under1.6load
25 1.5 s 1.3 s 1.3 s 1.1 s 2 s s
50 1.3 s 1.15 s 1.1 s 1 s
disturbance is summarized in Table 5 considering the time required to attain the steady state. 1 s 0.9 s
100 0.9 s 0.7 s - - - -

2500 _ref i_q 2500 _ref i_q

ref , (rpm),iq(A)*1500

ref , (rpm),iq(A)*1500
2000 2000

1500 1500

1000 1000

500 500

0 0
0 2 4 6 8 0 2 4 6 8
Time(s) Time(s)

(a) (b)
2500 _ref i_q
ref , (rpm),iq(A)*1500

2000

1500

1000

500

Electronics 2020, 9, x 0 14 of 19
0 2 4 6 8
Time(s)
Figure 14. Speed response of PMSM at 25 kHz sampling frequency (a) case I, (b) case II and (c) case
(c)
III.
Figure 14. Speed response of PMSM at 25 kHz sampling frequency (a) case I, (b) case II and (c) case III.

2500 _ref i_q 2500 _ref i_q

ref , (rpm),iq(A)*1500
ref , (rpm),iq(A)*1500

2000 2000

1500 1500

1000 1000

500 500

0 0
0 2 4 6 8 0 2 4 6 8
Time(s)
Time(s)

(a) (b)
2500 _ref i_q
ref , (rpm),iq(A)*1500

2000

1500

1000

500

0
0 2 4 6 8
Time(s)
(c)

Figure
Figure 15.15.Speed
Speedresponse
responseofofPMSM
PMSMatat5050kHz
kHzsampling
samplingfrequency
frequency(a)
(a)case
caseI, I,(b)
(b)case
caseIIIIand
and(c)(c)case
caseIII.
III.

2500 _ref i_q

(A)*1500

2000

1500
 0
0 2 4 6 8
Time(s)
(c)

Figure 15. Speed response of PMSM at 50 kHz sampling frequency (a) case I, (b) case II and (c) case
Electronics 2020, 9, 1906 15 of 19
III.

2500 _ref i_q

ref , (rpm),iq(A)*1500
2000

1500

1000

500

0
0 2 4 6 8
Time(s)

Figure
Figure 16.
16. Speed
Speed response
response of
of PMSM
PMSM at
at 100
100 kHz
kHz sampling
sampling frequency
frequency case
case I.
I.

4.3. Effect of Sampling

TableFrequency on Speedcorresponding
5. Speed response Control Loop to the change of load disturbance.
The mechanical response of theCase motorI is slower compared Case to
II that of the electrical Case response
III of
Sampling Frequency (kHz)
the motor. Therefore, the sampling Low-High rateHigh-Low
of the speed controllerHigh-Low
Low-High is slower than that of the
Low-High current
High-Low
controller.
Electronics 2020,The25x sampling rate of
9, 1.5the
s encoder 1.3 considered
s 1.3 for
s the experimental
1.1 s validation
2s is 1s kHz.
1.615 of 19
50 1.3 s 1.15 s 1.1 s
Considering the sampling rate of the encoder the minimum sampling frequency that can be consider 1 s 1 s 0.9 s
for the motor 100speed response
Theimplementation of the speed 0.9 s control 0.7
corresponding loops is
to the1 kHz.
speed - controller -sampling frequency - 1 kHz- for
The motor
the change in thespeed
speedresponse
referencecorresponding
from 900 to 1500 to the
rpm speed
(low controller
to high) and sampling
1500 tofrequency
900 (high to 1 kHzlow)foris
4.3.
shown Effect
the change of
in the Sampling
inFigure
the speed Frequency
reference
17. The on
motorfromSpeed
speed Control
900response Loop
to 1500 rpm (low to high)
corresponding and 1500
to change intothe900 (high
load to low) is
disturbance
shown
that Theinmechanical
results thein Figure
motor 17. The motor
current
response change
of the speed
from
motor response
0.5isto 1 Acorresponding
slower iscompared
shown in to tothat
Figure change
18. Ininorder
of the the load disturbance
to compare
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thatmotor.
effect
the results
of thein motor current
sampling
Therefore, change
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the sampling onfrom
the 0.5
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the
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speed
is slower In order
thantothat
response compare
with
of the the effect
sampling
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of the sampling
frequency
controller. 1The frequency
kHzsampling
is compared on the
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the encoder
kHz sampling the motor
considered forspeed
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the experimental withvalidation
sampling frequency
controller sampling
is 1 kHz.
1 kHz
frequencyis compared
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kHz sampling
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Considering the sampling rate of the encoder the minimum sampling frequency that can be consider controller sampling frequency is
considered
for as 50 kHz forofboth
the implementation the cases.
the speed control loop is 1 kHz.

2500 _ref i_q

2500 _ref i_q
ref , (rpm),iq(A)*1500

2000
ref , (rpm),iq(A)*1500

2000

1500 1500

1000 1000

500 500

0
0
0 2 4 6 8
0 2 4 6 8
Time(s)
Time(s)

(a) (b)
2500 _ref i_q
ref , (rpm),iq(A)*1500

2000

1500

1000

500

0
0 2 4 6 8
Time(s)
(c)

Figure
Figure 17.
17. Speed
Speedresponse
responseof
ofPMSM
PMSM(a)
(a)case
caseI,I,(b)
(b)case
case IIII and
and (c)
(c) case
case III.
III.

2500 ref
2500 _ref i_q
ref , (rpm),iq(A)*1500

2000
ref , (rpm),iq(A)*1500

2000

1500 1500

1000 1000

500 500

0 0
0 2 4 6 8
 r
0
0 2 4 6 8
Time(s)
(c)

Electronics 2020, 9, 1906Figure 17. Speed response of PMSM (a) case I, (b) case II and (c) case III. 16 of 19

2500 ref
2500 _ref i_q

ref , (rpm),iq(A)*1500
2000
ref , (rpm),iq(A)*1500

2000

1500 1500

1000 1000

500 500

0 0
0 2 4 6 8
0 2 4 6 8
Time(s)
Time(s)

(a) (b)
2500 _ref i_q
ref , (rpm),iq(A)*1500

2000

1500

1000

500

0
0 2 4 6 8
Time(s)
(c)

Figure 18. Speed response of PMSM (a) case I, (b) case II and (c) case III.

The settling time required for the speed response to reach the steady state value is summarized in
Table 6 for the change in the speed reference and in Table 7 for the change in the load torque disturbance
corresponding to both speed sampling frequencies of 1 and 50 kHz. The transient response for the
sampling frequency of 50 kHz is slightly better compared to the 1 kHz for both change in the speed
reference and change in the load torque disturbance. Moreover, case III has a better response for the
speed sampling frequencies of 1 and 50 kHz.

Table 6. Speed response corresponding to the change of speed reference.

Speed Controller Sampling Case I Case II Case III

Frequency (kHz) Low-High High-Low Low-High High-Low Low-High High-Low
1 1.1 s 0.8 s 1.2 s 1.2 s 1.2 s 0.9 s
50 1.25 s 0.7 s 1s 0.9 s 1.1 s 0.8 s

Table 7. Speed response corresponding to the change of load disturbance.

Speed Controller Sampling Case I Case II Case III

Frequency (kHz) Low-High High-Low Low-High High-Low Low-High High-Low
1 1.35 s 1.2 s 1.45 s 1.3 s 1.1 s 0.9 s
50 1.3 s 1.15 s 1.1 s 1s 1s 0.9 s

4.4. System Performance in Terms of THD

The controller performance (three-phase current harmonics) depends up on the switching
frequency at which the power devices are operating as well as on the sampling frequency at which
the digitized sampled data are coming. Therefore, different switching frequencies corresponding to
the different sampling frequencies are considered to examine and analyze the controller performance.
The sampling frequency for the system should be double or more than double the switching frequency
and is considered as the fundamental criteria. The combinations of the switching frequency and
Electronics 2020, 9, 1906 17 of 19

sampling frequency are exercised to investigate the system performance as shown in the Table 8
considering case I of the time synchronization.

Table 8. Comparison of total harmonic distortion (THD).

Switching Frequency (kHz) Sampling Frequency (kHz) %THD

10 20
25 7.5
5
50 4.5
100 3.57
25 10.2
10 50 3.7
100 2.25
50 2.6
25
100 1.52
50 100 2.5

The current ripples are presented in the form of percentage total harmonic distortion (%THD).
The lower switching frequency performance in terms of %THD has improved drastically corresponding
to an increase in sampling frequencies. Nevertheless, the higher switching frequency results in higher
switching losses of the power devices and high sampling frequency demands the high-speed ADC to
feedback the data samples at a higher rate. The advancement in digital technology with cost reduction
trend can be vital in this aspect.

5. Conclusions
The PMSM drive system is presented considering the time synchronization analysis for
FPGA-based real-time control implementation using a digital simulator XSG integrated with the
MATLAB/Simulink (Math Works, Natick, MA, USA). The time synchronization of system control
corresponding to sampling frequencies has a significant impact on motor performance under a transient
operation. The controller demonstrates better performance under the change of speed reference for
case II and Case III with a sampling frequency of 50 kHz. The controller performance under the change
of load disturbance is better for case I with a sampling frequency of 100 kHz; however, Case III with
sampling frequency of 50 kHz is comparable to it.
Furthermore, the effect of the sampling time on the speed controller and THD is also studied
and investigated. The performance of the speed controller is slightly better for higher sampling
frequency. Furthermore, the current ripple calculated in the form of %THD is lower corresponding to a
higher sampling frequency. As the sampling frequency increases, the difference between the errors for
consecutive samples reduces, and that ultimately reduces the current ripples. Therefore, a reduction in
current ripple is achievable for an even lower switching frequency with a higher sampling frequency
operation. The sampling frequency and the time synchronization both have an impact on motor
performance. An appropriate synchronization methodology and sampling time can achieve better
performance in terms of transient response under change in reference speed and motor load.

Author Contributions: The manuscript preparation including system design and experiments was performed
by I.M. The idea of analysis was suggested by R.N.T. R.N.T. has also contributed to the experiment, manuscript
writing and correction. The work was completed under the supervision of T.H. All authors have read and agreed
to the published version of the manuscript.
Funding: This research received no external funding.
Conflicts of Interest: The authors declare no conflict of interest.
Electronics 2020, 9, 1906 18 of 19

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