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LCD Dot Matrix Display Single Line
LCD Dot Matrix Display Single Line
Introduction
Hitachi produces a wide range of monochrome medium resolution dot matrix liquid crystal displays. A number
of these displays require the use of an external display controller. This application note will discuss some of the
design implications that should be considered when using a dot matrix graphics LCD panel.
General Characteristics
LCD panels are categorised as non-emissive displays, in that they do not produce any form of light. LCDs
manipulate light by either passing or blocking light that is either reflected from an external source or produced
by an integrated backlighting system.
Display Types
Hitachi manufactures a wide range of LCD panels with the following industry standard resolutions:
(Full data and specifications for these displays can be found in the Hitachi Liquid Crystal Graphic Display
module data book Reference 06-006C)
Typical Applications
Applications for LCD panels are many and varied: EPOS, Process Control, Instrumentation, Man Machine
Interfaces, Security systems, Hand-held devices, Factory automation, Office automation, Mobile
Communications, Handheld devices and many others.
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Figure 1. Schematic circuit diagram for the Hitachi SP10Q002 1/8 VGA LCD
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A line synchronisation pulse latches a line of display data into the column drivers (IC1, IC2, and IC3). Line
Pulse becomes active when a line of pixel data is clocked into the LCD panel and stays asserted for a duration
equal to the number of pixel clock periods.
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Figure 2. Interface timing for the Hitachi SP10Q002 1/8VGA LCD module.
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Typically, to control a Monochrome, Single Scan, Dot Matrix LCD with a 4-bit LCD data bus (where X =
number of rows, Y = number of columns) requires the following peripherals to be used:
Channel 0 can be configured to produce a CP pulse (Pixel Data Clock). This takes the form of a 50% duty
square wave.
Channel 1 can be configured to produce a Load signal (Line Pulse). This takes the form of a 1/(X/4) duty
square wave. This can be clocked by the output from channel 0 (where X = number of columns, 4 = LCD data
bus width)
Channel 2 can be configured to produce a Frame pulse (First Line Marker). This takes the form of a 1/Y duty
square wave. This can be clocked by the output of channel 1 (where Y = number of rows)
Channel 3 can be configured to produce the M signal.
The DMAC can be configured to transfer a byte of data from display memory to the timer pattern controller
next data register (TPC NDR) on each ITU Channel 0 compare match. The DMAC source display memory
address is then incremented after each data transfer. The destination for the display data is fixed hence the
destination address for the DMA transfer is remains the same. A CPU interrupt is generated after (X x Y)/4
transfers to reset the DMA source display memory address at the end of each frame of display data. (where X=
number of columns, Y = number of rows)
The timer pattern controller then transfers the display data byte to an 8-bit I/O port from the next data register
on each ITU Channel 0 compare match. The I/O port can be connected directly to the LCD data bus.
The LCD controller continuously transfers pixel data into the LCD panel via the LCD data bus. The LCD data
bus is timed by the Pixel Data Clock, Line Pulse and FLM signals. The pixel data clock clocks the pixel data
into the display drivers internal shift register. The line pulse latches the shifted pixel data into a wide latch at
the end of a line while FLM marks the first line of the displayed page. The line pulse signifies the end of the
current line of serial data. The line pulse enclosed by the FLM signal marks the end of the first line of the
current display frame.
Mid-range LCD controllers are designed to support most standard monochrome LCD panels. The end user can
configure the display image or text entirely to suit his chosen application. The user can control configuration of
character or language fonts, bitmaps, icons and graphics software routines.
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Many embedded 16/32-bit microcontrollers and processors have built in LCD controller peripherals enabling
simple and quick implementations with full software configuration.
Epson www.epson-electronics.de
OKI www.oki.co.jp
Yamaha www.yamaha.co.jp
C&T(Intel) www.chips.com
(Please note that this is by no means a comprehensive listing of LCD controller manufacturers. A further
application note is planned to discuss LCD Controllers in more detail).
Dithering
Dithering is achieved by alternately driving some pixels black and some white in a checkerboard type pattern.
When using this method, the pattern should be produced in a random order to create the perception of a gray
shade. If dithering is performed using a regular or repeating pattern it can be detected by the human eye.
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In gray scale mode, the number of data words required for displaying gray levels increases as opposed to
black/white mode. Also, the line buffer needs to be loaded before the next line is displayed. Therefore, the LCD
pixel clock, LCD frame refresh rate, line buffer fill and line to line interval are affected by gray scale
generation. Display timing characteristics should be checked to ensure that the display is capable of displaying
gray shades or levels.
7 6 5 4 3 2 1 0
0,0 1,0 2,0 3,0 4,0 5,0 6,0 7,0
8,0 9,0 10,0 11,0 12,0 13,0 14,0 15,0
… … … … … … … …
x-8,y-1 x-7,y-1 x-6,y-1 x-5,y-1 x-4,y-1 x-3,y-1 x-2,y-1 x-1,y-1
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Figure 6. Memory map for 2-bits per pixel (memory requirement increases x 2)
Figure 7. Memory map for 4-bits per pixel (memory requirement increases x 4)
7,6,5,4 3,2,1,0
0,0 1,0
2,0 3,0
4,0 5,0
6,0 7,0
8,0 9,0
10,0 11,0
12,0 13,0
14,0 15,0
… …
x-2,y-1 x-1,y-1
What is Shadowing?
Shadowing is caused by crosstalk which is best described as the effect when a dark image (box or window
shape) is placed in the middle of a white background. Faint vertical and horizontal lines will be seen from the
edge of the window proceeding to the edges of the screen. The off selected pixels are not completely off and
some charge, very strong at the edge of a window, has leaked into the adjacent pixels creating the effect. This
is a common problem and is due to the nature of the LCD technology employed.
With higher pixel density, the electrode size must be reduced and the amount of voltage necessary to drive the
display rapidly increases. Higher driving voltages create a secondary problem: charging effects. Even though
only one row and column are selected, the pulse affects the liquid crystal material near the row and column
being charged. The net result is the pixel selected is active (dark), but the areas surrounding the addressed
point are also partially active The partially active pixels reduce the display contrast and degrade image quality.
What is Ghosting?
Ghosting is an issue caused by the speed of the STN material; a display must be able to react in less than 50
milliseconds for performance similar to a CRT. Most monochrome STN materials are between 250 and 600
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milliseconds and can not switch from black to a white image that quickly. This problem results in disappearing
cursors and blurred images when high speed graphics are utilised.
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