ADDRESSING MODES

ADDRESSING MODES
• Various methods used to access instruction operands is
called as Addressing Mode

• General Instruction Format

OPCODE Operand  Operand

• Operands may be contained in

• Registers,
• Memory
• I/O ports.
• Three basic modes of addressing are
• Immediate
• Register
• Memory
 Example:
If CS=24F6h & IP=634Ah, show the;
1- The logical address
2- The offset address
3- The physical address
4- The lower range of the segment
Solution: 5- The upper range of the segment

1- The logical address is the CS: IP content which is: 24F6:634A

2- The offset address is the content of the IP register which is: 634A
3- The physical address:

3
• 8086 Addressing modes - classified according to
flow of instruction execution
A. Sequential flow instructions
• Arithmetic
• Logical
• Data transfer
• Processor control
B. Control transfer instructions
• INT
• CALL
• RET
• JUMP
A. Sequential flow instructions
1. Implied Addressing mode
2. Immediate addressing mode
3. Direct addressing mode
4. Register addressing mode
5. Register Indirect addressing mode
6. Indexed addressing mode
7. Register Relative addressing mode
8. Based Indexed addressing mode
9. Relative Based Indexed addressing mode
B. Control transfer instructions
1. Intersegment Direct addressing mode
2. Intersegment Indirect addressing mode
3. Intra segment Direct addressing mode
4. Intra segment Indirect addressing mode
1. Implied Addressing - The data value/data
address is implicitly associated with the
instruction.
• AAA
• AAS
• AAM
• AAD
• DAA
• DAS
• XLAT
Sequential Flow Instructions
2. Immediate Addressing – Data / operand is part
of the instruction Destination
Source

MOV AX, 25BF ; [ AX25BF H ] 16 Bit Data

MOV AL, 8EH ;
[ AL8E ] 8 Bit Data

3. Direct Addressing – Data is pointed by 16 bit

offset value specified in the instruction
MOV AX, [5000H] ;

Effective Addr = 5000

PhyAddr = 10H*DS + 5000H
4. Register Addressing – Data is in the register
specified in the instruction

MOV BX, AX No PhyAddr, since data is in regr

16 BIT Operand Registers - AX, BX, CX,DX, SI, DI, SP, BP

8 BIT Operand Registers - AL, AH, BL, BH, CL, CH, DL, DH
5. Register Indirect Addressing – Data is pointed by
the offset value in the register, specified in the
instruction

MOV AX, [BX] Default Segment - DS or ES

Offset – BX or SI or DI

DS BX
PhyAddr = 10H *
ES
+ SI
DI
If DS=5000H; BX=10FF;
Then EffectiveAddr = 10FF
and PhyAddr = 10H*5000H + 10FFH = 510FFH
6. Indexed Addressing
 Data is pointed by the offset in the index
register specified in the instruction
 DS is the default segment register for SI and
DI

MOV AX, [SI] Data is available in the logical

address [DS:SI]
Effective Addr = [SI]
SI
PhyAddr = 10H * DS + DI
7. Register Relative Addressing
 Data is pointed by the sum of 8 bit or 16 bit
displacement specified in the instruction plus
 Offset specified in the registers –BX, BP, SI,
DI
 Default segment registers – DS, ES
MOV AX, 50H [BX]

EffectiveAddr = 50H+[BX]
BX
DS BP
PhyAddr = 10H * ES + SI
DI
8. Based Indexed Addressing
 Data is pointed by content of base register
specified in the instruction plus
 Content of index register specified in the
instruction
 Default segment registers – DS, ES

MOV AX, [BX] [SI]

BX SI
EffectiveAddr = BP + DI

DS BX SI
PhyAddr = 10H * ES
+ BP
+ DI
9. Register Relative Addressing
 Data is pointed by the sum of 8 bit or 16 bit
displacement specified in the instruction plus
 Offset specified in the base registers –BX, BP
plus
 Offset specified in the index registers – SI, DI
 Default segment registers – DS, ES

8 bit BX SI
EffectiveAddr = 16 bit + BP + DI

DS 8 bit BX SI
PhyAddr = 10H * ES +
16 bit
+ BP + DI
Control Transfer Instructions
• Intrasegment Direct Addressing –
 Control transfer instruction and
 Address where control is transferred lies in the same
segment
 Immediate displacement value specified in instruction
 Displacement is w.r.t IP register content
 Short jump –
8 bit signed displacement ‘d’
i.e (-27 < d < +27-1) = (-128 < d < +127 )
= (-80H < d < +7FH )
 Long jump – 16 bit signed displacement ‘d’

 i.e (-215 < d < +215 ) = (-32768 < d < + 32768 )
 Example: JMP SHORT LABEL
LABEL lies within (-128 to +127 ) from the current IP
content
Intrasegment Direct Addressing –

 Short Jump or Code Segment

CS: 3000H
 Near Jump IP: 0000H
 The jump destination is
in the same code CS: 3000H JMP NEXT
IP: 0010H
segment
 To execute the jump, CS: 3000H
only the contents of NEXT: INC BX
IP: 0020H
Instruction Pointer (IP)
register needs to be
changed
• Intrasegment Indirect Addressing –
 Control transfer instruction and
 Address where control is transferred lies in the same
segment
 Displacement value specified indirectly – as content
of a register or a memory location in the instruction
 Used in unconditional instructions

 Example: JMP [BX]

EffectiveAddr = [BX]
PhyAddr = 10H*[CS]+[BX]
Intrasegment Indirect Addressing
Code Segment
6FFFF BX = 75ABH
CS = 6000H

Effective Addr = [BX]

675AB MOV AX, BX
PhyAddr = 10H*[CS]+[BX]

61000 JMP [BX] Displacement from current location:

675AB - 61000 = +65AB H= +2602710
60000
• Intersegment Direct Addressing –
 Control transfer instruction and
 Address where control is transferred lies in the
different segments
 Branching from one code segment to another code
segt
 CS and IP of destination address are specified in
instruction
 Example: JMP 5000H: 2000H
EffectiveAddr =2000H
PhysicalAddr 10H
= * 5000H + 2000H = 52000H
 Intersegment Direct Addressing
Code Segment A
 Long Jump or Far Jump CS: 3000H
IP: 0000H

 The jump destination is in CS: 3000H

IP: 0010H JMP NEXT
a different code segment

 To execute the jump, 8086 Code Segment B

has to change the contents CS: 6000H
of Code Segment (CS) IP: 0000H
register and IP register
CS: 6000H
NEXT: INC BX
IP: 0050H
• Intersegment Indirect Addressing –
 Control transfer instruction and
 Address where control is transferred lies in the
different segments
 Branching from one code segment to another code
segt
 CS and IP of destination address are specified
indirectly in the instruction
 Starting address of a memory block specified in
instn
(i.e) content of a memory block containing 4 bytes
IP(LSB), IP(MSB), CS(LSB), CS(MSB)
 Example: JMP [2000H]
EffectiveAddr = 2000H
PhysicalAddr = 10H * DS + 2000H
Intersegment Indirect Addressing
DS = 6000H
6FFFF 7FFFF

MSB LSB

74466 IP 44 66

CS 70 00
62003 70H
62002 00H
62001 44H
62000 66H

60100 JMP [2000H]

60000 70000