TABLE OF INDEX

SNO LAB OBJECTIVE DATE SIGNATURE

1 To verify truth table of Basic gates

2 To verify truth table of NAND and NOR

gates

3 To verify truth table of HALF ADDER and

HALF SUBTRACTOR

4 To verify truth table of FULL ADDER and

FULL SUBTRACTOR

6. To verify truth table of Encoder and

decoder via simulator

6 To verify truth table of Multiplexer(1:8

MUX) and De-multiplexer (8:1)via
simulator

7 To perform Shift register operation via

simulation

8 To perform Counter operation via

simulation
 LAB 1

Objective: To verify the truth table of BASIC GATES.

Apparatus required: Connecting wires, breadboard Kit, IC 7432 (OR gate), 7408 (AND Gate), 7404 (NOT
Gate)

Pin Diagram of Basic Gates

TRUTH TABLE of OR GATE TRUTH TABLE of AND GATE

A B A+B

0 0 0

0 1 1

1 0 1

1 1 1

A B A.B

0 0 0

0 1 0
 1 0 0

1 1 1

TRUTH TABLE of NOT GATE

A OUTPUT

0 1

1 0

RESULT: The truth table of Basic Gates is verified successfully

LAB 2 (Do as Lab 1 is done)

 LAB 3
Objective: To verify the truth table of HALF ADDER and SUBTRACTOR

Apparatus Required: Connecting wires, breadboard Kit, IC 7408 (AND gate), IC 7486 (XOR Gate)

Circuit Diagram of Half Adder

Truth table of Half Adder

A B SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0
 1 1 0 1

Circuit Diagram of Half Subtractor

Truth table of Half Subtractor

A B Difference Borrow

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0
Result: The truth table of Half adder and Half Subtractor is verified

LAB 4
Objective: To verify the truth table of FULL ADDER AND SUBTRACTOR

Apparatus Required: Connecting wires, breadboard Kit, IC 7408 (AND gate), IC 7486 (XOR Gate), IC
7432(OR GATE)

Circuit Diagram of Full Adder

Truth table of Full Adder

Circuit Diagram of Full Subtractor

Truth table of Full Subtractor

Result: The truth table of full adder and full Subtractor is verified
LAB 6

Objective: To verify the truth table of Encoder and Decoder

Required: //please write here the simulator name that you used in lab

Block Diagram of 8-to-3 line Binary ENCODER and 3-to-8 line DECODER

Circuit Diagram of 8-to-3 line Binary ENCODER

Truth table of 8-to-3 line Binary ENCODER

D0 D1 D2 D3 D4 D5 D6 D7 X Y Z

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1

Circuit Diagram of 3-to-8 line Binary DECODER

Result: Truth table of encoder and decoder is verified.