Soc Methodology Training

SoC Design Methodology: A Practical
Approach
SoC Design Methodology : A Practical Approach
Schedule for Tutorial
 09:00 - 10:30 : Session 1.

 10:30 - 11:00 : Morning break.
 11:00 - 12:30 : Session 2.
 12:30 - 13:30 : Lunch break.
 13:30 - 15:00 : Session 3.
 15:00 - 15:30 : Afternoon break.
 15:30 - 17:00 : Session 4.
 17:00 - 17:15 : Feedback forms.
2
Outline
 Session 1 (9:00 – 10:30)
 Introduction
 Design Methodologies
 Design Planning and RTL
 Session 2 (11:00 – 12:30)
 Functional Verification
 Design For Test (DFT)
 Synthesis
 Session 3 (13:30 – 15:00)
 Floorplanning and Timing Analysis
 Design Closure
 Manufacturing Tests
 Session 4 (15:30 – 17:00)
 Advanced Topics
3
 09:00 - 10:30 : Session 1.

 10:30 - 11:00 : Morning break.
 11:00 - 12:30 : Session 2.
 12:30 - 13:30 : Lunch break.
 13:30 - 15:00 : Session 3.
 15:30 - 17:00 : Session 4.
 17:00 - 17:15 : Feedback forms.
4
Session 1 (9:00 – 10:30)

 What is SoC?
 Why SoCs?
 Why SoC Methodology?
 Typical Design Methodologies
 Design Planning
 Design start
 Die size estimation
 IP deliverables
 Design prototyping and partitioning
 RTL
5
What is System on a Chip (SoC)?

Application Specific Chip with:
 Embedded hard/soft/firm
processor cores
 Embedded memories
GPP DSP  Multiple peripherals
Memory  Modules interconnected via
Peripherals “standard” busses
 User logic 500K+ gates
User logic Analog  Analog Modules (Phys,
ADC, DAC)
 Application S/W for the
processor core(s)
Design Reuse a MUST for SoC success
6
Why SoCs: Potential chip-level savings?

 A typical broadband application consists of following chips:
DSP, CPU, Data Converters, ASIC/FPGA (Peripherals and
Custom Logic), Ethernet PHY, and Memories.
Memory Ethernet Data
Memory Phy
CPU DSP ASIC Converters
$9 - $10 $1.5 $5 $5 $15 - $20 $2.5
Die area
Number of SoC reduction in
packages reduced
$16 - $24
integrated
from 5  1.
solution
Typical chip-level Savings of 30% - 45% using SoC!!!

7
Why SoCs: Potential board-level savings?

1998 Memory F Memory
P
Internet
Ethernet G
Switch CPU DSP
A
Area: ~32 sq. in.
Power: ~6 Watts
SLIC SLAC
Cost: ~$100
2003
Memory Area: ~8 sq. in. IMPROVEMENTS
Power: ~1.5 Watts
Internet Cost: <$25 Area: 4x
SOC
Power: 4x
SLIC
Cost: 4x
8
Why SoCs?
 Advanced technologies enabling more
integration on a chip  Reduced Product
Cost.
 Physical size of products shrinking 
Minimize number of parts on a board.
 Consumer electronics requiring low cost
products  More integration.
 Minimize number of silicon vendors for a
product  Reduced Business Cost.
 Improved Reliability.
9
Typical Methodologies
 Waterfall Model*
 Spiral Model*
 Construct by Correction*
 HW/SW Co-design
* Source: “Reuse Methodology Manual For System-On-a-Chip

Designs,” Michael Keating and Pierre Bricaud, Kluwer Academic
Publishers.
10
Waterfall Model
Specification
 Based on traditional ASIC flow RTL Development

 Serial design flow, design transition
Functional Verification
phases in a step function.
 Assumes all steps are Perfect and Synthesis
NO need to revisit a completed
Timing Analysis (wireload model)
design phase.
 Specification is Golden, NO changes Scan Insertion & ATPG
permitted without having a major
impact on design schedule. Place & Route
 Expects clean handoffs from one Timing Analysis (with SDF)
team to the next.
 Works well for ~1M gate designs. Gate-level Sims (with SDF)
 Not suitable for large complex Deep Mfg. & Test
SubMicron (DSM) designs.
Deliver to software and systems teams.
11
Spiral Development Model

RTL & Verification Software
 Architecture  Application Prototype
 Block Partitioning  Prototype testing
 RTL Coding  Application development
 Module & Chip-level  Application testing
verification
 DFT Planning
Physical Design
Synthesis & Timing
 Library selection
 Constraints and
 Package selection exceptions definition
 Floorplan  Block-level Synthesis
 Clock expansion  Top-level Synthesis
 Placement  Scan Insertion / ATPG
 Routing  Static Timing Analysis
 Signal Integrity
 IR Drop Analysis
12
Spiral Development Model (contd…)

System Design, HW/SW Partitioning and Verification
Physical Synthesis RTL &
Software
Design & Timing Verification
Physical Timing HW and SW
Spec Spec Verification Spec Spec
Block App.
Preliminary Block Timing
Selection/ Prototype T
Floorplan Spec
Design & Ver Development I
Updated Block Top-level
App. M
Prototype
Floorplans Synthesis HDL E
testing
Top-level App.
Trial Top-level
verification Development
Placement Synthesis
Trial Scan Insertion HW/SW Co- App. testing

Placement & ATPG verification
Final Place and Route

Tapeout
AJ/AS/JR Jan. 6, 2005 VLSI Design 2005 13

Spiral Development Model (contd…)

 Concurrent development  Multiple aspects of
design worked on together.
 Parallel design flow, hardware and software
developed concurrently.
 Planned iterations to pipe clean the flow with
early version of netlist and learn from these
iterations.
 Manage spec changes without having major
impact on schedule.
 Works for large complex Deep SubMicron (DSM)
designs.
14
Construct by Correction
 Used for development of UltraSPARC.
 Single team took design from Architectural definition
through Place and Route.
 Engineers had to learn required tools.
 Team understood impact of architectural decisions on
Area, Power, and Performance of final design.
 Planned multiple passes from architecture to layout to
learn more about design.
 Multiple iterations allowed the team to learn from their
mistakes and correct them in next iteration.
 UltraSPARC development project was one of the most
successful in Sun Microsystems history.
15
HW/SW Co-Design
HW-SW System- Executable

Requirements & Specifications
Spec
Design Constraints System Architecture Design
HW/SW Partitioning & tradeoffs
cosimulatio level
K
HW Requirements
SIMULATION / VERIFICATION
SW Requirements
IP Repository
C
n
HW Architecture HW SW SW Architecture
Custom Reusable Processor/ Application Reusable Custom
Logic modules modules SW
Functional /
DSP cores
A
Behavioral
specific
Memories
RTL Coding Subsystem Peripherals
module
in C / Subsystem C/Assembly
Functional simulation Integration Controllers Assembly Integration Coding
B
Bridges Drivers
Chip-level Integration SW Integration
RTL / ISS HW-
cosimulation
Synthesis
SW
D
FVEC (RTL-Gates) Compile code for
Subsystem-level
DFT STA (Wire load) target processor
Chip-level
ATPG Floorplanning Verification
E
HW-SW cosimulation
Gate-level / Spice /
Place & GRoute
FVEC (Gates-Gates)
Tech Libraries Profiling and
E
SDF Generation / STA Simulation Optimization

Synthesis
CTS & DRoute Formal Verification

F
FVEC (Gates-Gates) DFT

SDF Generation / STA Physical Design
Tester
Regression
Regression PG
HW/SW Integration & Test
PRODUCT

Needs for Robust SoC Methodology

 Time-to-Market extremely important for business.
 Easy integration of Intellectual Properties (IPs) from
multiple sources.
 Resource management
 Minimize number of resources required to complete a design.
 Efficiently manage resources across projects.
 Share domain expertise across multi-site design teams.
 Make effective use of design automation.
 Advancement in technology  Handle Increased
Complexity of Integration.
 Maximize Performance.
 Manage Feature Creep and Engineering Changes
quickly.
17
Summary
 SoC design enables potential cost reduction and early
Time-to-Market (TTM) goals.
 Design reuse and automation essential ingredients.
 Different methodologies followed in the industry:
 Waterfall Model
 Spiral Design Model
 Construction By Correction
 HW/SW Co-Design
 Robust Design Methodology needed for success of
SoCs.
18
Design Planning
 What is ...
 Define chip implementation characteristics.
 Early Physical Prototyping
 Design Partitioning
 When …
 Initial steps prior to start of design implementation.
19
Design Start
 Design Specification
 Library selection
 Target technology node
 Frequency and Power limits
 Layout density entitlement
 IP Selection
 Hard vs. Soft
 Internal vs. external
 Embedded RAMs/ROMs
 PLLs & Analog blocks
 Custom Cells (if needed)
 Chip-level Power estimation
20
Design Start (contd…)

 Selection of verification environment
 Selection of configuration management environment
 IO Selection
 System/SoC performance
 Package
 System hook-up conditions
 Pin-multiplexing needs
 Operating conditions
 ESD protection expectations
 Test requirements
21
Design Start (contd...)

 Package Selection
 Number of SoC I/Os
 Build Cost
 Power dissipation demands
 Die size
 Electrical/Thermal demands
 Number of power levels
 Presence of high-speed I/O interfaces
 Mechanical reliability
 Die size estimation tradeoffs
 Preliminary floorplan
 IO limited vs. Core limited vs. Megamodule limited vs.
Package limited
22
Design Start (contd…)

I/O MEGAMODULE
core
uP
LIMITED LIMITED gates
gates
BALANCED
ram rom ram
ram
gates
ram
ram
gates
gates
ram
ram
CORE
PACKAGE
LIMITED
LIMITED
23
Principles of Die size Estimation

 Estimate IO Periphery Area:
 Comprehend IO form-factor
 Include Die corner IO cells
 Include IO feed-through and transition cells
 Estimate Core Area:
 Include hard macro (memory + custom cells)
 Comprehend hard macro overheads
• Power routing hook-up, physical keep-outs
 Logic gate area = # of logic gates / logic density
• Logic density is “Gates per mm2” for the technology
24
Quality and Reliability

 Testability
 ATPG coverage
 Memory testing
 PLL testing hooks
 Analog Module testing
 Boundary Scan/Jtag
 Functional at-speed test
 ESD/Latch-up testing
 Planning Design Reviews
25
Design Management
 Configuration management
 Paramount for Multi-site development
 Design and Scope changes
 Feature Creep
 Process Requirement Changes
 Test and Reliability Requirement Changes.
 External deliverables, e.g., IPs, custom cell.
 Handoffs and milestones
 Design Milestones, e.g., RTL freeze, Initial synthesis, tapeout.
 Design team (or customer) handoffs.
 Optimize engineering and compute resources.
26
Hard IP
 Need to support the following models:
 Functional  Floorplanning
 Timing  Physical Design
 Synthesis  Software tools for
 DFT processor core
 Scan hookup requirements
 Clock insertion delay numbers and skew
requirements
 Power requirements
 Integration/Test documentation
27
Soft IP
 Synthesizable RTL
 Functional Verification
 Coverage metrics
 models to speed-up verification
 Synthesis / Timing Analysis
 Timing exceptions and constraints
 Clock and Reset requirements
 Critical paths should be documented
 DFT scripts
 Physical design
 Memory placement guidelines
 Special clock handling requirements
 Software tools for processor cores
 Implementation and integration documentation
28
Design Prototyping & Partitioning
 Hardware vs. Software tradeoffs

 Prototyping – “Early” assessment of design
planning decisions
 Partitioning designs into subchips or
hierarchical modules
 Flat vs. Physical hierarchy decisions
 Partitioning is needed to
 Meet Area, Timing, and Power budgets.
 Minimize top-level logic and routes.
29
SoC Prototyping – All about tradeoffs

Increased Run-times
Planning Implementation
 Early & Incomplete

Data  Complete Data
 Quick Iterations Commit  Costly Iterations
 “Coarse” Partitions  “Detailed”
Optimizations
Optimizations
Increased Accuracy
30
Design Prototyping & Partitioning
 Activities
 “Coarse” logic placement
• Define SoC Peripherals pin-multiplexing
• Identify logical hierarchy candidates that can be “merged”
for physical implementation
 Macro placement
 Physical hierarchy or subchip planning
• Size, Shape, Location, Metal choices, Feed-through
 Power grid planning
 Subchip Pin assignment and optimization
 Preliminary Timing and Routability assessment
31
Physical Hierarchy Planning

Good Candidates Poor Candidates
 “Re-usable” modules  SoC “Bridges”
 Aggressive speed or  High pin count density
timing closure goals  Weirdly rectilinear due
 “Late-changing” to floorplan constraints
modules  Constrain/Obstruct
 External customer IP routing channel
 Special requirements, resource
such as alternate power
supply
32
Design Prototyping: Examples

RAM RAM RAMRAM RAM RAM RAMRAM
L2
SubChip3 SubChip3
L1
RAM RAM RAM RAM
RAM RAM
RAM RAM
ROM ROM
RAM RAM
CORE RAM CORE RAM
RAM RAM
Physical Partition Bad Pin Assignment

Candidates on Partitions
33
Design Partitioning: Example
RAM RAM RAMRAM
SubChip4 SubChip3
0.8M logic gates
1.1M logic gates
RAM RAM5M gates of
logic + RAM
1.6M logic gates processor Core
RAM
SubChip2
0.5M logic gates
ROM + Memories
RAM
0.4M logic gates CORE RAM
@ 250 MHz SubChip1 0.6M logic gates
RAM
@ 125 MHz
“Divide and Conquer” approach for partitioning the design into

several smaller blocks.
34
Summary
 Design Planning is the most critical phase of
SoC design methodology.
 Encompasses
 Technology selection
 IP (hard vs. soft) selection
 IO selection
 Package selection
 Design Prototyping and Partitioning
 Functional and Timing Verification planning
 Testability planning
35
RTL Design
 What is …
 RTL design is to create behavioral implementation
using hardware description languages (HDL).
 When …
 Design requirements and specification complete.
Verilog HDL
module my_mod
(a,b,clk,rst,y);
input a,b,clk,rst;
output y;
always @(posedge clk)
begin
if (rst) y <= #1 1’b0;
else y <= #1 a & b;
end
36
What is RTL?
Verilog HDL
 Register Transfer Logic module my_mod (a,b,clk,rst,y);
input a,b,clk,rst;
(RTL) output y;
 Method of describing begin
if (rst) y <= #1 1’b0;
hardware behavior in else y <= #1 a & b;
end
software using Hardware
Description Languages (HDL) VHDL
Entity my_mod is (
 Higher abstraction level a : in std_logic;
b : in std_logic;
than gate-level schematics clk : in std_logic;
rst : in std_logic;
y : out std_logic
 Faster simulation );
 Used to develop IP and architecture RTL of my_mod is

begin
capture digital designs. process
begin
wait until clk’event and clk = ‘1’;
 Verified using RTL if (rst = ‘1’) then y <= ‘0’ after 1 ;
else y <= a and b after 1 ;
simulators. end if;
end process;
end RTL;
37
RTL for SoCs?

 SoC is a structural HDL; Typically, integration
of re-usable Soft and Hard IPs.
 Functionality of IPs verified at module-level.
 New IP or chip specific RTL may be required
depending on application.
 Chip-level RTL needs to comprehend:
 All functional and test modes of operations.
 Partitioning strategy.
 Glue logic.
38
 09:00 - 10:30 : Session 1.

 10:30 - 11:00 : Morning break.
 11:00 - 12:30 : Session 2.
 12:30 - 13:30 : Lunch break.
 13:30 - 15:00 : Session 3.
 15:30 - 17:00 : Session 4.
 17:00 - 17:15 : Feedback forms.
39
Session 2 (11:00 – 12:30)

 Functional Verification
 What is Functional Verification?
 Types of Test
 Abstraction models and metrics
 Types of Verification
 Design For Test (DFT)
 Why DFT?
 Scan Fundamentals
 Multiple clock design
 Scan insertion guidelines
 Memory BIST
 Synthesis
 What is Synthesis?
 Terminology, Constraints, and Exceptions
 Top-Down vs. Bottom-up synthesis
40
 What is …
 Functional Verification of implemented HDL
against specification.
 When …
 Design RTL is ready.
Verilog HDL
module my_mod
(a,b,clk,rst,y);
input a,b,clk,rst;
output y;
begin
if (rst) y <= #1 1’b0;
else y <= #1 a & b;
end
41
What is Functional Verification?

 Verify functionality of chip to ensure all internal
logic has been implemented correctly and meets
the specification.
 Verify chip functionality in context of system and
software.
42
Functional Verification: SoC

 Each IP block MUST be fully verified before
integration. Module level verification needs to
be exhaustive and robust.
 Chip-level verification typically checks
 Chip-level hookup is correct, e.g., there is no bus
swapping.
 Processor can access the registers inside the IPs.
 Memory map is not overlapping between different
IPs.
 Simultaneous access of multiple IPs does not
impact the functionality of individual IPs.
 System does not lock under any condition.
43
Types of Verification Tests

 Focused Tests
 Compliance testing verifies that the design complies
with the functional specification.
 Corner case testing targets complex scenarios that
are possible on an SoC and may break the design.
Example: Simultaneously enable multiple masters in
a design.
 Verification of all functional and test modes.
 Realistic scenario testing
 Create a test that represents real application code.
 For processor based design, boot sequence is very
important.
44
Types of Verification Tests (contd…)

 Constraint-driven and Pseudo-random testing
 Verification engineer can use testbench automation
tools to restrict inputs to certain range of values.
 Stress more and creates test scenarios that are hard
to anticipate by verification engineer.
 Regression testing
 Once tests are developed and validated  Added to
Regression test suite.
 This test suite run whenever any changes are done in
RTL.
 Same test suite used at different levels of
abstractions (RTL, Gate-level, Post Silicon).
45
Abstraction Models
 Transaction Level Model (TLM)
 Temporal Ordering (C, C++, SystemC, Vera, etc.)
 Instruction Set Simulator (ISS) accurate
 Functional and cycle count accurate (C, C++, SystemC, etc.)
 Bus Functional Model (BFMs)
 Bus Cycle Accurate (C, C++, SystemC, Behavioral HDL)
 Internally Cycle Accurate
 Maintain internal states that change on clock edge.
 Functional and cycle count accurate (C, C++, SystemC,
Behavioral HDL)
 Register Transfer Logic (RTL)
 Gate-level
46
Verification Metrics
 Code Coverage
 Statement coverage ensures all executable statements have
been executed at least once. It gives count of how many
times each executable statement has been executed.
 Branch coverage verifies that each and every branch in
conditional statements (if-then-else and case) is executed.
 For conditional statements, Conditional coverage checks all
sub conditions have been triggered.
 For each signal in sensitivity list, Trigger coverage provides
count of number of times the process was activated by that
signal.
 Toggle coverage provides count of 0  1 and 1  0
transitions.
 FSM coverage provides statistics of sequence of states.
47
Verification Metrics (contd…)
 Functional Coverage
 Refers to how well the functionality of a device has
been tested.
 At module-level, the functional coverage ideally
should be 100%.
 Statistics of how many times a feature in the design
has been exercised during verification.
 The monitored features need to be defined.
48
Functional Verification: An Example

c c c
h h h
e e e
c c c
k k k
1 2 3
V V Proc Peripheral V V
e Externale Bus Bus IP Module
IP e External e
r I/O r Proc
Cycles Bridge Cycles r I/O r
Module
i Gen i Model
Gen Gen i Gen i
f. f. Cvg Cvg f. f.
Cvg
Behavioral / Full Functional / RTL / Gate-level Model
Code / Functional Coverage hooks

Interface Checking Properties
Bus Cycle Generation Model
High-level Verification Code
49
Verification Metrics
 Bug rate convergence
 Provides information about maturity of verification
suite.
Module C Verification
90
80
Closed
70
Fixed
60
New
Number
50
Rejected
40
30 All
20 Open
10 Resolved
0
2
28 02
29 02
26 02
02
25 02
02
5/ 002
6/ 002
7/ 002
2
23 02
20 02
02
2/ 200
00
4/ 00
00
00
0
0
0
0
20
20
20
20
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/
1/
9/
6/
4/
14
14
18
15
12
11
28
8/
2/
3/
7/
8/
9/
3/
4/
5/
6/
8/
9/
Date
50
Verification Test Plan

 Comprehensive functional verification
essential at both module-level and chip-level.
 Needs to be reviewed with SoC design,
software, and system design teams at the
beginning of the project.
 Create a table of all the tests that are agreed
upon by entire design team.
 Finding missing tests early on minimize
surprises later in the design cycle.
 May divide these tests based on priority.
51
Verification Test Plan (contd…)
 Minimize number of required tests without

compromising functional coverage.
 Should include
 Test strategy at both subsystem and chip-level.
 Block diagram of verification environment.
 Include details of all models used for the external
interfaces.
 Required coverage metrics for SoC.
 Specification of module level features to be verified
at chip-level.
52
SoC Verification: Example

Expected
GOLDEN MODEL Value
FIFO
DSP Block2
Transactor
Micro Controller
Subsystem
InOut1
Subsystem
In1
Block4
Block1
Control
Memory
Out2
FIFO
Block6 Block5
SoC
 RTL Blocks verified at module-level

 Verify Dataflow
 Verify Control
53
SoC Verification: Example (contd…)
Interfac
Interfac
e BFM
e BFM
DSP
DSPSubsystem
Subsystem
(Cycle Accurate Model)
FIF
DSP
O
Block2
Transactor
Micro Controller
Subsystem
InOut
Subsystem
In1
Block4
Block1
1
Control
Memory
Out2
FIFO
Block6 Block5
SoC
 How to Speed up simulation time?

 Replace modules with Internally Cycle
Accurate models.
 Replace modules with interface BFMs.
54
SoC Verification: Example

0 Mode Select
CPU Subsystem
Peripheral1
Peripheral1 0 0 Transactor
CPU
Bridge
Peripheral2 1 1 Peripheral2
sys bus
ROM Transactor
RAM Peripheral3
cpu bus
Clock / Peripheral3 Transactor

Reset
EMIF
SoC
Clock Reset
Memory
Model
55
Hardware Software Co-verification

H/W and S/W designs are done in isolation
Software Development Hardware Verification
Debugger CPU Subsystem Peripherals
cpu bus
CPU
sys bus
Clock /
Appl Code/ Prog. Proc ROM Reset
RAM
Dev. Driver ISS
EMIF IF
Bridge
Memory
Instruction Set Simulator (ISS) has Logic Simulation performance does

a very limited view of H/W not allow execution of big software
(> %85 execution in memory cycles)
56
Hardware Software Co-verification

Software View Co-verification Tool Hardware View
Hardware Simulator
Control Panel CPU Subsystem Peripherals
Debugger
A Configuration Manager A CPU
cpu bus
sys bus
BFM
Clock /
Reset
ISS
P CoSim Manager P ROM
RAM EMIF
Memory I Memory Manager I Bridge
Device Driver
Memory
Application Code Model
• ISS-Memory abstraction  Adaptability to existing design environment • BFM interfaces to H/W

• Debugging capability
 Synchronize the S/W and H/W processes • H/W Simulators
 Memory mapping
 Controllability/Observability across partitions
 Distributed network processing
 Optimize memory transactions via back door
 Speed-up Verification run time.
57
System Emulation
 Enables designs to be verified at 10x -100x faster than
RTL simulators. Typically, a scaled down frequency
version of chip Frequency is used for verification.
 Functional verification only.
 Allows capability of testing real system test case at much
faster compared to RTL/Gate-level simulations.
 Enables EARLY software development.
 Quickturn (QT)
 Designs need to be compiled and mapped to Quickturn
hardware.
 Expensive solution and Limited availability of QT box.
 FPGA based emulation
 Need to partition the design and map embedded memories to
FPGA memories for implementation.
 Limited debug visibility.
58
Gate-Level Simulations
 Rarely used to exhaustively test SoC.
 Much slower than RTL simulations.
 A subset of regression suite can be used for this.
 Two types:
 Unit Delay Timing
• Can be done as soon as first synthesis netlist is available.
• Useful to verify chip-level initialization and there are no un-
initialized flops.
 Full Timing
• Much slower than unit delay.
• Useful to validate asynchronous logic.
59
Summary
 Functional verification is a challenge and

needs too many resources.
 Selection of different tests and a good
functional verification plan is essential for
success.
 Clearly define coverage metrics to track
progress and status.
 Use different abstraction models to speed-up
simulation time.
60
Design For Test (DFT)
 What is …
 Structured techniques for manufacturing test.
 When …
 Design Planning and Design Implementation
Verilog HDL
module clk_mod (funcclk,testclk,
test_mode,clk);
input funcclk, testclk, test_mode;
output clk;
always @(test_mode)
begin
if (test_mode) clk = testclk;
else clk = funcclk;
end
61
Why DFT?
 IC manufacturing process is inherently defective,

but must still provide high quality ICs.
 Silicon must meet Performance specs.
 Enables reduction in number of test patterns.
 Faster generation of working test patterns
(automated).
 Faster ramp-to-volume production.
62
Functional vs. Structural

 Fault simulation took
100
90
ATPG Patterns
10 days for a 10%
80 fault sample on an
Fault Coverage
70
60 Functional Patterns UltraSPARC.
50
40
 ATPG took 5 mins
30
20 on 100% fault
10 sample on the same
0
0 50000 100000 150000 200000 machine.
Tester Cycle Number
 Relying on Functional patterns for complex SoCs.

 Long test times  High Cost.
 Typically, there is NO real need for functional
patterns.
63
How to Test?
 Automatic Test Equipment (ATE) used to catch
manufacturing defects.
 Use structured Design For Test (DFT) techniques.
 Improves Overall Device Quality.
 Reduces ATE test time  Lower Cost.
 Use automated tools for pattern generation
 Scan stuck-at for open/shorts in interconnect defect coverage
 Scan IDDQ for IDDQ defect, reliability
 Delay fault.
 I/O stuck-at for DC parametrics test
 Memory BIST
 Special cells such as PLLs handled separately.
64
Testability: Definition
. Fault
Input Cone
. of A A Y Output .
.. Input Cone
Cone of Z .
B .
. of B
.
Combinational Circuit
 All internal nodes of interest can be set to logic 0 or 1

(controllability), and any change in the desired logic
value at a node of interest, due to a fault, can be
observed externally (observability).
65
Fault Detection Example

 Two phases:
 Excitation
• Two Possibilities: A=X;B=0; C=1 OR A=0; B=X; C=1.
 Propagation to Output
• A=0; B=1; C=1 will detect s-a-0 fault.
s-a-0
?
0 A 0X 1/0
1
0
?
1
B X
0
1
1 0
Y
?
1 C 0
Z 1
0 1 Good
Good/Faulty
1
66
Foundation of Scan Design
Huffman Model
Primary ... ... Primary

Inputs Outputs
Combinational Storage
Circuit Elements
Scan Chain
67
Scan Design: An Example

COMBINATIONAL LOGIC
X
1
X
0 X
Z
0
X
1
0 X
0 X
1 X
1
SCAN_IN
D D D D
X
1
0 SD Q X
1
0 SD Q X
0
1 SD Q X
1
0 SD Q X
0
1
SCAN SCAN SCAN SCAN
SCAN_OUT
CLK CLK CLK CLK
0
X
CLK
X
0
1
SCAN_EN
CLK
SCAN_EN
PARALLEL SERIAL SHIFT

SERIAL SHIFT SERIAL SHIFT
CAPTURE
68
Multiple Scan Chains

Scan In 1 12721500
FFs FFs Scan Out 1
Scan In 2 1272 FFs
1800 FFs Scan Out 2
Scan In 3 9001272
FFs FFs Scan Out 3
Scan In 4 12711550
FFs FFs Scan Out 4
Scan In 5 1271
1300FFs
FFs Scan Out 5
Scan In 6 1250
1271 FFs
FFs Scan Out 6
Scan In 7 600 FFs1271 FFs Scan Out 7
Scan Enable
 Total of 8900 flops

 Use one Scan Enable for all chain
 Simultaneously, load and unload to reduce test time
 Test time determined by worst chain length (Chain 2 with 1800 flops)
 Balance scan chains reduces test time by ~30%  Cost savings.
 When shipping Millions of units this cost saving can be substantial.
69
Scan Design : Multiple Clocks
D D D SO1 D D SO2
SI1 SD Q SD Q SD Q SI2 SD Q SD Q
SE SE SE SE SE
CLK CLK CLK CLK CLK
CLKA CLKB
Scan
 Scan chain consists of flops from same clock domain.

 Number of flops in each clock domain may not be
same.
 Necessary to merge different clock domains flops in
one scan chain.
70
Scan Design : Multiple Clocks (contd…)

FF1 FF2 FF3 FF4 FF5
D D D D D SO1
SI1 SD Q SD Q SD Q SD Q SD Q
SE SE SE SE SE
CLK CLK CLK CLK CLK
CLKA CLKB
Scan
Skew
CLKA
CLKB
 Skew between CLKA and CLKB important.

 When Skew is greater than CLK  Q for FF3 plus required setup time
of FF4.
 Value stored in FF3 and FF4 is always the same after a shift cycle.
 ATPG tools do not comprehend clock skews  Failing patterns.
71
Scan Design : Multiple Clocks (contd…)

FF1 FF2 FF3 FF4 FF5
D D D D D SO1
SI1 SD Q SD Q SD Q SD Q SD Q
SE SE SE SE SE
CLK CLK CLK CLK CLK

Scan
CLKA CLKB
0 0
TestClk
1 1
Test Mode Test Mode
 Use TestClk for all the flops in Test mode.

 Use lock-up latch.
FF1 FF2 FF3 FF4 FF5
D D D D D SO1
SI1 SD Q SD Q SD Q D Q SD Q SD Q
SE SE SE Latch SE SE
EN CLK CLK
CLK CLK CLK
CLKA CLKB
Scan
72
SoC Scan Architecture: Example

 Combine multiple scan chains of
RAM RAM hard or harden macro into one
Subchip 3 chain.
Subchip 2  Hard macro scan chains can be
brought directly to periphery or
RAM RAM
merged with scan chains with top-
level scan chains.
RAM RAM
 All the ports of hard macro may
not be controllable.
Hard Macro  Hard macro could be completely
Subchip 1
bounded, like boundary scan.

 For bounded scan chains module
level patterns can be re-used at
chip-level for the macro.
73
DFT for Logic

 Scan is predominant DFT technique for logic.
 Scan is essential to obtain high fault coverage
using ATPG.
 Stuck-at fault model typically used
 High stuck-at fault coverage required for achieving
low DPPM
 Scan can be used for delay faults as well.
 Scan is also used for Iddq tests.
 Scan overhead is typically ~5-10% for total
gate area.
74
Scan Insertion Guidelines

 Successful scan insertion and ATPG require DFT
guidelines to be followed at the RTL stage.
 Synthesize RTL using scan flops to comprehend
performance impact.
 Checking for DFT rules can be performed at the RTL
level. Some of the examples are:
 No internally generated clocks can be used in scan mode.
 No internally generated asynchronous SETs/RESETs.
 No combinational loops.
 Synthesis tools perform gate-level checks to
determine if scan rules are met.
75
Scan Insertion and ATPG

 Scan is inserted in gate-level netlist.
 Identify areas of potential coverage loss. Add
controllability and observability points to
improve coverage.
 Scan chain re-ordering is performed at layout
time, if necessary.
 ATPG then performed on scan-inserted netlist.
76
DFT and Test Planning
 Understand DFT and Test requirements early

on in the design cycle.
 DPPM requirements.
 DFT architectures to suit target tester.
 Number of scan chains, length of scan chains, etc.
 Test Vector Memory.
 Max. frequency of operation.
 Identification of special cells, such as PLLs,
and their test strategy.
77
Verification of Manufacturing Test Patterns

 Static Timing Analysis with post-layout SDF to
determine correctness of timing in scan shift
and capture mode.
 Simulation-based verification at selected
corners.
 Tester constraints checks.
78
Memory Test
 Current SoC designs contain several
embedded memories.
 Direct tester access to all memory signals
impossible.
 Built-in Self-Test (BIST)
 using special BIST logic inserted by vendor tools.
 using existing CPU to test memories.
79
Memory BIST Architecture

BIST Collar
BIST Controller
RAM
D D
ADDR ADDR
CNTL Q
CNTL
CLK
MBIST_MODE
80
Summary
 Planning for DFT in the initial stages of the
design essential.
 Structured test is a must  Enables diagnosis.
 LogicBist - a future solution to reduce test time
and eliminate use of ATE.
81
Synthesis
 What is …
 Convert design RTL description to gates in a Target
Cell Library.
 When …
 RTL available.
Verilog HDL
test_mode,clk);
output clk;
always @(test_mode)
begin
else clk = funcclk;
end
82
Design Synthesis
Design Constraints
and Exceptions
RTL
module my_mod (a,b,clk,rst,y);
input a,b,clk,rst; Synthesis
output y;
always @(posedge clk) Tool
begin
if (rst) y <= #1 1’b0;
else y <= #1 a & b;
end
gate-level netlist
Cell Library +
ands xors memories
bufs constraints
flip-flops
invs subchips
83
Timing Path & Synthesis

COMBINATIONAL LOGIC
A
Y A Y A
G1 G2 A
B Y Y
D Q G3
B B G1
Flop
CLK1 A
QZ Y
B G4
Flop1 D Q
clk
Flop
CLK2
QZ
Flop2
 Path delay = Cell delays + Interconnect delays.
 Cell delay is delay from input  output of a logic gate.
 Depends on input transition time and output load on a gate.
 Also called as Gate or Propagation delay.
 Interconnect delay is delay from output of the driving cell to the
input of the load cell.
 Caused by parasitic capacitance and net resistance.
 Also called as Net delay.
 Synthesis tools optimize combinational logic to minimize Path
delay to keep it less than a period of a clock.
84
Synthesis Terminology
tc
 Clock period
tu Flop1 Clk
 tc (ns)
tb
 Duty cycle ta
t1
 ta/tc (%) / tb/tc (%)
t2 - t1 Flop2 Clk
 Important when both
clock edges are used.
 Clock uncertainty t2
 tu (ps)
Q
Models clock jitter
D

TDxxx Cloud2
CLK1
 Affects timing budget
clkin A
B Flop1
QZ
D Q
CTS3
 Clock skew CTS1

Cloud1 CTS2
C
CLK2
TDxxx
QZ
 t2 – t1 (ps) CTS4 Flop2
 Affects timing budget

85
Synthesis Terminology (contd...)

 Clock Tree
 Network of clock buffers to distribute clocks to all
sequential end points.
 Could also be used for high fanout nets, such as
RESET, TEST_SE.
 Clock Tree Synthesis (CTS)
 Flow for clock tree creation and balancing (intra
and inter clocks).
 The inserted buffers minimize skew across the
chip.
86
CTS: Example
D Q
D Q
D Q
D Q Flop
Flop
Flop QZ
Flop QZ
QZ
QZ
D Q
D Q
D QFlop
Flop D Q D Q
Flop QZ D Q D Q
QZ D QFlop D QFlop
CLK1 QZ D QFlop
Flop QZ
Flop QZ
D QFlop
Flop QZ
Flop QZ
QZ QZ
QZ QZ
Clock Buffer
CLK2
D Q
D Q
D QFlop
D QFlop
Flop QZ
D Q Flop QZ
D Q QZ
D Q
Flop
D Q QZ
Flop
D QFlop
QZ
Flop QZ
Flop QZ
QZ
QZ
87
Synthesis Terminology (contd...)

 Wire Load Models (WLM)
 Tables used to estimate net capacitance,
resistance, and area values using net fanout as a
parameter.
 Used by synthesis tool for interconnect and cell
delay calculations.
Capacitance Resistance
Fanout Length (um) Area (um2)
per um per um
1 0.002 0.005 0.004 0.006
2 0.003 0.009 0.007 0.01
...
...
...
...
...
10 0.02 0.03 0.024 1.4
88
Constraints and Exceptions: Example

input slew
output delay
input delay false path
IN OUT
Q D Q COMBINATIONAL D Q D
External LOGIC External
Flop Flop Sequential
Sequential
CLK CLK
element QZ QZ output element
CLK Flop1 Flop2

load
CLK
D Q
multicycle path= 3
CLK_A Flop
QZ
Slow
Combo
Flop3 Q
Logic D
Flop
Enable CLK1
D Q QZ
Flop Flop5
QZ
Flop4
89
Top-Down vs. Bottom-up Synthesis

 Top-down synthesis
 Constraints and clocks defined at the top-level.
 Synthesis tool can see entire design.
 Run time and memory penalty.
 Bottom-up synthesis
 Constraints and clocks defined at leaf module-level.
 Synthesis tool can see only module being targeted.
 Need to define time budgets to comprehend combinational
paths spread between multiple modules.  Challenge.
 Combination of Top-down and Bottom-up synthesis.
 Group modules into subsystems.
 Define time budgets and constraints for each subsystem.
 Synthesize each subsystem top-down.
90
Logic Synthesis Shortcomings
 Net delay portion in Path delay significantly

higher than gate propagation delay for Deep
Sub Micron (DSM) designs.
 WLMs provide delay information based on
block size and statistical models.
 Use of wireload models causes inaccuracies
in delay estimation.
 Can lead to many iterations through the timing
closure loop.
91
Summary
 Synthesis is a step to translate a design from
high-level description (HDL) to gate-level
netlist.
 Essential to specify all constraints and
exceptions correctly.
 For large SoCs, need to use right WLMs.
 Use proper synthesis methodology to
minimize run time and memory usage.
 Comprehend clock jitter and interconnect
parasitics.
92
 09:00 - 10:30 : Session 1.

 10:30 - 11:00 : Morning break.
 11:00 - 12:30 : Session 2.
 12:30 - 13:30 : Lunch break.
 13:30 - 15:00 : Session 3.
 15:30 - 17:00 : Session 4.
 17:00 - 17:15 : Feedback forms.
93
Session 3 (13:30 – 15:00)

 Floorplanning
 Place and Route
 Parasitic extraction
 Physical synthesis
 Timing analysis
 Design Closure
 Challenges for DSM designs
 Manufacturing tests
94
Floorplan and Timing Analysis
 What is …
 Floorplan is physical view of a chip.
 Timing analysis checks timing specification of the
chip.
 When …
 Synthesized gate-level netlist is available.
Verilog HDL
test_mode,clk);
output clk;
always @(test_mode)
begin
else clk = funcclk;
end

Floorplanning
Generate a physical description of a chip.
RAM gate-level
RAM netlist  Define Core Dimensions
RAM RAM
RAM design
RAMconstraints
SubChip2  Place IOs
RAM RAM
RAM RAM  Place Macros/Modules
ROM  Add Power Core Ring
Design database
DSP  Add Power Contours
SubChip1
 Add Power Straps

Floorplan: Examples
RAM
SubChip2 SubChip2
RAM
RAM
RAM SubChip3
BAD
RAM
RAM
RAM
RAM
RAM
BAD SubChip7
SubChip5
Floorplan Floorplan
SubChip4
R0M
DSP SubChip1 SubChip1 SubChip6
RAM
RAM RAM
SubChip2
SubChip2
RAM RAM
RAM RAM
SubChip3 SubChip4
RAM RAM SubChip6
RAM RAM
SubChip5
ROM
SubChip1
DSP SubChip1 SubChip7

Place and GRoute
RAM RAM
 Place core cells
RAM RAM
SubChip2
RAM RAM  Global Route Nets
RAM RAM
RAM RAM  Relieve Congestion

ROM
 Generate Pre-layout
DSP
Standard Delay
SubChip1 Format (SDF) for
timing analysis.

Parasitic Extraction
 Estimate Resistance and Capacitance values
for each net segment.
R1 R2 YY R3
A Y AA
C1 C2 C3 C4
 Extraction accuracy and computation

requirements vary with abstraction model used
for interconnects.

Extraction Accuracy
Run Time Increase
+100%
Detail Route Global Route
Field Solver
RC Error (%)
10%
3-D Extraction TLU WLM

0
-10%
-100%
1 10 50 100
Delay (ps)
Accuracy Increase

Physical Synthesis
 Extension of existing synthesis techniques to enable
simultaneous optimization of HDL, timing, and
physical placement of the synthesized logic.
 Timing based on global routes instead of using WLMs.
 Reduces iterations between synthesis and backend
flow.
 Leads to faster timing closure.
 Physical synthesis flow can be:
 Gates  Placed Gates
 RTL  Placed Gates
 Gates  GDSII
 RTL  GDSII

Timing Analysis: Dynamic vs. Static

 Dynamic
 Gate-level simulation with annotated SDF.
 Regress functional test cases to ensure all pass.
 Only paths targeted by input stimulus are checked.
 Timing analysis as good as testcase. Critical paths
may be missed, if input stimulus does not exercise
all relevant paths.
 Thorough analysis requires too many testcases.
 Difficult to control margins.
 Not practical for complex SoCs.

Timing Analysis: Dynamic vs. Static

 Static
 Analyze all timing paths in all modes (Functional
and Test).
 Not used to do functional verification.
 Essential to use correct constraints and exceptions.
 Best suited for fully synchronous designs.
 Uses Static Timing Analysis (STA) tools.
 Popularly used in complex SoCs.

Timing Analysis: STA

 Apply design constraints and exceptions. These are
reused from synthesis step.
 Device and interconnect parameters can vary with:
 Process, Temperature, and Voltage (PTV).
 Parasitic corners.
 Typical STA is done with SDF corresponding to a PTV
operating condition and parasitic corners:
 Max Delay: Worst process, high temperature, and low voltage.
 Min Delay: Best process, low temperature, and high voltage.
 Annotate SDF on gate-level netlist OR use smallest
WLM, if SDF not available.

Timing Analysis: Setup & Hold time

DATA
setup
CLK hold
setup/hold window
 Minimum time required for data to be stable before a

clock edge  Setup requirement.
 Minimum time required for data to be stable after a
clock edge  Hold requirement.
 Data must not transition between setup/hold window
for proper operation of a sequential element.
 Setup and hold requirements could be negative.

Timing Analysis: Setup Check

COMBINATIONAL LOGIC
Max Data Path

A (Ddatamax)
Y A Y A
G1 G2 A
Launch Clock Path B Y Y
D Q G3
B B G5
(CLKlaunch) Required
Flop
CLK1 A Setup Time
QZ Y
B G4
CLK Flop1 D Q
Flop
CLK2
QZ
Capture Clock Path Flop2

(CLKcapture)
CLKlaunch + Ddatamax – CLKcapture + Setup ≤ Clock Period

Setup Analysis: An Example

3.4 / 3.3
0.1 / 0.2 A
A
Y Y A A
B G1 G2 Y Y
D Q G3
B B G5
2.0 Flop
CLK1 A
QZ Y
B G4
0.8 Flop1 D Q
CLK
Flop
setup =
CLK2 0.2
QZ
Flop2
0.9 0.9
CLKlaunch = 0.8 + 2.0 = 2.8ns

Ddatamax = 0.2 + 3.4 = 3.6ns
CLKcapture = 0.8 + 0.9 + 0.9 = 2.6ns
CLKlaunch + Ddatamax – CLKcapture + Setup ≤ Clock Period
2.8ns + 3.6ns – 2.6ns + 0.2ns = 4.0ns

Timing Analysis: Hold Check

COMBINATIONAL LOGIC
Min Data Path

A (Ddatamin)
Y A Y A
G1 G2 A
Launch Clock Path B Y Y
D Q G3
B B G5
(CLKlaunch) Required
Flop
CLK1 A Hold Time
QZ Y
B G4
CLK Flop1 D Q
Flop
CLK2
QZ
Capture Clock Path Flop2

(CLKcapture)
CLKlaunch + Ddatamin – CLKcapture – Hold ≥ 0

Hold Analysis: An Example
0.05 / 0.1 A
A
Y Y A A
B G1 G2 Y Y
D Q G3
B B G5
1.0 Flop
CLK1 A
QZ Y
B G4 0.5 / 0.6
0.3 Flop1 D Q
CLK
Flop
hold =
CLK2 0.3
QZ
Flop2
0.6 0.6
CLKlaunch = 0.30 + 1.0 = 1.30ns

Ddatamin = 0.05 + 0.5 = 0.55ns
CLKcapture = 0.30 + 0.6 + 0.6 = 1.50ns
CLKlaunch + Ddatamin – CLKcapture - hold ≥ 0
1.30ns + 0.55ns – 1.50ns - 0.30ns = 0.05ns

Timing Analysis Management

 For complex SoCs to use resources effectively:
 Minimize number of functional and test modes.
 Minimize number of PTV combinations used for timing analysis.
 Make use of timing models for hard macros to speed up timing
analysis.
 For chip-level analysis, use hierarchical analysis, replace all
subchips by interface timing models.
 For designs with lot of violations  Too much analysis
time to review all the reports.
 Design Automation can help in parsing timing reports
and summarizing results.

Summary
 Floorplan is physical view of a chip.
 Essential to have a good floorplan to minimize
die size and meet timing.
 Cell placement and global route can flag
congestion that may require floorplan changes.
 Timing analysis based on GRoute SDF (placed
cells and global route) much more accurate
compared to WLM based.
 Fix only coarse violations using pre-layout SDF.

Design Closure
 What is ...
 Timing closure and Signal Integrity/Reliability
checks.
 When …
 After floorplanning with scan inserted netlist.
Verilog HDL
module clk_mod
(funcclk,testclk,
test_mode,clk);
input funcclk, testclk,
test_mode;
output clk;
always @(test_mode)
begin
if (test_mode) clk =
testclk;
else clk = funcclk;
end

What is Design Closure?
 Consists of the following:

 Timing & Routability closure
 Signal Integrity checks
 Reliability checks

What is Timing & Routability Closure?

Place & DRoute  Expand all Clocks and do
detailed route.
Parasitic Extraction  Generate Standard Parasitic
Exchange Format (SPEF).
Delay Calculator  For all PTV corners
generate SDFs.
 Complete timing analysis in
STA all modes of operations.
 Parse reports for timing
Analyze Reports failures.
 Identify fixes for setup/hold
Fix Setup/Hold time violations.
Violations
Place and DRoute

 Place core cells
RAM RAM
 Expand Clocks and all
RAM RAM
RAM RAM
SubChip2 high fanout nets.
RAM RAM
 Pre-route special nets.
RAM RAM
ROM  Detail route nets
DSP
 Relieve routing
SubChip1 congestion
 Fix design rule
violations.

Parasitic Extraction Accuracy

Run Time Increase
+100%
Detail Route Global Route
RC Error (%)
Filed Solver
10%
3-D Extraction TLU WLM 0
-10%
-100%
1 10 50 100
Delay (ps)
Accuracy Increase
For accuracy, essential to correlate timing calculator with

actual silicon data.
Setup Violation Fix

D Q N1 G2 D Q
G1
Flop Flop
CLK1 CLK2
QZ QZ
CLK Flop1 Flop2
 CLK1  D (Flop2) is too slow.

 Analysis shows large cell delays for gates (G1 and G2) and net
(N1).
 Options to fix setup time:
 Upsize gate G1.
 Move gate G2 closer to G1.
 Add intentional Skew to capture clock (CLK2) w.r.t. launch clock
(CLK1).
 Buffer net (N1).
 Reduce load on net (N1) by duplicating gate G1.

Hold Violation Fix

N2
D Q N1 G2 D Q
G1
Flop Flop
CLK1 CLK2
QZ QZ
CLK Flop1 Flop2
 CLK1  D (Flop2) is too fast.

 Analysis shows clock skew between CLK1 and CLK2
results in hold failure via net N2.
 Options to fix hold time:
 Minimize Clock skew (CLK2 – CLK1).
 Delay CLK1  D (Flop2) path.
• Place a delay buffer between G2 output and D (Flop2).
• Add a buffer on net N2.

Design Closure Challenges for DSM

designs
 On-chip Variations
 Crosstalk

Why On-Chip Variation (OCV)?
 Reduced feature size and increased

integration  More intra die variations for
both devices and interconnects.
 DSM manufacturing process irregularities need
to be comprehended for timing analysis.
 Temperature across die can also vary because
of different switching frequencies.
 Voltage drop (Static + Dynamic) can be
significant from periphery to center of the die.

Typical Power Grid Model

VDD
Bond Wire On Chip Power Grid
VDD
VDD
V1
V2
VDD V3
VDD
VDD
VDD
VDD

Voltage Drop Across Die

On Chip Power Grid
Bond Wire
V1 V2 V3 V4 V5
VDD
i(t)
 Assuming inductors are shorted and capacitors are

open, power grid can be modeled as resistors only
network.  Voltage drop = I x R (Static)
 Comprehending inductor, Voltage drop
v(t) = i(t) x R + L x di(t) / dt
Static Dynamic
This drop depends on the frequency of operation.
Voltage Drop Across Die (contd…)

On Chip Power Grid
Bond Wire
V1 V2 V3 V4 V5
VDD
i(t) DA
D1 D2 D3
Cell1
Cell2 Cell1 Cell3
Cell3 Cell1
Cell2 Cell1
D4 D6
D5
DB
V2 V3 V4 V5
 Typically, VDD > V1 > V2 > V3 > V4 > V5.

 Cells (Cell1, Cell2, Cell3) instantiated multiple times.
 Different core voltage seen for each cell instance 
Different cell delay even for similar cell loading.
 Typically, D4 > D1, D5 > D2, and D6 > D3.
 Thus, DA (= D1 + D2 + D3) < DB (= D4 + D5 + D6).
OCV Analysis
 Cannot assume constant PTV across die  Essential
to comprehend impact of these variations in timing
analysis.
 STA tools support OCV analysis mode
 Compute min and max delays for cells and nets by multiplying
annotated delay with min and max timing de-rate value,
respectively.
 Apply min and max delays to different paths simultaneously.
 For setup check, annotate worst case SDF. Use max delay for
launch path and min delay for capture path.
 For hold check, annotate best case SDF. Use min delay for
launch path and max delay for capture path.

OCV Setup Analysis: Example

3.23 / 3.4 / 3.74
A
0.19 / 0.2 / 0.22 Y A Y A A
B G1 G2 Y Y
D Q G3
B B G5
1.9 / 0.2 / 2.2 Flop
CLK1 A
QZ Y
0.76 / 0.8 / 0.88 B G4
CLK Flop1 D Q
Flop
setup =
CLK2 0.2ns
QZ
Flop2
0.85 / 0.9 / 0.99 0.85 / 0.9 / 0.99
Max Derate = 1.10 Min Derate = 0.95
CLKlaunch = 0.88 + 2.20 = 3.08ns

Ddatamax = 0.22 + 3.74 = 3.96ns
CLKcapture = 0.76 + 0.85 + 0.85 = 2.46ns
3.08ns + 3.96ns – 2.46ns + 0.20ns = 4.78ns

OCV Hold Analysis: Example
A
0.045 / 0.05 / 0.055 Y A Y A A
B G1 G2 Y Y
D Q G3
B B G5
0.9 / 1.0 / 1.1 Flop
CLK1 A
QZ Y
0.27 / 0.3 / 0.33 B G4
CLK Flop1 0.45 / 0.5 / 0.55 D Q
Flop
hold =
CLK2 0.3ns
QZ
Flop2
0.54 / 0.6 / 0.66 0.54 / 0.6 / 0.66
Max Derate = 1.10 Min Derate = 0.90
CLKlaunch = 0.270 + 0.90 = 1.17ns

Ddatamin = 0.045 + 0.45 = 0.495ns
CLKcapture = 0.330 + 0.66 + 0.66 = 1.65ns
1.17ns + 0.495ns – 1.65ns - 0.3ns = -0.285ns

Why Crosstalk?
 Wire aspect ratio changes for DSM
technologies.
Cc Cc
Cs Cs
≥ 0.5 μm ≤ 0.13 μm
 Coupling capacitance has gone up with shrink

in feature size.
Crosstalk Effect
 Crosstalk affect the circuit in two ways:

functionality and timing.
Suffering from noise
 Glitch propagation Victim
problem. Contributing
Aggressor noise
 Glitches on Clocks
can be a real problem.
Victim
 Delay Variation can be
an issue. Aggressor

Crosstalk Delay Variation: Example

Aggressor
Victim
Victim
Victim
without
with noise
noise
 Aggressor/Victim net
Vdd
Opposite switching in same direction
direction leads to reduced signal delay
Vdd/2 switching through the victim net.
 Aggressor/Victim net
switching in opposite
direction leads to increased
t
signal delay through the
Same direction switching victim net.
Crosstalk Delay: Timing Window

Aggressor 1
Victim
Aggressor 2
Victim
VictimNet
NetDelay
Delaywithout Crosstalk
with Crosstalk
Victim
Aggressor 1
Aggressor 2

Effects of Crosstalk Delay
 Delay changes due to affect of switching

aggressor net on victim net needs to be
comprehended:
 During setup check worst case condition
• capture clock is faster, data path and launch clock are
delayed.
 During hold check worst case condition
• capture clock is slower, data path and launch clock are
speedup.

How to Manage Crosstalk?

 Ensure transition timing window for coupling
nets do not overlap.
 For heavily loaded nets improve transition time.
 Minimize use of low drive cells.
 For clocks, shield to minimize coupling.
 Use Physical Design tools capabilities of
avoiding crosstalk during detail route.
Design Planning essential for all of the above.

Additional Design Closure Checks

 Antenna
 Gate Oxide Integrity
 ElectroStatic Discharge/Latchup
 Power EMIR
 Signal EM
 Geometric Verification/Schematic Verification
(GV/SV)

Summary
 Timing & Routability closure for DSM design is

a challenge.
 It is an iterative process between floorplan,
place and route, SDF generation, and STA.
 Timing closure needs to comprehend OCV
and Crosstalk issues.
 Checks need to be done for signal integrity,
reliability, and GV/SV.

Manufacturing Tests
 What is ...
 Screen manufacturing defects.
 When …
 After silicon is fabricated.
Verilog HDL
module clk_mod
(funcclk,testclk,
test_mode,clk);
input funcclk, testclk,
test_mode;
output clk;
always @(test_mode)
begin
if (test_mode) clk =
testclk;
else clk = funcclk;
end

Why Manufacturing Tests?

 The “Rule of Ten” - Cost of detecting/fixing a defect
 During IC test : $ 0.05
 During final test : $ 0.50
 During board test : $ 5.00
 During system test : $ 50.00
 In the field : $ 500.00
 Costly to identify defective parts in a product.  Need
to screen these defects before SoC is integrated in a
product.
 Detect manufacturing defects to deliver reliable and
quality chips.
 Meet SoC customers Defective Part Per Million (DPPM)
requirements.
How to do Manufacturing tests?

 Use Automatic Test Equipment (ATE) to test
the manufactured silicon.
 Types of tests:
 Structural
• Scan ATPG
• Memory BIST
• Jtag Boundary Scan
 Functional
• Slow functional
• At-Speed functional
• Special tests for PLLs or Analog blocks
Manufacturing Tests
 Structural tests are typically generated using
some EDA tools and represent majority of the
test time.
 Functional tests are targeted tests developed
by SoC functional verification team. Typically,
these tests target areas not tested by
structural tests.
 Minimize number of required tester cycles for
both structural and functional tests without
compromising quality of tests.

Why At-Speed Test?

 Operational frequency for designs increasing
rapidly.
 Interconnect issues
 Increasing percentage in path delay in DSM
designs.
 Dominate defects in DSM designs.
 Manufacturing process variations.
 Resistive Vias  Slow-to-rise/slow-to-fall signals at
the input of gates.
 Speed binning.
 Guarantee performance for designs.
Approaches for At-Speed Test
 Functional Tests
 Both Core logic and I/O running at-speed.
 During LED Test core logic runs at-speed and I/O
run at lower frequency. Also referred as
Load/Execute/Unload test.
 Scan-based Techniques
 Logic Built-In Self Test (Logic BIST)

Functional Test: Core & I/O At-speed
 Run design verification patterns at-speed

during manufacturing test.
 Requires expensive ATE
 Chip interfaces need to run at-speed.
 Often requires multiple timing per pin.
 Hard to generate at-speed patterns for ATE.
 Test coverage is typically not available. Need
to run coverage analysis tool to compute test
coverage for these patterns.

Functional Test: LED Test
 Utilizes on-chip memory.

 Internal memory is loaded with target test and
run at-Speed internally.
 Pass/Fail is signaled on slow interface.
 Chip interface does not have to run at-speed
 Compatible with low cost ATE.
 Commonly used for processor based designs.

 09:00 - 10:30 : Session 1.

 10:30 - 11:00 : Morning break.
 11:00 - 12:30 : Session 2.
 12:30 - 13:30 : Lunch break.
 13:30 - 15:00 : Session 3.
 15:30 - 17:00 : Session 4.
 17:00 - 17:15 : Feedback forms.

Advanced Topics (Session 4: 15:30 – 17:00)
 DFT
 Timing Analysis and Closure
 Substrate Noise Analysis
 Power Management
 Package co-design

DFT: Advanced Topics
 At-speed scan based techniques

 Logic BIST

What is At-Speed Scan Based Test?

 CLK: Functional Mode = 250 MHz; Test Mode = 50 MHz.
SD SD SD
Q COMBO Q COMBO Q
D D D
LOGIC LOGIC
SE SE SE
QZ QZ QZ
CLK
Flop N-1 Flop N Flop N+1
SCAN_EN
20 ns 40 ns
CLK
SCAN_EN
PARALLEL
SERIAL SHIFT SERIAL SHIFT
CAPTURE
 For at-speed test, need to stress combo logic at 250 MHz

clock rate instead of 25 MHz.

At-Speed Scan Based Techniques
 Three step process:

 Initialization pattern scan-in.
 Launch cycle to stress cloud of combo logic.
 Capture cycle to register the value for comparison
during scan-out.
 Two Approaches to Launch cycle:
 Launch from shift (last shift used to launch)
 Launch from capture (explicit clock for launch)

At-Speed Scan Based Techniques (contd…)

SD SD SD
Q COMBO Q COMBO Q
CLK D
SE
LOGIC
D
SE
LOGIC
D
SE
Func mode = 250 MHz QZ QZ QZ
Test mode = 50 MHz CLK
Flop N-1 Flop N Flop N+1
SCAN_EN
4 ns
20 ns
Launch CLK
from SCAN_EN
Shift SERIAL SHIFT SERIAL SHIFT
Launch edge Capture edge

4 ns
20 ns
Launch CLK
from SCAN_EN
Capture SERIAL SHIFT SERIAL SHIFT

At-Speed Scan Based Techniques (contd…)

Launch from Shift Launch from Capture
 Sequence of events:  Sequence of events:
 Scan-in  Scan-in
 1-bits last shift  Toggle Scan Enable
 Toggle Scan Enable  Pulse clock for launch
 Pulse capture clock  Pulse capture clock
 Scan-out/Scan-in  Scan-out/Scan-in
 At-speed scan enable  Slow scan enable
 Single cycle,  Dual cycle, sequential
combinatorial ATPG ATPG
 Higher coverage  Slightly lower coverage
 Fewer patterns  More patterns
 Shorter run time for  Longer run time for
ATPG ATPG
At-Speed Scan Challenges
 Generating at speed clock pulse for launch and

capture edge: internal vs. external (ATE)
 Launch from shift seems to be better than launch from
capture to reduce TEST cost  Scan Enables needs
to operate at-speed.
 For large SoC, difficult to guarantee this from external
pin  Use pipelined scan enable.
 Commercial ATPG tools are learning to cope with
pipelined scan enable.
 Long test time, but improving with each ATPG tool
release.
Logic BIST
 Existed since early/mid-80’s.
 Standard scan techniques combined with Structural
techniques to generate patterns and output signature
on-chip.
 Based on properties of Linear Feedback Shift Register
(LFSR)
 Extra logic on chip.
 Enables system/field test.
 Can be used for at-speed testing.
 Compatible with low cost ATE.

What is LFSR?
 Shift register with outputs of some flops combined in XOR
configuration and feedback as inputs to flops.
O1 O2 O3
I1 I2 I3
0 0 1 Initial
D Q D Q D Q
1 0 0
0 1 0
QZ QZ QZ
Flop 1 1 0 1
CLK
Flop 2 Flop 3
1 1 0
1 1 1
0 1 1
O1 O2 O3
 Generates pseudo-random patterns of 1s and 0s.

 Maximal-length LFSR produces 2n-1 non-repeating patterns.
 XOR feedback structure and Initial seed controls patterns.
 Used as Pseudo-Random Pattern Generation (PRPG) and
Multiple-Input Signature Register (MISR).
Logic BIST: A Typical Implementation
PRPG LFSR
MISR LFSR
Scan
Chains
DUT
BIST Controller
 Number of scan chains equal to width of LFSR.

 Pattern source random  Pattern volume large and lower fault
coverage compared to normal ATPG.
 Long self-test runs  Inefficient use of ATE resources.
 Difficult to test random pattern-resistant (RPR) faults.
 No unknowns (X) allowed in the circuit.
 Fault diagnosis difficult.
 Aliasing problem in output signature.
Variations of Logic BIST
PRPG LFSR
Phase Shifter
MISR LFSR
Scan
Chains
DUT
BIST Controller
 Phase shifter is a combinational block that maps “n inputs” to “k

outputs” (k > n ) to allow many short scan chains to reduce
pattern count and test time  Reduced width for PRPG LFSR.
 Phase shifter reduces structural dependencies.
 PRPG LFSR reconfigurable & possible to load different seeds.
 Use deterministic ATPG to produce seeds for PRPG.
 Still need to change logic to avoid X propagation.

Variations of Logic BIST (contd…)
PRPG LFSR
Phase Shifter
Mux Structure
Scan
Chains
DUT
BIST Controller
 MISR LFSR replaced with a Mux structure to observe

selected scan chains.
 No changes necessary in the logic to avoid X propagation.
 No MISR to generate observation signature  No Aliasing.

Summary
 At-speed testing can be done using scan.
 Logic BIST can be used to enable system/field
testing.
 Variants of traditional Logic BIST becoming popular
approaches.
AJ/AS/JR Jan. 6, 2005 VLSI Design 2005

Timing Analysis and Closure:

Advanced Topics
 Useful clock skew.
 Timing analysis for process variability.

Timing Closure: Useful Clock Skew

 Controlling and managing skew in clock network
essential part for timing closure.
 Traditional timing closure flow:
 Goal is to minimize clock skew.
 Ignore data path timing and rely on user specified offsets to
expand and balance clocks.
 Better timing correlation between pre-CTS and post-CTS
analysis.
 Minimize number of Hold buffers.
 For DSM designs, clock skew can be used to
advantage by intelligently skewing clock arrivals.

What is Useful Clock Skew?

Minimize Clock Skew CLK Delays:
CLK  CLK1 = 2.00 ns
Flop1 Flop2 Flop3
Slow
D Q Fast Combo D Q D Q CLK  CLK3 = 1.95 ns
Logic Combo Flop2 Slack:
CLK1 CLK2 CLK3
QZ QZ Logic QZ Setup = 1.50 ns
Hold = 0.20 ns
CLK
Flop3 Slack:
Setup = -0.5 ns
Hold = 1.50 ns
Useful Clock Skew CLK Delays:

Flop1 Flop2 Flop3 CLK  CLK2 = 1.50 ns
D Q D
Slow D CLK  CLK3 = 1.95 ns
Fast Combo Q Q
Logic Combo Flop2 Slack:
CLK1
QZ
CLK2
QZ Logic CLK3
QZ
Setup = 0.90 ns
Hold = 0.80 ns
Flop3 Slack:
CLK
Setup = 0.10 ns
Hold = 0.90 ns

Useful Clock Skew

 Why?
 Improves performance by increasing clock
frequency.
 Enables faster timing closure for hard to fix paths.
 Minimize number of critical paths (both setup and
hold)  More robust design.
 Clock toggles spread over wider timing window 
Reduces peak dynamic power.
 How?
 Do timing analysis using ideal (zero clock skew).
 Use above data during CTS.
Timing Analysis for Process Variability

 Typical observations in DSM and sub-nanometer
regime:
 Parameters (Leff, VT, Tox, etc.) across chips are different.
 Parameters within the same chip are also different.
 Why?
• Feature size is getting smaller than “Lithography
Wavelength”  Some mask information is lost.
• Critical dimensions are scaling faster  Less Control.
• Back End Of Line (BEOL) variability.
• Across Chip Line-width Variations (ACLV).
• Across-the-chip temperature and VDD variation.
 Designers and Business goals require as many chips
as possible to “work”.
“Nano-CMOS Circuit and Physical Design,” Ban Wong, Anurag Mittal, Yu Cao, Greg Starr, ISBN:0-471-46610-7

What are the different kinds of variations?
 Two Kinds:
 Inter Die
 Intra Die

What are Inter-Die process variations?

 Difference in the value of a parameter across
nominally identical dies. These could be fabricated on
the same wafer or different wafers or different lots.
 Mainly design independent.
 Related to equipment properties, wafer placement,
processing temperatures etc.
 Example:
• Metal and/or dielectric layers might be thicker/thinner
• Each exposure could be over/under exposed
• Each layer could be over/under etched
“Manufacturing aware Physical Design,” Puneet Gupta and Andrew B. Kahng, Proc IEEE/AM Intl Conference on
Computer Aided Design, November 2003

What are Intra-die process variations?
 Deviation occurring spatially within any die.

 Variation could arise from wafer level trends and
layout-pattern dependencies.
• Optical Proximity Effects
• Metal Density Effects
• Center vs. Corner Focus
 Fluctuations in channel doping, gate oxide thickness
and ILD permittivity could be more random.
(Statistical)
“Manufacturing aware Physical Design,” Puneet Gupta and Andrew B. Kahng, Proc IEEE/AM Intl Conference on
Computer Aided Design, November 2003

Conventional approaches to tackle

process variability
 Worst case corners
 Cannot handle intra-chip variation
 Multiple corner analysis – becomes formidable!!
 Classify each signal/gate as clock or data
 Cases: both clock and data maximally slow, clock
maximally slow and data almost as slow, etc.
 Goes against Time to Market goals.
 Problems with these approaches
 Too pessimistic Leaves performance on the table.
 Not pessimistic enough: doesn’t handle fast M1, slow
M2
Interconnect variation - Net delays, Path

delays are f(P)
 CNET= fcap(P0, P1, P2, …)
 DELAYNET= fnet(P0, P1, P2, …)
P5
P4 Pitch is well controlled

Width and spacing
These dimensions can P3
P2 are not
vary independently
independent
P1
P0

Explicit Computation Approach

 Represent delay value, D, as a Taylor series:
D = Dnom + Σ di x ∆pi (i = 1 to N)
where, di describe how the value varies with a
change in process parameter ∆pi and N is number
of parameters.
 Example: If the parameters are Leff, Vt and Tox
then the delay value can be represented as follows
D = Dnom + d(Leff) x ∆p(Leff) + d(Vt) x ∆p(Vt) + d(Tox) x ∆p(Tox)
 ∆pi itself has 2 parts ∆pi = ∆Gi + ∆si,d
 ∆Gi is global (chip-wide variation).
 ∆si,d is the statistical variation of this value.

 Consider the constraint that the difference
between data arrival (A) and clock arrival (C) must
be less than the cycle time (Tmax):
 A(P) – C(P) < Tmax; P is a vector of process parameters
 Substituting in the above inequality gives us
 Anom – Cnom + Σi(ai – ci) ∆Gi + Σi(aisia – cisic) < Tmax
Global Statistical


N
D = D0 + ∑ di • ∆ pi
D = D0 + ∑
N
di • ∆ pi
i=1
i= 1
N
D = D0 + ∑ di • ∆ pi
N i= 1
D = D0 + ∑
N
di • ∆ pi
D = D0 + ∑ di • ∆ pi
i= 1
i=1
N
D = D0 + ∑ di • ∆ pi
i= 1
 Propagate functions
 Timing analysis is done first, then plugs the
process distributions to get timing distributions.
 Different distributions can be evaluated in one-shot.
Traditional Delay Vs. Statistical Delay

Statistical Delay Variation

 Different things contributing to variation may have
different characteristics.
 Some are correlated and some are not.

Statistical Static Timing Analysis (SSTA)
 Propagate arrival time distributions.

 Statistical timer.
 Result is a distribution of delays / slacks at each
of the outputs.

Real Situation: Combination of both

 Gate delays are somewhat correlated but have a
big statistical component
 Wire delays (particularly close wires) are very
highly correlated but have a small random
component.
 Delays consist of two parts that combine differently
N
∑
N
D = D0 + di • ∆ Gi
i= 1
D = D0 + ∑i= 1 di • ∆ Gi
N
Distribution of statistical part is also
D = D0 + ∑ d i • ∆ Gi
i= 1 a function of process variation

Summary
 Useful clock skew can be used
 To achieve higher clock rate
 To have a robust design
 Reduce timing closure iterations
 Minimize switching power.
 Statistical variations (both inter-die and intra-die) of
process parameters need to be comprehended in a
DSM SoC design.
 Two approaches for timing analysis:
 Explicit computation
 Statistical analysis.
Substrate Noise Analysis
 Definition
 Substrate Noise Analysis flow
 Noise minimization methods

The Substrate Noise Crisis
Digital Block Digital Block

D1 D2
Noise Generation Noise Sensitivity
Increased # of Digital Gates Increased Signal Resolution

Higher Frequency Analog Higher Frequency
Sharper Transition times Lower Operating Voltages
Digital Block
D3
 This is a huge careabout for mixed-signal SoC,

high performance PLL Cores, high-speed IO
interfaces, RF designs and high-speed A/D and
D/A analog blocks.
Key Challenges
 Substrate noise generated by digital
components can degrade sensitive analog
circuit performance  To simulate this
performance degradation, the total amount of
generated noise must be known.
 Simulating large digital circuits for noise
analysis is prohibitive in terms of run-times
and memory needs  Need to model
substrate noise source from digital blocks.

Substrate Noise Analysis Flow

Digital Block level Substrate Noise Model
Block-level Block-level
Switching SPICE Substrate
Activity Noise Model
Extract Noise at Analog Substrate

Block-level Substrate
Layout
model Analog
Block
Block-level
Block-level Noise at
Block-level
Substrate
Block-level
Substrate
Substrate
Noise Model
SPICE Analog
NoiseSubstrate
NoiseModel
Model substrate
Noise Model
Chip Package
Model

Substrate Noise Analysis: Example

 Design consists of 12 digital blocks with a frequency range from
75 MHz – 150 MHz.
 I/O interface frequency in the range of 1 MHz – 150 MHz.
 Total decoupling cap ~50nF.
 Wire bond BGA package.
Substrate Noise Frequency Spectrum
40.00
35.00
Substarte Voltage (mV)
30.00
25.00
wo_guardrings
20.00
w_guardrings
15.00
10.00
5.00
0.00
0.00 0.50 1.00 1.50 2.00 2.50 3.00
Frequency (GHz)

Noise Minimization Methods

 Designing Noise Sensitive Ckts fully
differential or at least pseudo-differential.
 Reduce impedance on Supply-Ground
network.
 Package inductance minimization.
 On-Chip decoupling capacitors to the extent
possible.
 Provide low-impedance substrate contacts.
e.g., Guard Rings.
 Thorough Package Analysis to take prevent
Noise Coupling as much as possible.
Power Management
 Definitions
 Dynamic/Active power
 Static/Leakage power
 Power management techniques
 Dynamic
 Static

Power Management – Motivation

 Maximize Battery life for portable or hand held
applications.
 Optimize package cost.
 Reduce voltage drop to minimize impact on
path delays.
 EM can cause voids (or open circuits) or
hillocks (or shorts with neighboring wires) 
Non-functional silicon.

Power Management – Definitions

 Active or Dynamic Power
 Pdynamic = Pswitching + Pshort-circuit
 Pswitching: Primarily due to actively changing states of
the circuit due to constantly charging and
discharging of the effective capacitive loads
• Pswitching= Switching Activity x freq x Ceff x Vdd2
• Clock power is the largest contributor (nearly 75%)
• Interconnect is the largest consumer
 Pshort-circuit: Momentary “crowbar” current flowing
between VDD and GND when transistor stacks
switch state

Power Management – Definitions (contd…)

 Leakage or Static Power
 Primarily contributed by source-to-drain leakage
current that increases with lowering VT (threshold)
and increasing temperature.
 Voltage drop
 Supply voltage reduction across a large die as
current flows through its power grid.
 Electro-Migration (EM)
 Flow of metal ions under the influence of high
electric current densities resulting in depletion and
accumulation of metal ions along the interconnect.
Power Management - Trends

5
4
40-50% is leakage
3 power
Power (W)
0
250 180 130 90 65
Leakage Power
Feature Size (nm)
Active Power

Dynamic Power Management Techniques

 Clock Gating
 Selectively turn OFF registers when not needed.
 Power Gating
 Shut OFF power to blocks in stand-by mode.
 Retention flip-flops (on an isolated power supply) can be used
to save the logic state of all sequential elements when the
chip is powered down.
 Eliminates need to re-initialize the device when coming out of
stand-by mode.
 Power-aware Physical design
 Reduce capacitive loading by down-sizing gates.
 Minimize wire length.

Dynamic Power Management Techniques:

Voltage Islands
 Partition design into:
 High speed blocks fed by higher voltage.
 Low speed blocks fed by lower voltage.
 Need Level Shifters (LS) between blocks operating at different
voltage levels and ensure correctness of LS connectivity.
V1 V2
1.2V 1.5V
250 MHz 300MHz
LS
V3 (0.8V)
150 MHz
LS
CORE V2 (1.5V)
300 MHz
 Need Scaleable Polynomial Library (SPM) support

 Additional careabouts related to scan stitching and clock
distribution required.
Leakage Power Management Techniques

 Multi-Voltage Threshold Libraries
 Higher VT cells have lower leakage power but are
slower
 Lower VT cells have higher leakage power but are
faster
 Target initial logic synthesis with high VT cells and
then selectively swap high with low VT cells on
performance-critical paths
 Power Gating also an option here
 Power down blocks to save sub-threshold leakage
Power Integrity Analysis

 Static Voltage drop
 Vstatic = I x R
 Current supplied by power network
 Remedy:
• Power grid sizing and optimization
• Use of flip chip package
 Dynamic Voltage drop
 v(t) = i(t) x R + L x di(t) / dt
 Need to also assess impact on sign-off timing.
 Remedy:
• Power grid sizing
• Insert de-coupling capacitors to minimize voltage fluctuations on
power grid.

Package Co-design
 Motivation
 Selection of Package-Die combination
 Package Design and Routability
 Package Signal Integrity and Modeling

Silicon – Package Co-design

 Motivation
 Choosing the appropriate package-die combination,
e.g., flip-chip based device.
 Ensure package substrate design routability.
 Interface with the Silicon Floor-planning activities to
make the correct choices of IO buffers and
floorplan choices.
 Address the IC, Package, and Product Signal
Integrity issues.
 Package-Die combination needs to be viewed
holistically to enable cost vs. performance
tradeoffs.
Choosing the appropriate Package-Die

combination
 Flows from Product Requirements.
 Assessing impact of following competing parameters for
“Wire-bond” vs. “Flip-Chip” package types
 Die-size  Design rules
 Buffer Placement (Floor-planning)  Signal routing
 Substrate technology  Device Ball Map
 Number of layers  Cost tradeoffs
 For a Flip-Chip a slightly larger Die-size could be
less expensive due to less expensive package
substrate.
 A smaller die requires more layers in package substrate.
 Finer design rules to route the design successfully.
Choosing the appropriate Package-Die

combination (contd…)
Peripheral Approach
 Tradeoff of bump placement
at Core vs. Periphery.
 Peripheral approach
• Silicon floor-planning may be
simplified at the potential cost
of larger die to accommodate
the same number of signals.
 Core approach Core Approach
• May increase performance,
but simultaneously introduce
complexity in your floor-
planning process related to
routing, substrate selection
and PCB routing.

Package design & routability assessment

 The following items need to be addressed during routability
assessment.
 The bump pattern (tile pattern), total signal I/O, number of power
levels, and device performance steer the selection of the
substrate technology, number of layers, stack-up topology, and
signal routing design rules.
 High-speed interface requirements are translated to targets for
package designers
• Characteristic impedance
• Time Delay
• Power Plane Inductance
 Addressing signal integrity issues through Electromagnetic
Simulations.
 Need to meet mechanical reliability and substrate manufacturing
robustness.
• Assessment results needs to be fed into the bump plan.
Package signal integrity and Modeling

 Electrical performance of package substrate cannot
be ignored at high frequencies. The following need to
be considered for impacting SI performance:
 Transmission line effects
 High frequency propagation losses and
 EMI
 All aspects of the substrate 3-D topology must be
considered.
 The overall package power and ground networks.

Package signal integrity and Modeling

(contd…)
 A typical Package performance assessment
includes
 Understanding the Signal performance
• Providing crosstalk analysis for high-speed (SerDes)
differential pairs.
• Determining return loss and insertion loss for critical signal
paths.
 Understanding the plane performance
• Impedance of the power plane for a bandwidth of several GHz.
• Simulations involving internal bypass capacitance (IC) to verify
its effect on the resonant behavior.

Future Directions
 Adoption of Advanced tools and techniques

addressed in this session.
 Automation of Golden model generation;
Executable spec to SystemC model.
 High-level design planning tool.
 Formal methods for functional verification.
 PBIST (Programmable BIST)
 Mixed signal integration.

Acknowledgements and Contacts

 We would like to acknowledge
 Colleagues from TI who have helped in numerous
ways in putting this presentation together.
 Reviewers from VLSI Design 2005 for their
feedback.
 TI management for their encouragement and
support.
 Contacts:
 Atul Jain (atuljain@ti.com)
 Anindya Saha (asaha@ti.com)
 Jagdish Rao (j-rao@ti.com)
Bibliography
Books
1. “Reuse Methodology Manual for System-On-A-Chip Designs,” Micheal Keating, Pierre Bricaud, by Kluwer
Academic Publishers, ISBN: 0792381750.“
2. Hardware/Software Co-design,” Giovanni De Micheli, Mariagiovanni Sami, Published by Kluwer Academic
Publishers, ISBN: 0792338839.
3. “Principles of Functional Verification,” Andreas Meyer, Published by Butterworth-Heinemann Newnes.
4. “Logic Synthesis,” Srinivas Devdas, Abhijit Ghosh, Kurt Keutzer, Published by McGraw Hill Professional, ISBN:
0070165009.
5. “Digital Systems Testing and Testable Design,” M. Abramovici, M.A. Breuer and A.D. Friedman, IEEE Press,
New York.
6. “Design-For-Test For Digital IC's and Embedded Core Systems,” Alfred Crouch, Sep 1999, ISBN: 0130848271.
7. “Timing Verification of Application-Specific Integrated Circuits (ASICs),” Farzad Nekoogar, Published by
Prentice Hall PTR, ISBN 0137943482.
8. “Algorithms for VLSI Physical Design Automation,” N. Sherwani, Published by Kluwer Academic Publishers.
9. “VLSI Physical Design Automation – Theory and practice,” S. Sait and H. Youssef, Published by McGraw Hill.
10. “Signal Integrity – Simplified,” Eric Bogatin, Publisher : Prentice Hall PTR, September 2003, ISBN : 0-13-
066946-6.
11. “Modern VLSI Design: System-on-Chip Design,” Wayne Wolf. Published by Prentice Hall PTR, January 2003,
ISBN: 0130619701.
Papers
1. “Nano-CMOS Circuit and Physical Design,” Ban Wong, Anurag Mittal, Yu Cao, Greg Starr, ISBN:0-471-46610-
7.
2. “Impact of Die-to-Die and within Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for
Gigascale Integration,” Keith A. Bowman, Steven G. Duvall and James D. Meindl, in IEEE Journal of Solid-
State Circuits, vol. 37, Feb 2002.
3. “Manufacturing aware Physical Design,” Puneet Gupta and Andrew B. Kahng, Proc IEEE/AM Intl Conference
on Computer Aided Design, November 2003.
4. “Characterization of the Threshold Voltage Variation: a Test Chip and the Results,” Mariusz Niewczas, IDCMTS
1997.

Bibliography (contd…)
Papers (contd…)
1. “Impact of Spatial Intrachip Gate Length Variability on the Performance of High-Speed Digital Circuits,” Michael
Orshansky, Linda Milor, Pinhong Chen,Kurt Keutzer and Chenming Hu, IEEE TRANSACTIONS ON
COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 21, no. 5, MAY 2002.
2. “Statistical Metrology: Tools for Understanding Variation,” Duane Boning and James Chung in Future Fab
International, December 1996.
3. “Explicit Computation of Performance as a Function of Process Parameters,” L. Scheffer in 2002, ACM/IEEE
Tau workshop on Timing Issues in the Specification and Synthesis of Digital Systems.
4. “First-Order Parameterized Block-Based Statistical Timing Analysis,” K. Kalafala, C Visweswariah, K Ravindran
in 2002, ACM/IEEE Tau workshop on Timing Issues in the Specification and Synthesis of Digital Systems.
5. “Fast Statistical Timing Analysis by Probabilistic Event Propagation,” J.-J Liou, K.-T.Cheng, S. Kundu and A.
Krstic, Proc. 38th Design Automation Conference, June 2001.
6. "Leakage Current in Low Standby Power and High Performance Devices: Trends and Challenges,” G.C-
F.Yeap, Proceedings of 2002 International Symposium on Physical Design.
7. "Leakage-Tolerant Design Techniques for High Performance Processors,” V. De, Proceedings of 2002
International Symposium on Physical Design.
8. "Power reduction by simultaneous voltage scaling and gate sizing,” Chen C., and Sarrafzadeh M, Proceedings
of ASPDAC '00.
9. "Incremental Delay Change due to Crosstalk Noise,” Lauren Hui CHen and Malgorzata Marek-Sadowska,
Proceedings of 2002 International Symposium on Physical Design.
10. "Uncertainty-Aware Circuit Optimization,” Xiaoliang Bai, Chandu Visweswariah, Philip N. Strenski, David J.
Hathaway, Proceedings of 39th Design Automation Conference, 2002.
11. "Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering
Technique,” Mohab H. Anis, Shawki M. Areibi, Mohamed K. Mahmoud, Mohamed Elmasry, Proceedings of 39th
Design Automation Conference, 2002.

Bibliography (contd…)
Conference Proceedings
1. IEEE International SOC Conference.
2. Design Automation Conference.
3. International Test Conference.
4. International Conference on VLSI Design.
5. International Conference on Computer Aided Design.
6. Design, Automation, and Test in Europe Conference.
7. IEEE Custom Integrated Circuits Conference.
EDA Tool Vendors Documentation

 09:00 - 10:30 : Session 1.

 10:30 - 11:00 : Morning break.
 11:00 - 12:30 : Session 2.
 12:30 - 13:30 : Lunch break.
 13:30 - 15:00 : Session 3.
 15:30 - 17:00 : Session 4.
 17:00 - 17:15 : Feedback forms.

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SoC Design Methodology: A Practical

Schedule for Tutorial

 09:00 - 10:30 : Session 1.

Schedule for Tutorial

 09:00 - 10:30 : Session 1.

Session 1 (9:00 – 10:30)

What is System on a Chip (SoC)?

Why SoCs: Potential chip-level savings?

Typical chip-level Savings of 30% - 45% using SoC!!!

Why SoCs: Potential board-level savings?

* Source: “Reuse Methodology Manual For System-On-a-Chip

 Based on traditional ASIC flow RTL Development

Spiral Development Model

Spiral Development Model (contd…)

Trial Scan Insertion HW/SW Co- App. testing

Final Place and Route

AJ/AS/JR Jan. 6, 2005 VLSI Design 2005 13

Spiral Development Model (contd…)

HW-SW System- Executable

RTL / ISS HW-

SDF Generation / STA Simulation Optimization

CTS & DRoute Formal Verification

FVEC (Gates-Gates) DFT

AJ/AS/JR Jan. 6, 2005 VLSI Design 2005 16

Needs for Robust SoC Methodology

Design Start (contd…)

Design Start (contd...)

Design Start (contd…)

Principles of Die size Estimation

Quality and Reliability

Design Prototyping & Partitioning

 Hardware vs. Software tradeoffs

SoC Prototyping – All about tradeoffs

 Early & Incomplete

Design Prototyping & Partitioning

Physical Hierarchy Planning

Design Prototyping: Examples

Physical Partition Bad Pin Assignment

Design Partitioning: Example

RAM RAM RAMRAM

“Divide and Conquer” approach for partitioning the design into

 Used to develop IP and architecture RTL of my_mod is

RTL for SoCs?

Schedule for Tutorial

 09:00 - 10:30 : Session 1.

Session 2 (11:00 – 12:30)

What is Functional Verification?

Functional Verification: SoC

Types of Verification Tests

Types of Verification Tests (contd…)

Verification Metrics (contd…)

Functional Verification: An Example

Behavioral / Full Functional / RTL / Gate-level Model

Code / Functional Coverage hooks

Bus Cycle Generation Model

High-level Verification Code

Verification Test Plan

Verification Test Plan (contd…)

 Minimize number of required tests without

SoC Verification: Example

 RTL Blocks verified at module-level

SoC Verification: Example (contd…)

 How to Speed up simulation time?