SRM University

Faculty of Engineering and Technology

Department of Electronics and Communication Engineering

Design Project Summary

Note: ABET’s 2008-2009 requirements for design projects are as follows:

Criterion 3 (c):
“an ability to design a system, component, or process to meet desired needs within realistic
constraints such as economic, environmental, social, political, ethical, health and safety,
manufacturability, and sustainability”

Criterion 5:
“Students must be prepared for engineering practice through a curriculum culminating in a major
design experience based on the knowledge and skills acquired in earlier course work and
incorporating appropriate engineering standards and multiple realistic constraints.”

Project Title : IMPROVED AREA EFFICIENT WEIGHTED MODULO 2N+1 ADDER

DESIGN WITH SIMPLE CORRECTION SCHEMES.

Supervisor/Guide: Mrs A. Maria Jossy

Team Members: 1) Adithiyan.M [10407218]

2) Vandana.D. Shah [10407198]
3) Vikas.P [10407209]

Background/Literature Review:
Some papers referred are:

1. R. Zimmermann, “Efficient VLSI implementation of modulo 2n ± 1 addition and multiplication,”

in Proc. 14th IEEE Symp. Comput. Arithmetic, Apr. 1999, pp. 158–167.

2. H. T. Vergos, C. Efstathiou, and D. Nikolos, “Diminished-one modulo 2n + 1 adder design,” IEEE

Trans. Comput., vol. 51, no. 12, pp. 1389–1399, Dec. 2002.

3. H. T. Vergos and D. Bakalis, “On the use of diminished-1 adders for weighted modulo 2n + 1
arithmetic components,” in Proc. 11th EUROMICRO Conf. Digit. Syst. Des. Archit., Methods Tools,
Sep. 2008, pp. 752–759.

4. J. Sklansky, “Conditional sum addition logic,” IRE Trans. Electron. Comput., vol. EC-9, no. 6, pp.
226–231, Jun. 1960.

Objective:
To design an improved area-efficient weighted modulo 2n + 1 adders. This is achieved by
modifying existing diminished-1 modulo 2n + 1 adders to incorporate simple correction schemes to
produce modulo sums within the range {0, 2n}, which is more than the range {0, 2n − 1} produced by
existing diminished-1 modulo 2n + 1 adders.
Technical Requirements:
Model Sim 6.4, Xilinx ISE 7.1i

Engineering standards and realistic constraints in these areas:

Area Codes & Standards / Realistic Constraints

Economic It is a cost effective process which does not involve much of an
expenditure.
Environmental This project is not expected to entail any particular environmental
consequences.
Social This project will not entail any social constraints nor will it have
societal impact.
Ethical This project is not expected to entail ethical constraints.

Health and Safety This project is not expected to entail health and safety constraints.
Manufacturability This project must be easily replicated as it is very easy to design
which requires only the access to softwares like Modelsim and
Xilinx. This project can be used for various applications. Further
advancement is also possible.
Sustainability Not Applicable

Realistic Constraints:

This project describes the adders that can outperform previously reported weighted modulo adders in
terms of area in the same delay constraints.

Deliverables:

1) An improved area efficient modulo adder will be designed having less area consumption with
the same delay constraints.

Abstract:

These efficient adders are done by modifying existing diminished-1 modulo 2n + 1 adders to
incorporate simple correction schemes. Our adders can produce modulo sums within the range {0, 2n},
which is more than the range {0, 2n − 1} produced by existing diminished-1 modulo 2n + 1adders. The
area required for the adders is lesser than previously reported weighted modulo 2n+ 1 adders with the
same delay constraints. The improved area-efficient weighted modulo 2n + 1 adder design is done
using diminished-1 adders with simple correction schemes. This is achieved by subtracting the sum of
two (n + 1)-bit input numbers by the constant 2n + 1 and producing carry and sum vectors. The modulo
2n + 1 addition can then be performed using parallel-prefix structure diminished-1 adders by taking in
the sum and carry vectors plus the inverted end-around carry with simple correction schemes. The area
cost for the proposed adders is low. In addition, the adders do not require the hardware for zero
detection that is needed in diminished-1 modulo 2n + 1 addition.

Fig (a): Architecture of the improved area efficient adder with correction schemes