Vansh Tomar - 035 - Training Report VHDL - ECE 3

Thesis/Report submitted in partial fulfilment of the requirement for the degree of
B.Tech.
in
Electronics and Communications Engineering

Under the Supervision of
Mr. Mukesh Sahu

By
Vansh Tomar
ECE-3
03576802818
rajachoudhary697@gmail.com
To
Guru Tegh Bahadur Institute of Technology, Delhi

(affiliated GGSIPU)
October, 2020
Vansh Tomar | ECE 3 | 03576802818
Declaration
This is to certify that Thesis/Report entitled “Digital System Design using VHDL”
which is submitted by me in partial fulfilment of the requirement for the award of
degree B.Tech./MTech. in Electronics and Communications Engineering to Guru
Tegh Bahadur Institute of Technology, Delhi (affiliated GGSIPU) comprises only
my original work and due acknowledgement has been made in the text to all other
material used.
Date: 19 June 2020
Name of Student: Vansh Tomar (03576802818)
APPROVED BY: -
Dean/Director
Guru Tegh Bahadur Institute of
Technology
Vansh Tomar | ECE 3 | 03576802818
Certificate
Vansh Tomar | ECE 3 | 03576802818
Acknowldegment
I take this opportunity to express my profound gratitude and deep regards to my guide
(Mr.Mukesh Sahu) for their exemplary guidance, monitoring and constant
encouragement throughout the course of this report. The blessing, help and guidance
given by them time to time shall carry me a long way in the journey of life on which I
am about to embark.I also take this opportunity to express a deep sense of gratitude
to my batchmates for valuable information and guidance, which helped me in
completing this task through various stages.
I am grateful for their cooperation during the periodof my assignment.
Lastly, I thank almighty, my parents and friends for their constant encouragement
without whichthis assignment would not be possible.
Vansh Tomar | ECE 3 | 03576802818
Contents
Introduction ........................................................................................................................ 8
1.2 History ........................................................................................................................ 8
1.3 Capabilities ................................................................................................................. 9
2. A Tutorial ................................................................................................................... 11
2.1 Basic Terminology ................................................................................................... 11
2.1.2 Architecture ............................................................................................................. 12
2.2 Levels of Abstraction.................................................................................................. 14
2.2.1 Behavioral Modeling……………………………………………………………………………………………11
2.2.2 Dataflow Modeling………………………………………………………………………………………………11
2.2.3 Structural Modeling…………………………………………………………………………………………….11
2.2.3.1 Component Declaration ........................................................................................ 16

2.2.3.2 Component
Instantiation…………………………………………………………………………………………………………………13
2.3 Libraries in VHDL………………………………………………………………………………………………….…14
2.3.1 Design Library……………………………………………………………………………………………………15
2.4 Putting It Together!! ……………………………………………………………………………………………16
2.5 Simulation................................................................................................................. 20
3. Basic Language Elements............................................................................................ 21
3.1. Lexical Elements…………………………………………………………………………………………………….17
3.1.1. Comments……………………………………………………………………………………………………...…17
3.1.2. Identifiers………………………………………………………………………………………………………….17
3.1.3. Numbers……………………………………………………………………………………………………………17
3.1.4. Characters…………………………………………………………………………………………………………17
3.1.5. Strings…………………………………………………………………………………………………………….…17
3.1.6. Bit Strings………………………………………………………………………………………………………….17
3.2 Data Types and Objects……………………………………………………………………………………………
3.2.1. Integer Types .......................................................................................................... 22

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3.2.2. Physical Types ........................................................................................................ 23

3.2.3. Floating Point Types ............................................................................................... 24
3.2.4. Enumeration Types ................................................................................................. 24
3.2.5. Arrays ..................................................................................................................... 25
3.2.6. Records ................................................................................................................... 26
3.2.7. Subtypes ................................................................................................................. 27
3.2.8. Object Declarations ................................................................................................ 27
3.3. Expressions and Operators........................................................................................ 28
3.4. Sequential Statements ............................................................................................... 29
3.4.1. Variable Assignment .............................................................................................. 29
3.4.2. If Statement ............................................................................................................ 29
3.4.3. Case Statement ....................................................................................................... 30
3.4.4. Loop Statements ..................................................................................................... 30
3.4.5. Null Statement ........................................................................................................ 31
3.4.6. Assertions ............................................................................................................... 32
 Software Overview (Xillinx)

o Project Navigator
o Panels
o Workspace
o Understanding the ISE Project File
o Creating a project
 VHDL Projects
 Conclusion
 Future Aspect
 Refrences
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Preface
VHDL is a hardware description language that can be used to model a digital system.
It contains elements that can be used to describe the behavior or structure of the digital
system, with the provision for specifying its timing explicitly. The language provides support
for modeling the system hierarchically and also supports top-down and bottom-up design
methodologies. The system and its subsystems can be described at any level of abstraction
ranging from the architecture level to gate level. Precise simulation semantics are associated
with all the language constructs, and therefore, models written in this language can be
verified using a VHDL simulator.
VHDL is a large and verbose language with many complex constructs that have
complex semantic meanings and is difficult to understand initially (VHDL is often quoted to
be an acronym for Very Hard Description Language). However, it is possible to quickly
understand a subset of VHDL which is both simple and easy to use. The emphasis of this text
is on presenting this set of simple and commonly used features of the language so that the
reader can start writing models in VHDL. These features are powerful enough to be able to
model designs of large degrees of complexity.
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Introduction
1.1 What Is VHDL?

VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for
Very High Speed Integrated Circuits). It is a hardware description language that can be used to
model a digital system at many levels of abstraction ranging from the algorithmic level to the
gate level. The complexity of the digital system being modelled could vary from that of a simple
gate to a complete digital electronic system, or anything in between. The digital system can also
be described hierarchically. Timing can also be explicitly modelled in the same description.
The VHDL language can be regarded as an integrated amalgamation of
following languages:
sequential language + concurrent language + net-list language + timing
specifications + Waveform generation language => VHDL
Therefore, the language has constructs that enable you to express the concurrent or sequential
behavior of a digital system with or without timing. It also allows you to model the system as an
interconnection of components. Test waveforms can also be generated using the same
constructs. All the above constructs may be combined to provide a comprehensive description
of the system in a single model.
The language not only defines the syntax but also defines very clear simulation
semantics for each language construct. Therefore, models written in this language can be
verified using a VHDL simulator. It is a strongly typed language and is often verbose to write. It
inherits many of its features, especially the sequential language part, from the Ada programming
language. Because VHDL provides an extensive range of modeling capabilities, it is often
difficult to understand. Fortunately, it is possible to quickly assimilate a core subset of the
language that is both easy and simple to understand without learning the more complex features.
This subset is usually sufficient to model most applications. The complete language, however,
has sufficient power to capture the descriptions of the most complex chips to a complete
electronic system.
1.2 History
The requirements for the language were first generated in 1981 under the VHSIC program. In
this program, a number of U.S. companies were involved in designing VHSIC chips for the
Department of Defense (DoD). At that time, most of the companies were using different
hardware description languages to describe and develop their integrated circuits. As a result,
different vendors could not effectively exchange designs with one another. Also, different
vendors provided DoD with descriptions of their chips in different hardware description
languages. Reprocurement and reuse was also a big issue. Thus, a need for a standardized
hardware description language for design, documentation, and verification of digital systems
was generated.
A team of three companies, IBM, Texas Instruments, and Intermetrics, were first
awarded the contract by the DOD to develop a version of the language in 1983. Version 7.2 of
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VHDL was developed and released to the public in 1985. There was a strong industry
participation throughout the VHDL language development process, especially from the
companies that were developing VHSIC chips. After the release of version 7.2, there was an
increasing need to make the language an industry-wide standard. Consequently, the language
was transferred to the IEEE for standardization in 1986. After a substantial enhancement to the
language, made by a team of industry, university, and DoD representatives, the language was
standardized by the IEEE in December 1987; this version of the language is now known as the
IEEE Std 1076-1987. The official language description appears in the IEEE Standard VHDL
Language Reference Manual made available by the IEEE. The language described in this book
is based on this standard. The language has since also been recognized as an American National
Standards Institute (ANSI) standard.
The Department of Defense, since September 1988, requires all its digital Application-
Specific Integrated Circuit (ASIC) suppliers to deliver VHDL descriptions of the ASICs and
their subcomponents, at both the behavioral and structural levels. Test benches that are used to
validate the ASIC chip at all levels in its hierarchy must also be delivered in VHDL. This set of
government requirements is described in military standard 454.
1.3 Capabilities
The following are the major capabilities that the language provides along with the features that
differentiate it from other hardware description languages.
• The language can be used as an exchange medium between chip vendors and CAD tool
users. Different chip vendors can provide VHDL descriptions of their components to
system designers. CAD tool users can use it to capture the behavior of the design at a
high level of abstraction for functional simulation.
• The language can also be used as a communication medium between different CAD and
CAE tools, for example, a schematic capture program may be used to generate a VHDL
description for the design which can be used as an input to a simulation program.
• The language supports hierarchy, that is, a digital system can be modeled as a set of
interconnected components; each component, in turn, can be modeled as a set of
interconnected subcomponents.
• The language supportsflexible design methodologies: top-down, bottom-up, or mixed.
• The language is not technology-specific, but is capable of supporting technology-
specific features. It can also support various hardware technologies, for example, you
may define new logic types and new components, you may also specify technology-
specific attributes. By being technology independent, the same behavior model can. be
synthesized into different vendor libraries.
• It supports both synchronous and asynchronous timing models.
• Various digital modeling techniques such as finite-state machine descriptions,
algorithmic descriptions, and boolean equations can be modeled using the language.
• The language is publicly available, human readable, machine readable, and above all, it
is not proprietary.
• It is an IEEE and ANSI standard, and therefore, models described using this language
are portable. The government also has a strong interest in maintaining this as a standard
so that re-procurement and second-sourcing may become easier.
• The language supports three basic different description styles: structural, dataflow, and
behavioral. A design may also be expressed in any combination of these three
descriptive styles.
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• It supports a wide range, of abstraction levels ranging from abstract behavioral

descriptions to very precise gate-level descriptions. It does not, however, support
modeling at or below the transistor level. It allows a design to be captured at a mixed
level using a single coherent language.
• Arbitrarily large designs can be. modeled using the language and there are no
limitations that are imposed by the language on the size of a design.
• The language has elements that make large scale design modeling easier, for example,
components, functions, procedures, and packages.
• There is no need to learn a different language for simulation control. Test benches can
be written using the same language to test other VHDL models.
• Nominal propagation delays, min-max delays, setup and hold timing, timing
constraints, and spike detection can all be described very naturally in this language.
• The use of generics and attributes in the models facilitate back-annotation of static
information such as timing or placement information.
• Generics and attributes are also useful in describing parameterized designs.
• A model can not only describe the functionality of a design, but can also contain
information about the design itself 'in terms of user-defined attributes, for example,
total area and speed.
• A common language can be used to describe library components from different
vendors. Tools that understand VHDL models will have no difficulty in reading models
from a variety of vendors since the language is a standard.
• Models written in this language can be verified by simulation since precise simulation
semantics are defined for each language construct.
• Behavioral models that conform to a certain synthesis description style are capable of
being synthesized to gate-level descriptions.
• The capability of defining new data types provides the power to describe and simulate a
new design technique at a very high level of abstraction without any concern about the
implementation details.
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2. A Tutorial
2.1 Basic Terminology
VHDL is a hardware description language that can be used to model a digital system. The digital
system can be as simple as a logic gate or as complex as a complete electronic system. A
hardware abstraction of this digital system is called an entity in this text. An entity X, when used
in another entity Y, becomes a component for the entity Y. Therefore, a component is also an
entity, depending on the level at which you are trying to model.
To describe an entity, VHDL provides five different types of primary constructs, called
design units.
They are
1. Entity declaration
2. Architecture body
3. Configuration declaration
4. Package declaration
5. Package body
2.1.1 Entity
We elaborated top-down design methodology in chapter one and stated that the main design idea
has to be broken down into smaller modules. These abstract blocks are called components that can
be designed individually and they can be put together using bottom-up method and constitute the
main design. In this case each one of the blocks can be treated as an entity. An entity is a black
box with declaration of inputs and output
which defines a full adder with three input ports and two output ports. Each design must
have at least one entity and one corresponding architecture that specifies the external
specification of the design. Each entity has a names assigned to it along with a port list.
Each port has a name, direction and type.
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2.1.2 Architecture
An architecture statement defines the structure or description of a design and is bounded
with an entity. The syntax for VHDL architecture is as follows. As you see the
architecture is bounded with the entity that was defined before. VHDL allows an entity to
have multiple architectures. Since architecture describes what is inside an entity, it can be
written in different ways by different designers. Some prefer dataflow while the others
may prefer the structural method for a design. Architecture has two parts. The first part is
between the keywords architecture and begin which is the declaration part. In this section
you can define the interconnection signals, other components referenced by this
architecture, or constants. The second part starts after the keyword begin that includes the
statements and assignments and structure of the design. The following piece of code
describes the architecture of the above entity.
2.1.3 Configuration
In the previous section we stated that an entity can have multiple architectures. The configuration
statement specifies which entity is to be bounded to which architecture. This allows you to switch
between different architectures for an entity in a design. The following is an example of a
configuration statement. In this example we bound the above pair of entity-architecture.
2.1.4 Package
It could be very tedious to repeat the declarations every time you need them. As a programmer
you want to be able to use a piece of code over and over once you write it to save time and
resources. Package provides this flexibility in VHDL and is used to store frequently used
declarations among different design units. Package may be used in its simplest form to declare
components, constants, global variables, or global functions which can be made visible not only
for the current design but also for any other design units that reference the package. A package can
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be accessed using the use statement, which will be explained later. A package can be identified
using the keyword package. The following is an example of a package.
2.1.5 Package Body

A package body is always associated with package definition with the same name. If a package
includes a function or a deferred constant a package body is needed to define the value of the
constant or definition of the function. The following example gives the details of the function that
was in the above package
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2.2 Levels of Abstraction

There was no specific technological knowledge such as advanced electronics or mechanical
design or soldering skills was required for this course except a programming background. The
intent was not having the student reinvent the basics of robotics but rather it was enabling the
students to come up with methodological approach and differentiate the levels of abstractions in
design flow. Student is supposed to insulate himself/herself from the details of the implementation
and think about the project implementation at higher level. All the basics were provided to the
students in this case. VHDL supports different styles of design description. These styles vary in a
sense that how they relate to the underlying hardware. When we speak of the different styles of
VHDL, we are actually talking about the levels of abstraction. Figure 2-1 shows four possible
levels of Bahavioral Dataflow (RTL) Structural (Logic or Gate -level) Layout Figure 2-1
Abstraction Levels in VHDL language abstractions: behavioral, RTL (or Dataflow), structural
(sometimes called gate-level or logic) and layout.
As an example of these four levels of abstraction, consider a simple BCD counter. It is possible to
describe the counter in a number of ways. At the lowest level of abstraction (layout level), we
could use the layout of transistors and build gates and flip flops out of them and connect them so
as logic function can be satisfied. At the next level (logic or structural) counter can be specified as
a sequence of predefined logic gates and flip-flips to form the complete circuit. To describe this
same circuit at a dataflow or RTL level of abstraction, we might describe the combinational logic
portion of the counter (its decoding portion) using higher-level Boolean logic functions and then
feed the output of that logic into a set of registers. At the behavioral level of abstraction, regardless
of target technology we just define the behavior of the system using human language. In this case
this could be as “This counter counts from 0 to 9 and rolls over after it reaches the highest count
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2.2.1 Behavioral Modeling

Behavioral modeling is the highest level of abstraction in VHDL. In this method, the behavior
of the system should be defined with respect to time. The operation of time is the critical point
in behavioral modeling and it distinguishes this type from the others. There are multiple of ways
to represent the time in VHDL that will be discussed in details later. The concept of time could
be defined exactly with the actual delays between the events or in the order of the sequential
operations. After you write the VHDL code in behavioral, it has to be synthesized to create the
netlist. Sytnehsis is the process of translating an abstract concept (behavioral code in this case)
into a less abstract form (a netlist in this case). A netlist is the translation of your code in terms
of gates so the implementation tool can understand it. It is unlikely that the synthesis tool can
understand your behavioral code and create the same behavior that you have defined. Today’s
synthesis tools ignore timing details of the design and the delays will depend on the target
device technology. A behavioral code is very similar to a software program like C++ in which
smaller programs and instructions operate sequentially and talk to one another. In software
programming the execution platform (which is the compiler) is located in CPU while in VHDL
it is the simulation or synthesized hardware that can execute your code. A testbench with all
timing equations is an example of behavioral code that can be written in combination with your
code to verify the functionality. Testbenches can be understood by simulation tools and not the
synthesis tools.
2.2.2 Dataflow Modeling

The highest level of abstraction accepted by the synthesis tools available in today’s marketplace
is dataflow level. In dataflow modeling you define your circuit in terms of how data moves
within the system. Registers are the main components in digital systems and the behavior of the
system can be described as data flow among the registers. Normally we can be very specific in a
design at where the registers are located but the combinatorial part of the design can be
described at relatively high level and the synthesis tool will figure out how the details of the
implementation would be. Sometimes this type of implementation of modeling digital systems is
called RTL or Register Transfer Logic. We stated that the behavioral code should be verified by
simulation but it is not synthesizable. After the simulation, design must be redefined until it can
be understandable by the synthesis tools. Most of the times hardware designers prefer to write
the code at this level of abstraction since this is closer to the actual hardware components such
as registers and gates.
2.2.3 Structural Modeling

In structural modeling the smaller components connect together to form the larger components
and eventually the whole circuit. Designer might use this type of modeling in a very low level
description of a circuit such as gates and flip flops or in a high level description such as block
diagrams. Designer can use the latter case in order to break down a complex block into
manageable parts. Either way, some internal signals are needed to provide the interconnection
between the components. Using this method you can drastically simplify a design using a top-
down design methodology. In structural modeling, lower level modules are components that get
connected to form higher level modules. In fact structural modeling represents the design in the
form of a netlist of connected components. It is very important that every module is declared
before it is used. Declaration is identified using component declaration and connecting the
components is done using component instantiation.
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2.2.3.1 Component Declaration

A component declaration declares design entity interface that will be used later to form a
hierarchical design. Following is an example of a component declaration
2.2.3.2 Component Instantiation A component instantiation is a statement that

references lower-level component in the design, in essence creating unique copy (or instance) of
that component. A component instantiation statement is a concurrent statement, so there is no
significance to the order in which components are referenced. The concept of concurrent and
sequential statements will be covered in details in later chapters. You must, however, declare any
components that you reference in either the declarative area of the architecture (before the begin
statement) or in an external package that is visible to the architecture. Following is an example of
a component instantiation that makes an instance of the half adder that was declared in previous
section. A good analogy for component instantiation would be putting an electronic IC into a
socket
2.3 Libraries in VHDL

A library, in general, is a collection of compiled design units that is being used to manage
designs. The keyword library identifies a library in VHDL followed by the logical library name. A
library becomes visible when a library statement is used. Following examples show how to declare
libraries.
library IEEE;
declares IEEE library which is a library that includes conversion functions, useful types, etc.
library std_logic_1164;
declares IEEE 1164 standard library
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library LSI_1100;
declares LSI ASIC library
2.3.1 Design Library

A design library is a storage area for previously compiled design units. A design library is
completely implementation dependent, meaning that it depends on synthesis tool. Typically, you
specify the areas to store frequently used design units such as packages and package bodies for
future reference. If you don’t do so, the design units will be compiled into a default library called
work. In case if you work with simple designs and individual source files, the library is accessible
using the use statements which will be explained in the next section otherwise you should have a
good understanding of how libraries are managed in the design process. Using named libraries
increases productivity in design flow. The point is not to use the work library in different source
files that are in different locations. All design units include std and work libraries by default but
the contents of the work libraries might be different since they are results of different
implementations. Most of the synthesis and simulation tools follow the standard definition in
VHDL that defines the work library to be only those design units that are included in the source
file currently being compiled.
2.3.2 Use Statement

To use a design unit from within a library or other design units, a use statement must be used
specifying the design unit. A use statement makes the referenced design unit visible to the
working environment. A use statement starts with the keyword use followed by the list of the
design units. The use statement is flexible and it can be used in different ways. You can address
the individual components in a library or all of the items available in the library. Following
examples show how to use libraries. The library statement described in the previous section is
used to load a library so that its contents are available when compiling a source file. However, the
library statement does not actually make the contents of the specified library visible to design units
in the current source file. Visibility is created when you specify one or more use statements prior
to the design units requiring access to items in the library. A good practice is to place library
statement in the beginning of the source file followed by the use statement whenever a visibility to
a specific item or library or package is needed and also avoid using work library for shared
packaes.
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2.4 Putting It Together!!

VHDL Skeleton Now that you understand the basics of VHDL, let’s put it together and write a
code for a complete design of a 4 bit full adder from scratch. For the sake of example let’s build
the 4 bit adder based on the full adder design in section 2.1.1. In this example the full adder design
is considered as a component that is instantiated in the 4 bit adder design. Here is the complete
VHDL code:
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The code starts with necessary library declarations and is followed by entity and architecture
declarations. The entity part defines the design as a black box with inputs and outputs. The
architecture part defines the interrelation of these inputs and outputs. In fact architecture specifies
what is inside the black box. The architecture part is divided into two sections: declaration and
instantiation part. Declaration part is between the keywords architecture and begin. Here, all the
signals, components, constants, variables, … must be declared. In our example, carry_int signal is
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defined to handle interconnection between the single bit full adders. Also the single bit full adder
is defined as a component. The instantiation part starts after the keyword begin. Four instances of
the full adder are constructed and using the port map statements they are connected together. Note
that full adder instantiations are concurrent statements and order does not matter. These are the
statements that are executed in parallel and operate asynchronously. Concurrent statements are
versus sequential statements that are executed sequentially upon the flow of the program. We will
see this concept in near future.
2.5 Simulation
Once the model description is successfully compiled into one or more design libraries, the next
step in the validation process is simulation. For a hierarchical entity to be simulated, all of its
lowest level components must be described at the behavioral level.
A simulation can be performed on either one of the following:
• Anentity declaration and an architecture body pair,
• A configuration.
Preceding the actual simulation are two major steps:
1. Elaboration phase: In this phase, the hierarchy of the entity is expanded and
linked, components are bound to entities in a library and the top-level entity is
built as a network of behavioral models that is ready to be simulated. Also,
storage is allocated for all data objects (signals, variables, and constants)
declared in the design units. Initial values are also assigned to these objects.
2. Initialization phase: The effective values for all explicitly declared signals are
computed, implicit signals (discussed in later chapters) are assigned values,
processes are executed once until they suspend, and simulation time is reset to
0 ns.
Simulation commences by advancing time to that of the next event. Values that are
scheduled to be assigned to signals at this time are assigned. Each process that has a signal in its
sensitivity list whose value just changed, is executed until it suspends. Simulation stops when a
user-specified time limit is reached, or when an assertion violation occurs, depending on the
implementation of the VHDL system (assertion statements are discussed in Chap. 4), or when
the maximum time as defined by the language is reached.
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3. Basic Language Elements

This section describes the basic elements of the language. These include data objects that store
values of a given type, literals that represent constant values, and operators that operate on data
objects. Every data object belongs to a specific type. The various categories of types and the
syntax for specifying user-defined types are discussed here.
It is important to understand the notion of data types and objects since VHDL is a
strongly-typed language. This means that operations and assignments are legal in the language
only if the types of the operands and the result match according to a set of rules; it does not
allow objects and literals of different types to be mixed freely in expressions. Examples of
illegal operations are adding a real value to an integer value, and assigning a boolean value to an
object of type BIT. It is, therefore, important to understand what types are and how they can be
correctly used in the language.
3.1. Lexical Elements

3.1.1. Comments
Comments in VHDL start with two adjacent hyphens (‘--’) and extend to the end of the line. They
have no part in the meaning of a VHDL description
3.1.2. Identifiers
Identifiers in VHDL are used as reserved words and as programmer defined names. They must
conform to the rule:
identifier ::= letter { [ underline ] letter_or_digit }
Note that case of letters is not considered significant, so the identifiers cat and Cat are the same.
Underline characters in identifiers are significant, so This_Name and ThisName are different
identifiers.
3.1.3. Numbers
Literal numbers may be expressed either in decimal or in a base between two and sixteen. If the
literal includes a point, it represents a real number, otherwise it represents an integer. Decimal
literals are defined by:
decimal_literal ::= integer [ . integer ] [ exponent ]
integer ::= digit { [ underline ] digit }
exponent ::= E [ + ] integer | E - integer
Based literal numbers are defined by:
based_literal ::= base # based_integer [ . based_integer ] # [ exponent ] base

::= integer based_integer ::= extended_digit { [ underline ] extended_digit }
3.1.4. Characters
Literal characters are formed by enclosing an ASCII character in single-quote marks. For example:
'A' '*' ''' ' '
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3.1.5. Strings
Literal strings of characters are formed by enclosing the characters in double-quote marks. To
include a double-quote mark itself in a string, a pair of double-quote marks must be put together.
A string can be used as a value for an object which is an array of characters. Examples of strings:
"A string" "" -- empty string "A string in a string: ""A string"". " -- contains quote marks
3.1.6. Bit Strings

VHDL provides a convenient way of specifying literal values for arrays of type bit ('0's and '1's,
see Section 2.2.5). The syntax is:
bit_string_literal ::= base_specifier " bit_value
" base_specifier ::= B | O | X
bit_value ::= extended_digit { [ underline ] extended_digit }
Base specifier B stands for binary, O for octal and X for hexadecimal.
Some examples:
B"1010110" -- length is 7
O"126" -- length is 9, equivalent to B"001_010_110"
X"56" -- length is 8, equivalent to B"0101_0110
3.2 Data Types and Objects

VHDL provides a number of basic, or scalar, types, and a means of forming composite types. The
scalar types include numbers, physical quantities, and enumerations (including enumerations of
characters), and there are a number of standard predefined basic types. The composite types
provided are arrays and records. VHDL also provides access types (pointers) and files, although
these will not be fully described in this booklet. A data type can be defined by a type declaration:
:
full_type_declaration ::= type identifier is type_definition ;
type_definition ::=
scalar_type_definition
| composite_type_definition
| access_type_definition
| file_type_definition
scalar_type_definition ::= enumeration_type_definition |
integer_type_definition | floating_type_definition | physical_type_definition
composite_type_definition ::=
array_type_definition
| record_type_definition
3.2.1. Integer Types
An integer type is a range of integer values within a specified range.

The syntax for specifying integer types is:
integer_type_definition ::= range_constraint
range_constraint ::= range range
range ::= simple_expression direction simple_expression

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direction ::= to | downto
The expressions that specify the range must of course evaluate to integer numbers. Types declared
with the keyword to are called ascending ranges, and those declared with the keyword downto are
called descending ranges. The VHDL standard allows an implementation to restrict the range, but
requires that it must at least allow the range –2147483647 to +2147483647.
Some examples of integer type declarations:
type byte_int is range 0 to 255;
type signed_word_int is range –32768 to 32767; type
bit_index is range 31 downto 0;
There is a predefined integer type called integer. The range of this type is implementation
defined, though it is guaranteed to include –2147483647 to +2147483647.
3.2.2. Physical Types

A physical type is a numeric type for representing some physical quantity, such as mass, length,
time or voltage. The declaration of a physical type includes the specification of a base unit, and
possibly a number of secondary units, being multiples of the base unit. The syntax for declaring
physical types is:
physical_type_definition ::=
range_constraint units
base_unit_declaration
{ secondary_unit_declaration } end units
base_unit_declaration ::= identifier ; secondary_unit_declaration ::=
identifier = physical_literal ; physical_literal ::= [ abstract_literal ]
unit_name
Some examples of physical type declarations:

type length is range 0 to 1E9 units
um; mm = 1000 um; cm = 10
mm; m = 1000 mm; in = 25.4
mm; ft = 12 in; yd = 3 ft; rod =
198 in; chain = 22 yd;
furlong = 10 chain;
end units;
type resistance is range 0 to 1E8 units
ohms; kohms = 1000 ohms;
Mohms = 1E6 ohms; end
units;
The predefined physical type time is important in VHDL, as it is used extensively to specify
delays in simulations. Its definition is:
type time is range implementation_defined units
fs; ps = 1000 fs; ns
= 1000 ps; us =
1000 ns; ms = 1000
us; sec = 1000 ms;
min = 60 sec;
hr = 60 min;
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end units;
To write a value of some physical type, you write the number followed by the unit. For example:
10 mm 1 rod 1200 ohm 23 ns
3.2.3. Floating Point Types

A floating point type is a discrete approximation to the set of real numbers in a specified range.
The precision of the approximation is not defined by the VHDL language standard, but must be at
least six decimal digits. The range must include at least –1E38 to +1E38. A floating point type is
declared using the syntax:
floating_type_definition := range_constraint Some examples
are:
type signal_level is range –10.00 to +10.00; type
probability is range 0.0 to 1.0;
There is a predefined floating point type called real. The range of this type is implementation
defined, though it is guaranteed to include –1E38 to +1E38.
3.2.4. Enumeration Types

An enumeration type is an ordered set of identifiers or characters. The identifiers and characters
within a single enumeration type must be distinct, however they may be reused in several different
enumeration types.
The syntax for declaring an enumeration type is:
enumeration_type_definition ::= ( enumeration_literal { , enumeration_literal } )
enumeration_literal ::= identifier | character_literal
Some examples are:

type logic_level is (unknown, low, undriven, high);
type alu_function is (disable, pass, add, subtract, multiply, divide); type
octal_digit is ('0', '1', '2', '3', '4', '5', '6', '7');
There are a number of predefined enumeration types, defined as follows:
type severity_level is (note, warning, error, failure);
type boolean is (false, true); type bit is ('0', '1');
type character is (
NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,
BS, HT, LF, VT, FF, CR, SO, SI,
DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,
CAN, EM, SUB, ESC, FSP, GSP, RSP, USP,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
'X', 'Y', 'Z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
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'p', 'q', 'r', 's', 't', 'u', 'v', 'w',

'x', 'y', 'z', '{', '|', '}', '~', DEL);
Note that type character is an example of an enumeration type containing a mixture of identifiers
and characters. Also, the characters '0' and '1' are members of both bit and character . Where '0' or
'1' occur in a program, the context will be used to determine which type is being used.
3.2.5. Arrays
An array in VHDL is an indexed collection of elements all of the same type. Arrays may be
one-dimensional (with one index) or multidimensional (with a number of indices). In addition, an
array type may be constrained, in which the bounds for an index are established when the type is
defined, or unconstrained, in which the bounds are established subsequently.
The syntax for declaring an array type is:
array_type_definition ::= unconstrained_array_definition |
constrained_array_definition
unconstrained_array_definition ::= array ( index_subtype_definition { ,
index_subtype_definition } ) of elem ent_subtype_indication
constrained_array_definition ::= array index_constraint of elem
ent_subtype_indication
index_subtype_definition ::= type_mark range <> index_constraint
::= ( discrete_range { , discrete_range } ) discrete_range ::=
discrete_subtype_indication | range
Subtypes, referred to in this syntax specification, will be discussed in detail in Section2.2.7.

Some examples of constrained array type declarations:
type word is array (31 downto 0) of bit; type
memory is array (address) of word; type transform
is array (1 to 4, 1 to 4) of real;
type register_bank is array (byte range 0 to 132) of integer;
An example of an unconstrained array type declaration:
type vector is array (integer range <>) of real;
The symbol ‘<>’ (called a box) can be thought of as a place-holder for the index range, which will
be filled in later when the array type is used. For example, an object might be declared to be a
vector of 20 elements by giving its type as:
vector(1 to 20)
There are two predefined array types, both of which are unconstrained.
They are defined as:
type string is array (positive range <>) of character; type
bit_vector is array (natural range <>) of bit;
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The types positive and natural are subtypes of integer, defined in Section2.2.7 below. The type
bit_vector is particularly useful in modeling binary coded representations of values in simulations
of digital systems.
An element of an array object can referred to by indexing the name of the object. For example,
suppose a and b are one- and two-dimensional array objects respectively. Then the indexed names
a(1) and b(1, 1) refer to elements of these arrays. Furthermore, a contiguous slice of a
onedimensional array can be referred to by using a range as an index. For example a(8 to 15) is an
eight-element array which is part of the array a.
Sometimes you may need to write a literal value of an array type. This can be done using an
array aggregate, which is a list of element values. Suppose we have an array type declared as:
type a is array (1 to 4) of character;
and we want to write a value of this type containing the elements 'f', 'o', 'o', 'd' in that order. We could
write an aggregate with positional association as follows:
('f', 'o', 'o', 'd')
in which the elements are listed in the order of the index range, starting with the left bound of the
range. Alternatively, we could write an aggregate with nam ed association:
(1 => 'f', 3 => 'o', 4 => 'd', 2 => 'o')
In this case, the index for each element is explicitly given, so the elements can be in any order.
Positional and named association can be mixed within an aggregate, provided all the positional
associations come first. Also, the word others can be used in place of an index in a named
association, indicating a value to be used for all elements not explicitly mentioned. For example, the
same value as above could be written as:
('f', 4 => 'd', others => 'o')
3.2.6. Records
VHDL provides basic facilities for records, which are collections of named elements of possibly
different types. The syntax for declaring record types is:
record_type_definition ::= record
element_declaration
{ element_declaration } end
record
element_declaration ::= identifier_list : element_subtype_definition ;
identifier_list ::= identifier { , identifier ) element_subtype_definition ::=
subtype_indication An example record type declaration:
type instruction is record op_code :
processor_op; address_mode :
mode;
operand1, operand2: integer range 0 to 15;
end record;
When you need to refer to a field of a record object, you use a selected name. For example,
suppose that r is a record object containing a field called f. Then the name r.f refers to that field.
As for arrays, aggregates can be used to write literal values for records. Both positional and
named association can be used, and the same rules apply, with record field names being used in place
of array index names.
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3.2.7. Subtypes
The use of a subtype allows the values taken on by an object to be restricted or constrained subset
of some base type. The syntax for declaring a subtype is:
subtype_declaration ::= subtype identifier is subtype_indication ; subtype_indication ::=
[ resolution_function_name ] type_mark [ constraint ] type_mark ::= type_name |
subtype_name constraint ::= range_constraint | index_constraint
There are two cases of subtypes. Firstly a subtype may constrain values from a scalar type to be
within a specified range (a range constraint). For example:
subtype pin_count is integer range 0 to 400; subtype digits is
character range '0' to '9';
Secondly, a subtype may constrain an otherwise unconstrained array type by specifying bounds
for the indices. For example:
subtype id is string(1 to 20); subtype word is
bit_vector(31 downto 0);
There are two predefined numeric subtypes, defined as:
subtype natural is integer range 0 to highest_integer subtype positive
is integer range 1 to highest_integer
3.2.8. Object Declarations

An object is a named item in a VHDL description which has a value of a specified type. There
are three classes of objects: constants, variables and signals. Only the first two will be discusses in
this section; signals will be covered in Section3.2.1. Declaration and use of constants and variables is
very much like their use in programming languages.
A constant is an object which is initialised to a specified value when it is created, and which may
not be subsequently modified. The syntax of a constant declaration is:
constant_declaration ::= constant identifier_list : subtype_indication [ :=
expression ] ;
Constant declarations with the initialising expression missing are called deferred constants, and may
only appear in package declarations (see Section2.5.3). The initial value must be given in the
corresponding package body. Some examples:
constant e : real := 2.71828;
constant delay : Time := 5 ns;
constant max_size : natural;
A variable is an object whose value may be changed after it is created.
The syntax for declaring variables is:
variable_declaration ::= variable identifier_list : subtype_indication [ :=
expression ] ;
The initial value expression, if present, is evaluated and assigned to the variable when it is created. If
the expression is absent, a default value is assigned when the variable is created. The default value
for scalar types is the leftmost value for the type, that is the first in the list of an enumeration type, the
lowest in an ascending range, or the highest in a descending range. If the variable is a composite
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type, the default value is the composition of the default values for each element, based on the element
types.
Some examples of variable declarations:
variable count : natural := 0; variable trace
: trace_array;
Assuming the type trace_array is an array of boolean, then the initial value of the variable trace is an
array with all elements having the value false.
Given an existing object, it is possible to give an alternate name to the object or part of it. This is
done using and alias declaration. The syntax is:
alias_declaration ::= alias identifier : subtype_indication is name ; A reference to an
alias is interpreted as a reference to the object or part corresponding to the alias. For example:
variable instr : bit_vector(31 downto 0);
alias op_code : bit_vector(7 downto 0) is instr(31 downto 24);
declares the name op_code to be an alias for the left-most eight bits of instr.
3.3.Expressions and Operators
Expressions in VHDL are much like expressions in other programming languages. An expression
is a formula combining primaries with operators. Primaries include names of objects, literals,
function calls and parenthesized expressions. Operators are listed in Table 2-1 in order of decreasing
precedence.
The logical operators and, or, nand, nor, xor and not operate on values of type bit or boolean, and
also on one-dimensional arrays of these types. For array operands, the operation is applied between
corresponding elements of each array, yielding an array of the same length as the result. For bit and
Highest precedence: ** abs not
* / mod rem
+ (sign) – (sign)
+ – &
= /= < <= > >=
Lowest precedence: and or nand nor xor
Table 7-1. Operators and precedence.
boolean operands, and, or, nand, and nor are ‘short-circuit’ operators, that is they only evaluate their
right operand if the left operand does not determine the result. So and and nand only evaluate the
right operand if the left operand is true or '1', and or and nor only evaluate the right operand if the
left operand is false or '0'.
The relational operators =, /=, <, <=, > and >= must have both operands of the same type, and
yield boolean results. The equality operators (= and /=) can have operands of any type. For
composite types, two values are equal if all of their corresponding elements are equal. The remaining
operators must have operands which are scalar types or one-dimensional arrays of discrete types.
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The sign operators (+ and –) and the addition (+) and subtraction (–) operators have their usual
meaning on numeric operands. The concatenation operator (&) operates on one-dimensional arrays
to form a new array with the contents of the right operand following the contents of the left operand.
It can also concatenate a single new element to an array, or two individual elements to form an array.
The concatenation operator is most commonly used with strings.
The multiplication (*) and division (/) operators work on integer, floating point and physical types
types. The modulus (mod) and remainder (rem) operators only work on integer types. The absolute
value (abs) operator works on any numeric type. Finally, the exponentiation (**) operator can have
an integer or floating point left operand, but must have an integer right operand. A negative right
operand is only allowed if the left operand is a floating point number.
3.4. Sequential Statements

VHDL contains a number of facilities for modifying the state of objects and controlling the flow
of execution of models. These are discussed in this section.
3.4.1. Variable Assignment

As in other programming languages, a variable is given a new value using an assignment
statement. The syntax is:
variable_assignment_statement ::= target := expression ; target ::=
name | aggregate
In the simplest case, the target of the assignment is an object name, and the value of the expression
is given to the named object. The object and the value must have the same base type.
If the target of the assignment is an aggregate, then the elements listed must be object names,
and the value of the expression must be a composite value of the same type as the aggregate.
Firstly, all the names in the aggregate are evaluated, then the expression is evaluated, and lastly the
components of the expression value are assigned to the named variables. This is effectively a
parallel assignment. For example, if a variable r is a record with two fields a and b, then they could
be exchanged by writing
(a => r.b, b => r.a) := r
(Note that this is an example to illustrate how such an assignment works; it is not an example of good
programming practice!)
3.4.2. If Statement
The if statement allows selection of statements to execute depending on one or more conditions.
The syntax is:
if_statement ::= if condition then
sequence_of_statements
{ elsif condition then sequence_of_statements }
[ else
sequence_of_statements ]
end if ;
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The conditions are expressions resulting in boolean values. The conditions are evaluated
successively until one found that yields the value true. In that case the corresponding statement list is
executed. Otherwise, if the else clause is present, its statement list is executed.
3.4.3. Case Statement

The case statement allows selection of statements to execute depending on the value of a selection
expression. The syntax is:
case_statement ::= case expression is
case_statement_alternative
{ case_statement_alternative } end case ;
case_statement_alternative ::= when
choices =>
sequence_of_statements
choices ::= choice { | choice }
choice ::= simple_expression
| discrete_range
| elem ent_simple_name
| others
The selection expression must result in either a discrete type, or a onedimensional array of
characters. The alternative whose choice list includes the value of the expression is selected and the
statement list executed. Note that all the choices must be distinct, that is, no value may be duplicated.
Furthermore, all values must be represented in the choice lists, or the special choice others must be
included as the last alternative. If no choice list includes the value of the expression, the others
alternative is selected. If the expression results in an array, then the choices may be strings or bit
strings.
Some examples of case statements:
case element_colour of when red =>
statements for red;
when green | blue => statements for
green or blue;
when orange to turquoise => statements for
these colours;
end case; case opcode of when X"00" =>
perform_add; when X"01" => perform_subtract;
when others => signal_illegal_opcode;
end case;
3.4.4. Loop Statements

VHDL has a basic loop statement, which can be augmented to form the usual while and for loops
seen in other programming languages. The syntax of the loop statement is:
loop_statement ::=
[ loop_label : ]
[ iteration_scheme ] loop
sequence_of_statements end loop [
loop_label ] ;
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iteration_scheme ::= while

condition
| for loop_parameter_specification
parameter_specification ::= identifier in
discrete_range
If the iteration scheme is omitted, we get a loop which will repeat the enclosed statements
indefinitely. An example of such a basic loop is:
loop do_something;
end loop;
The while iteration scheme allows a test condition to be evaluated before each iteration. The
iteration only proceeds if the test evaluates to true. If the test is false, the loop statement terminates.
An example:
while index < length and str(index) /= ' ' loop index
:= index + 1; end loop;
The for iteration scheme allows a specified number of iterations. The loop parameter
specification declares an object which takes on successive values from the given range for each
iteration of the loop. Within the statements enclosed in the loop, the object is treated as a constant,
and so may not be assigned to. The object does not exist beyond execution of the loop statement.
An example:
for item in 1 to last_item loop
table(item) := 0; end loop;
There are two additional statements which can be used inside a loop to modify the basic pattern
of iteration. The ‘next’ statement terminates execution of the current iteration and starts the
subsequent iteration. The ‘exit’ statement terminates execution of the current iteration and
terminates the loop. The syntax of these statements is:
next_statement ::= next [ loop_label ] [ when condition ] ;
exit_statement ::= exit [ loop_label ] [ when condition ] ;
If the loop label is omitted, the statement applies to the inner-most enclosing loop, otherwise it applies
to the named loop. If the when clause is present but the condition is false, the iteration continues
normally. Some examples:
for i in 1 to max_str_len loop a(i) :=
buf(i);
exit when buf(i) = NUL;
end loop; outer_loop : loop inner_loop : loop
do_something; next outer_loop when temp =
0; do_something_else;
end loop inner_loop;
end loop outer_loop;
3.4.5. Null Statement

The null statement has no effect. It may be used to explicitly show that no action is required in
certain cases. It is most often used in case statements, where all possible values of the selection
expression must be listed as choices, but for some choices no action is required. For example:
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case controller_command is when forward =>

engage_motor_forward; when reverse =>
engage_motor_reverse;
when idle => null;
end case;
3.4.6. Assertions
An assertion statement is used to verify a specified condition and to report if the condition is
violated. The syntax is:
assertion_statement ::= assert
condition
[ report expression ]
[ severity expression ] ;
If the report clause is present, the result of the expression must be a string. This is a message which
will be reported if the condition is false. If it is omitted, the default message is "Assertion violation".
If the severity clause is present the expression must be of the type severity_level. If it is omitted, the
default is error. A simulator may terminate execution if an assertion violation occurs and the severity
value is greater than some implementation dependent threshold. Usually the threshold will be under
user control.
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Software Overview
The ISE® software controls all aspects of the design flow. Through the Project Navigator interface,
you can access all of the design entry and design implementation tools. You can also access the files
and documents associated with your project.
Project Navigator Interface

By default, the Project Navigator interface is divided into four panel sub-windows, as seen in Figure
2-1. On the top left are the Start, Design, Files, and Libraries panels, which include display and access
to the source files in the project as well as access to running processes for the currently selected
source
Design Panel
The Design panel provides access to the View, Hierarchy, and Processes panes.
View Pane
The View pane radio buttons enable you to view the source modules associated with the
Implementation or Simulation Design View in the Hierarchy pane. If you select Simulation, you must
select a simulation phase from the drop-down list.
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Hierarchy Pane
The Hierarchy pane displays the project name, the target device, user documents, and design source
files associated with the selected Design View. The View pane at the top of the Design panel allows
you to view only those source files associated with the selected Design View, such as Implementation
or Simulation. Each file in the Hierarchy pane has an associated icon. The icon indicates the file type
(HDL file, schematic, core, or text file, for example). For a complete list of possible source
types and their associated icons, see the “Source File Types” topic in the ISE Help. From Project
Navigator, select Help > Help Topics to view the ISE Help.
If a file contains lower levels of hierarchy, the icon has a plus symbol (+) to the left of the name. You
can expand the hierarchy by clicking the plus symbol (+). You can open a file for editing by double-
clicking on the filename.
Processes Pane
The Processes pane is context sensitive, and it changes based upon the source type selected in the
Sources pane and the top-level source in your project. From the Processes pane, you can run the
functions necessary to define, run, and analyze your design. The Processes pane provides access to the
following functions:
• Design Summary/Reports
Provides access to design reports, messages, and summary of results data. Message filtering can also be
performed.
• Design Utilities
Provides access to symbol generation, instantiation templates, viewing command line history, and
simulation library compilation.
• User Constraints
Provides access to editing location and timing constraints.
• Synthesis
Provides access to Check Syntax, Synthesis, View RTL or Technology Schematic, and synthesis
reports. Available processes vary depending on the synthesis tools you use.
• Implement Design
Provides access to implementation tools and post-implementation analysis tools.
• Generate Programming File
Provides access to bitstream generation.
• Configure Target Device
Provides access to configuration tools for creating programming files and programming the device.
The Processes pane incorporates dependency management technology. The tools keep track of which
processes have been run and which processes need to be run. Graphical status indicators display the
state of the flow at any given time. When you select a process in the flow, the software automatically
runs the processes necessary to get to the desired step. For example, when you run the Implement Design
process, Project Navigator also runs the Synthesis process because implementation is dependent on up-
to-date synthesis results.
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Libraries Panel
The Libraries panel enables you to manage HDL libraries and their associated HDL source files. You
can create, view, and edit libraries and their associated sources.
Console Panel
The Console provides all standard output from processes run from Project Navigator. It displays
errors, warnings, and information messages. Errors are signified by a red X next to the message; while
warnings have a yellow exclamation mark (!).
Errors Panel
The Errors panel displays only error messages. Other console messages are filtered out.
Warnings Panel
The Warnings panel displays only warning messages. Other console messages are filtered out.
Error Navigation to Source

You can navigate from a synthesis error or warning message in the Console, Errors, or Warnings panel
to the location of the error in a source HDL file. To do so, select the error or warning message, right-
click the mouse, and select Go to Source from the right-click menu.The HDL source file opens, and
the cursor moves to the line with the error.
Error Navigation to Answer Record

You can navigate from an error or warning message in the Console, Errors, or Warnings panel to
relevant Answer Records on the Suppor page of the Xilinx® website. To navigate to the Answer
Record, select the error or warning message, right-click the mouse, and select Search for Answer
Record from the right-click menu. The default Web browser opens and displays all Answer Records
applicable to this message.
Workspace
The Workspace is where design editors, viewers, and analysis tools open. These include ISE Text
Editor, Schematic Editor, Constraint Editor, Design Summary/Report Viewer, RTL and Technology
Viewers, and Timing Analyzer.
Other tools such as the PlanAhead™ software for I/O planning and floorplanning, ISim, third-party
text editors, XPower Analyzer, and iMPACT open in separate windows outside the main Project
Navigator environment when invoked.
Design Summary/Report Viewer

The Design Summary provides a summary of key design data as well as access to all of the messages
and detailed reports from the synthesis and implementation tools. The summary lists high-level
information about your project, including overview information, a device utilization summary,
performance data gathered from the Place and Route (PAR) report, constraints information, and
summary information from all reports with links to the individual reports. A link to the System Settings
report provides information on environment variables and tool settings used during the design
implementation.
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Using Project Revision Management Features
Project Navigator enables you to manage your project as follows.
Understanding the ISE Project File

The ISE project file (.xise extension) is an XML file that contains all source-relevant data for the
project as follows:
• ISE software version information
• List of source files contained in the project
• Source settings, including design and process properties The ISE project file does not contain the
following:
• Process status information
• Command history
• Constraints data
Note: A .gise file also exists, which contains generated data, such as process status. You should not
need to directly interact with this file.
The ISE project file includes the following characteristics, which are compatible with source control
environments:
• Contains all of the necessary source settings and input data for the project.
• Can be opened in Project Navigator in a read-only state.
• Only updated or modified if a source-level change is made to the project.
• Can be kept in a directory separate from the generated output directory (working directory).
Note: A source-level change is a change to a property or the addition or removal of a source file.
Changes to the contents of a source file or changes to the state of an implementation run are not
considered source-level changes and do not result in an update to the project file.
Making a Copy of a Project

You can create a copy of a project using File > Copy Project to experiment with different source options
and implementations. Depending on your needs, the design source files for the copied project and their
location can vary as follows:
• Design source files can be left in their existing location, and the copied project points to these files.
• Design source files, including generated files, can be copied and placed in a specified directory.
• Design source files, excluding generated files, can be copied and placed in a specified directory.
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Using the Project Browser

The Project Browser, accessible by selecting File > Project Browser, provides a convenient way to
compare, view, and open projects as follows:
• Compare key characteristics between multiple projects.
• View Design Summary and Reports for a selected project before opening the full project.
• Compare detailed information for two selected projects.
• Open a selected project in the current Project Navigator session.
• Open a selected project in a new Project Navigator session.
Using Project Archives

You can also archive the entire project into a single compressed file. This allows for easier transfer
over email and storage of numerous projects in a limited space.
Creating an Archive
To create an archive, do the following:
1. Select Project > Archive.
2. In the Project Archive dialog box, enter the archive name and location.
3. Click Save.
Note: The archive contains all of the files in the project directory along with project settings. Remote
sources are included in the archive under a folder named remote_sources. For more information, see
the ISE Help.
Restoring an Archive
You cannot restore an archived file directly into Project Navigator. The compressed file can be
extracted with any ZIP utility, and you can then open the extracted file in Project Navigator.
Creating a New Project

To create a new project using the New Project Wizard, do the following:
1. From Project Navigator, select File > New Project.
The New Project Wizard appears.
X-Ref Target - Figure 3-2
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Figure 3-2: New Project Wizard—Create New Project Page
2. In the Location field, browse to c:\xilinx_tutorial or to the directory in which you installed the project.
3. In the Name field, enter wtut_vhd or wtut_ver.
4. Verify that HDL is selected as the Top-Level Source Type, and click Next.
The New Project Wizard—Device Properties page appears.
Figure 3-3: New Project Wizard—Device Properties Page
5. Select the following values in the New Project Wizard—Device Properties page:
• Product Category: All
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• Family: Spartan3A and Spartan3AN

• Device: XC3S700A
• Package: FG484
• Speed: -4
• Synthesis Tool: XST (VHDL/Verilog)
• Simulator: ISim (VHDL/Verilog)
• Preferred Language: VHDL or Verilog depending on preference. This will determine the default
language for all processes that generate HDL files.
Other properties can be left at their default values.
6. Click Next, then Finish to complete the project creation.
Stopping the Tutorial

You may stop the tutorial at any time and save your work by selecting File > Save All.
Design Description
Using the New Source Wizard and ISE Text Editor
In this section, you create a file using the New Source wizard, specifying the name and ports of the
component. The resulting HDL file is then modified in the ISE Text Editor.
To create the source file, do the following:
1. Select Project > New Source.
The New Source Wizard opens in which you specify the type of source you want to create.
2. In the Select Source Type page, select VHDL Module or Verilog Module.
3. In the File Name field, enter debounce.
Figure 3-5: New Source Wizard—Select Source Type Page
4. Click Next.
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5. In the Define Module page, enter two input ports named sig_in and clk and an output port named
sig_out for the debounce component as follows:
a. In the first three Port Name fields, enter sig_in, clk and sig_out.
b. Set the Direction field to input for sig_in and clk and to output for sig_out.
c. Leave the Bus designation boxes unchecked.
Figure 3-6: New Source Wizard—Define Module Page
6. Click Next to view a description of the module.

7. Click Finish to open the empty HDL file in the ISE Text Editor.
Following is an example VHDL file.
VHDL File in ISE Text Editor

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OR Gate using If/Else:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or_gate_if_else_vansh is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
o : out STD_LOGIC);
end or_gate_if_else_vansh;
architecture Behavioral_03576802818 of or_gate_if_else_vansh is
begin
process(a,b)
begin
if (a ='0'and b ='0' ) then
o <= '0';
elsif (a='0'and b='1') then
o <= '1';
o <= '1';
o <= '1';
end if;
end process;
end Behavioral_03576802818;
Vansh Tomar | ECE 3 | 03576802818
RTL Schematic
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Testbench
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OR Gate Using When Else
library IEEE;
entity or_gate_when_else_vansh is
b : in STD_LOGIC;
c : out STD_LOGIC);
end or_gate_when_else_vansh;
architecture Behavioral_03576802818 of or_gate_when_else_vansh is
begin
c <= '0' when a = '0'and b = '0' else
'1' when a = '1'and b = '0' else
'Z';
RTL Schematic
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Testbench
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AND Gate using Data Flow

Modelling
library IEEE;
entity andgate_vansh is
b : in STD_LOGIC;
o : out STD_LOGIC);
end andgate_vansh;
architecture Behavioral_03576802818 of andgate_vansh is
begin
o <= a and b;
RTL Schematic
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Testbench
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XOR Gate using When Else
library IEEE;
entity xor_gate_vansh is
b : in STD_LOGIC;
o : out STD_LOGIC);
end xor_gate_vansh;
architecture Behavioral_03576802818 of xor_gate_vansh is
begin
o <= '0' when a = '0'and b='0' else
'Z';
RTL Schematic
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Testbench
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NOT Gate
library IEEE;
entity notgate_vansh is
b : out STD_LOGIC);
end notgate_vansh;
architecture
Behavioral_03576802818 of
notgate_vansh is
begin
b <= not a;
RTL Schematic
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Testbench
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NAND Gate using DFM
library IEEE;
entity nandgate_vansh is
b : in STD_LOGIC;
c : out STD_LOGIC);
end nandgate_vansh;
architecture Behavioral_03576802818 of nandgate_vansh is
begin
c<= a nand b;
RTL Schematic
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Testbench
Vansh Tomar | ECE 3 | 03576802818
NAND Gate with Select statement

library IEEE;
entity nand_gate_vansh is
b : in STD_LOGIC;
c : out STD_LOGIC);
end nand_gate_vansh;
architecture Behavioral_03576802818 of nand_gate_vansh is
signal sel:std_logic_vector(1 downto 0);
begin
sel <= a & b;
with sel select
c <= '1' when "00",
'1' when "01",
'1' when "10",
'0' when "11",
'Z' when others;
RTL Schematic
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Testbench
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NOR Gate DFM

library IEEE;
entity nor_gate_vansh is
b : in STD_LOGIC;
c : out STD_LOGIC);
end nor_gate_vansh;
architecture Behavioral_03576802818 of nor_gate_vansh is
begin
c <= a nor b;
RTL Schematic
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Testbench
Vansh Tomar | ECE 3 | 03576802818
XNOR Gate with Select statement

library IEEE;
entity xnor_gate_vansh is
b : in STD_LOGIC;
c : out STD_LOGIC);
end xnor_gate_vansh;
architecture Behavioral_03576802818 of xnor_gate_vansh is
signal sel:std_logic_vector(1 downto 0);
begin
sel <= a & b;
with sel select
c <= '1' when "00",
'0' when "01",
'0' when "10",
'1' when "11",
'Z' when others;
Vansh Tomar | ECE 3 | 03576802818
RTL Schematic
Testbench
Vansh Tomar | ECE 3 | 03576802818
Half Adder using Behavioural Model

library IEEE;
entity half_adder_vansh is
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end half_adder_vansh;
architecture Behavioral_03576802818 of half_adder_vansh is
begin
process(a,b)
begin
if (a = '0'and b = '0') then
sum <= '0';
carry <= '0';
elsif (a = '0'and b = '1') then
sum <='1';
carry <= '0';
sum <='1';
carry <= '0';
sum <='0';
carry <= '1';
end if ;
end process;
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RTL Schematic
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Testbench
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Half Subtractor
library IEEE;
entity halfsub_vansh is
b : in STD_LOGIC;
diff : out STD_LOGIC;
borr : out STD_LOGIC);
end halfsub_vansh;
architecture Behavioral_03576802818 of halfsub_vansh is
begin
diff <= a xor b;
borr <= ((not a) and b);
RTL Schematic
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TestBench
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Full Adder using DFM
library IEEE;
entity Fadder_vansh is
b : in STD_LOGIC;
ci : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC);
end Fadder_vansh;
architecture Behavioral_03576802818 of Fadder_vansh is
begin
s <= a xor b xor ci;
co <= (a and b) or (b and ci) or (ci and a);
RTL Schematic
Vansh Tomar | ECE 3 | 03576802818
Testbench
Vansh Tomar | ECE 3 | 03576802818
Full Adder using Structural Modelling
library IEEE;
entity full_adder_vansh is
b : in STD_LOGIC;
ci : in STD_LOGIC;
sum : out STD_LOGIC;
co : out STD_LOGIC);
end full_adder_vansh;
architecture Behavioral_03576802818 of full_adder_vansh is
component half_adder_behav_modelling is
port(a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic);
end component;
component or_gate_if_else_vansh is
port(a : in std_logic;
b : in std_logic;
o : out std_logic
);
end component;
signal s1,s2,s3:std_logic;
begin
ha_1 : half_adder_behav_modelling port map(a => a,b => b,sum => s1,carry
=> s2);
ha_2 : half_adder_behav_modelling port map(a => s1,b => ci,sum => sum
,carry => s3);
or_gate : or_gate_if_else_vansh port map(a => s3, b => s2, o => co );
Vansh Tomar | ECE 3 | 03576802818
RTL Schematic
Vansh Tomar | ECE 3 | 03576802818
Testbench
Vansh Tomar | ECE 3 | 03576802818
Full Subtractor
library IEEE;
entity fullsub is
b : in STD_LOGIC;
cin : in STD_LOGIC;
diff : out STD_LOGIC;
borr : out STD_LOGIC);
end fullsub;
architecture Behavioral of fullsub is
begin
diff <= (a xor b) xor cin;
borr <= ((not A) and (B or Cin)) or (B and Cin);
end Behavioral;
RTL Schematic
Vansh Tomar | ECE 3 | 03576802818
Testbench
Vansh Tomar | ECE 3 | 03576802818
MUX 2:1 Using When Else

library IEEE;
entity mux_21_vansh is
b : in STD_LOGIC;
s : in STD_LOGIC;
o : out STD_LOGIC);
end mux_21_vansh;
architecture Behavioral_03576802818 of mux_21_vansh is
begin
o <= a when s = '0' else
b;
RTL Schematic
Vansh Tomar | ECE 3 | 03576802818
Testbench
Vansh Tomar | ECE 3 | 03576802818
MUX 2:1 CASE STATEMENT
library IEEE;
entity m21x_vansh is
b : in STD_LOGIC;
s : in STD_LOGIC;
y : out STD_LOGIC);
end m21x_vansh;
architecture Behavioral_03576802818 of m21x_vansh is

begin
process(a,b,s)
begin
case s is
when '0'=> y <= a;
when '1'=> y <= b;
when others => y <= 'Z';
end case;
end process;
Vansh Tomar | ECE 3 | 03576802818
RTL Schematic
Vansh Tomar | ECE 3 | 03576802818
Testbench
Vansh Tomar | ECE 3 | 03576802818
MUX 4:1 WITH SELECT STATEMENT

library IEEE;
entity mux_41_vansh is
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
s1 : in STD_LOGIC;
s2 : in STD_LOGIC;
y : out STD_LOGIC);
end mux_41_vansh;
architecture Behavioral_03576802818 of mux_41_vansh is
signal s:std_logic_vector(1 downto 0);
begin
s <= s1 & s2;
with s select
y <= a when "00",
b when "01",
c when "10",
d when "11",
'Z' when others;
Vansh Tomar | ECE 3 | 03576802818
RTL Schematic
Vansh Tomar | ECE 3 | 03576802818
Testbench
Vansh Tomar | ECE 3 | 03576802818
MUX 4:1 STRUCTURAL MODELLING

library IEEE;
entity mux_41_sm_vansh is
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
s1 : in STD_LOGIC;
s2 : in STD_LOGIC;
q : out STD_LOGIC);
end mux_41_sm_vansh;
architecture Behavioral_03576802818 of mux_41_sm_vansh is
component mux_21_vansh is
port (a,b,s :in std_logic;
o : out std_logic);
end component;
signal m,n:std_logic;
begin
mux1: mux_21_vansh port map(a,b,s1,m);
mux2: mux_21_vansh port map(c,d,s1,n);
mux3: mux_21_vansh port map(m,n,s2,q);
Vansh Tomar | ECE 3 | 03576802818
RTL Schematic
Vansh Tomar | ECE 3 | 03576802818
Testbench
Vansh Tomar | ECE 3 | 03576802818
DECODER 2:1 BEHAVIOURAL MODELLING

library IEEE;
entity decoder_21_vansh is
Port ( a : in STD_LOGIC_vector(1 downto 0);
y : out STD_LOGIC_vector(3 downto 0)
);
end decoder_21_vansh;
architecture Behavioral_03576802818 of decoder_21_vansh is
begin
process(a)
begin
if (a = "00") then
y <= "0001";
elsif (a = "10") then
y <= "0100";
y <= "0010";
y <= "1000";
end if;
end process;
Vansh Tomar | ECE 3 | 03576802818
RTL Schematic
Vansh Tomar | ECE 3 | 03576802818
Testbench
Vansh Tomar | ECE 3 | 03576802818
D FLIP FLOP SYNCHRONOUS

library IEEE;
entity d_flip_flop_vansh is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC);
end d_flip_flop_vansh;
architecture Behavioral_03576802818 of d_flip_flop_vansh is
begin
process(clk,reset)
begin
if (reset = '1') then
q <= '0';
elsif (clk = '1') then
q <= d;
end if ;
end process;
Vansh Tomar | ECE 3 | 03576802818
RTL Schematic
Vansh Tomar | ECE 3 | 03576802818
Testbench
Vansh Tomar | ECE 3 | 03576802818
JK FLIP FLOP
library IEEE;
entity jk_flip_flop_vansh is
port (j : in std_logic;
k : in std_logic;
clk : in std_logic;
reset : in std_logic;
q : out std_logic
);
end jk_flip_flop_vansh;
architecture Behavioral_03576802818 of jk_flip_flop_vansh is
signal s:std_logic;
begin
process(clk,reset)
begin
s <= '0';
if (j = '0'and k = '0') then
s <= s;
elsif (j = '0'and k = '1') then
s <= '0';
s <= '1';
s <= not s;
end if;
end if;
q<= s;
end process;
Vansh Tomar | ECE 3 | 03576802818
RTL Schematic
Vansh Tomar | ECE 3 | 03576802818
Testbench
Vansh Tomar | ECE 3 | 03576802818
T FLIP FLOP
library IEEE;
entity t_flip_flop_vansh is
Port ( t : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC);
end t_flip_flop_vansh;
architecture Behavioral_03576802818 of t_flip_flop_vansh is
signal s:std_logic;
begin
process(clk,reset)
begin
s <= '0';
if (t ='0') then
s <= s;
elsif(s = '1') then
s <= not s;
end if;
end if;
q <= s;
end process;
Vansh Tomar | ECE 3 | 03576802818
RTL Schematic
Vansh Tomar | ECE 3 | 03576802818
Testbench
Vansh Tomar | ECE 3 | 03576802818
RS FLIP FLOP
library IEEE;
entity rs_flip_flop_vansh is
Port ( r : in STD_LOGIC;
s : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC);
end rs_flip_flop_vansh;
architecture Behavioral_03576802818 of rs_flip_flop_vansh is
signal p:std_logic;
begin
process(clk,reset)
begin
p <= '0';
if (r = '0'and s = '0') then
p <= p;
elsif (r = '0'and s = '1') then
p <= '0';
p <= '1';
p <= '-';
end if ;
end if;
q <= p;
end process;
Vansh Tomar | ECE 3 | 03576802818
RTL Schematic
Vansh Tomar | ECE 3 | 03576802818
Testbench
Vansh Tomar | ECE 3 | 03576802818
MELAY MACHINE
library IEEE;
entity melay_000_vansh is
Port ( clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC);
end melay_000_vansh;
architecture Behavioral_03576802818 of melay_000_vansh is
type state_type is (s0,s1,s2);
signal current_s,next_s:state_type;
begin
process(clk,reset)
begin
current_s <= s0;
elsif(rising_edge(clk)) then
current_s <= next_s;
end if;
end process;
process(current_s,input)
begin
case current_s is
when s0=>
if (input = '1') then
output <= '0';
next_s<=s0;
else
output <= '0';
Vansh Tomar | ECE 3 | 03576802818
next_s<=s1;
end if;
when s1 =>
if (input = '0') then
output <= '0';
next_s <= s2;
else
output <= '0';
next_s <= s0;
end if;
when s2 =>
if(input = '0') then
output <= '1';
next_s <= s0;
else
output <= '0';
next_s <= s0;
end if ;
end case;
end process;
RTL Schematic
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Testbench Simulation
Vansh Tomar | ECE 3 | 03576802818
Vansh Tomar | ECE 3 | 03576802818
SISO (SERIAL IN SERIAL OUT) BY USING

SM
library IEEE;
entity siso_vansh is
Port ( si : in STD_LOGIC;
clk : in STD_LOGIC;
so : out STD_LOGIC);
end siso_vansh;
architecture Behavioral_03576802818 of siso_vansh is
component d_flip_flop_syn is
port (d : in std_logic;
clk : in std_logic;
reset : in std_logic;
q : out std_logic
);
end component;
signal t1,t2,t3:std_logic;
begin
d1 :d_flip_flop_syn port map(si,clk,reset,t1);
d2 :d_flip_flop_syn port map(t1,clk,reset, t2);
d3 :d_flip_flop_syn port map(t2,clk,reset,t3);
d4 :d_flip_flop_syn port map(t3,clk,reset,so );
Vansh Tomar | ECE 3 | 03576802818
RTL Schematic
Vansh Tomar | ECE 3 | 03576802818
Testbench
Vansh Tomar | ECE 3 | 03576802818
Conclusion
 Learning about VLSI designing has helped me to understand the working of many
Application Specific Integrated Circuits that are used even in daily appliances like
Refrigerator, Washing Machines etc.
 RTL designing has much scope in the hardware sector in upcoming time in India as the
semiconductor market is worth $250 billion. Hence, the knowledge of VHDL also
increases the employability.
 Through my summer training, came out of the conventional subjects and gained a small
experience of the current hardware industries requirements and expectations.
 Apart from VHDL, there are also come other languages available for the Hardware
Description such as Verilog and System C which have their own benefits and
drawbacks. Yet, there knowledge certainly helps in becoming a good RTL designer.
 The main purpose of designing a code is to make it synthesizable rather than focusing
it to be a code that can be successfully simulated. Hence, during programming a
programmable device, certain hardware restrictions should always be put in mind.
Future Prospects
Results VHDL, one of the biggest jobs providing sector today, have a very bright future in the
coming time, but as the time is passing some other languages are making control over
designing, as for example Verilog HDL. Verilog HDL is little bit better in processing speed
than VHDL. But on the other hand, VHDL is also better in some fields like, all the three styles
of modelling (Data flow, Behavioural, Structural) in VHDL can be mixed together in the same
program i.e. VHDL is more user friendly than Verilog HDL.
But today all over world mainly VHDL is used for chip designing at low level. Till now there
are number of drawbacks in VHDL. As main drawback of VHDL is that, there are a number
of features in VHDL, that can be simulated but not synthesized. As, final shape to VHDL was
given by IEEE, hence IEEE is working on it continuously and trying to make available
simulation features to synthesis also.
So, if talk about future prospectus of VHDL, it depends on success of IEEE. If IEEE got able
to implement such features that there remain no differences between simulation & synthesis
with higher processing speed and designing up to lower level of abstraction, on that day VHDL
may take hold over all other HDL.s.
Vansh Tomar | ECE 3 | 03576802818
References
[1] M. Mano and C. Kime, “Logic and Computer Design Fundamentals.” 2nd Edition,
Prentice Hall, Upper Saddle River, 2001.
[2] S. Yalamanchili, "WHDL Starter’s Guide.” Prentice Hall, Upper Saddle River, 1998.
[3] J. Bhasker, “WHDL Primer,” 3rd Edition, Prentice Hall, Upper Saddle River, 1998.
[4] Douglas L. Perry,” VHDL Programming by Examples”, 41 Edition. TMH.
[5] C. EL Roth, “Digital System Design using VIIDL”, PWS Publishing

Vansh Tomar - 035 - Training Report VHDL - ECE 3

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Thesis/Report submitted in partial fulfilment of the requirement for the degree of

Electronics and Communications Engineering

Mr. Mukesh Sahu

Guru Tegh Bahadur Institute of Technology, Delhi

2.2.2 Dataflow Modeling………………………………………………………………………………………………11

2.2.3 Structural Modeling…………………………………………………………………………………………….11

2.2.3.1 Component Declaration ........................................................................................ 16

2.3 Libraries in VHDL………………………………………………………………………………………………….…14

2.3.1 Design Library……………………………………………………………………………………………………15

2.4 Putting It Together!! ……………………………………………………………………………………………16

3.1.6. Bit Strings………………………………………………………………………………………………………….17

3.2 Data Types and Objects……………………………………………………………………………………………

3.2.1. Integer Types .......................................................................................................... 22

3.2.2. Physical Types ........................................................................................................ 23

 Software Overview (Xillinx)

1.1 What Is VHDL?

• It supports a wide range, of abstraction levels ranging from abstract behavioral

2.1.5 Package Body

2.2 Levels of Abstraction

2.2.1 Behavioral Modeling

2.2.2 Dataflow Modeling

2.2.3 Structural Modeling

2.2.3.1 Component Declaration

2.2.3.2 Component Instantiation A component instantiation is a statement that

2.3 Libraries in VHDL

2.3.1 Design Library

2.3.2 Use Statement

2.4 Putting It Together!!

3. Basic Language Elements

3.1. Lexical Elements

based_literal ::= base # based_integer [ . based_integer ] # [ exponent ] base

3.1.6. Bit Strings

3.2 Data Types and Objects

3.2.1. Integer Types

An integer type is a range of integer values within a specified range.

range_constraint ::= range range

range ::= simple_expression direction simple_expression

direction ::= to | downto

3.2.2. Physical Types

Some examples of physical type declarations:

3.2.3. Floating Point Types

3.2.4. Enumeration Types

Some examples are:

'p', 'q', 'r', 's', 't', 'u', 'v', 'w',

Subtypes, referred to in this syntax specification, will be discussed in detail in Section2.2.7.

3.2.8. Object Declarations

3.3.Expressions and Operators

3.4. Sequential Statements

3.4.1. Variable Assignment

3.4.3. Case Statement

3.4.4. Loop Statements

iteration_scheme ::= while

3.4.5. Null Statement

case controller_command is when forward =>

Project Navigator Interface

Error Navigation to Source

Error Navigation to Answer Record

Design Summary/Report Viewer

Using Project Revision Management Features

Project Navigator enables you to manage your project as follows.

Understanding the ISE Project File

Making a Copy of a Project

Using the Project Browser