SRM INSTITUTE OF SCIENCE AND TECHNOLOGY

VADAPALANI CAMPUS
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
18CSC203J- COMPUTER ORGANIZATION AND ARCHITECTURE
QUESTION BANK
Unit – 1
4 Marks
1.Define computer.
A computer is an electronic device that manipulates information, or data. It has the ability to store, retrieve, and
process data. You may already know that you can use a computer to type documents, send email, play games, and browse
the Web.

2.Define program counter and instruction register.

The program counter (PC) holds the address of the next instruction to be executed, while the instruction
register (IR) holds the encoded instruction. Upon fetching the instruction, the program counter is incremented by one
"address value" (to the location of the next instruction).
he program counter and an instruction register are both registers located in the control unit within a computer processor.

The program counter points to the address of the instruction currently being executed or the next instruction to be executed
(depending on the processor), and is usually incremented after the execution of each instruction.

An instruction register contains the information relating to an instruction currently being decoded or executed. The register
contains an opcode and an operand. The opcode is the part which species the nature of the operation to be performed, and the
operand specifies the data which is going to undergo that operation.

3.Differentiate big endian and little endian.

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 All computers do not store the bytes that comprise a multi-byte value in the same order. Consider a 16-bit internet that
is made up of 2 bytes. Two ways to store this value −

• Little Endian − In this scheme, low-order byte is stored on the starting address (A) and high-order byte is stored on the
next address (A + 1).

• Big Endian − In this scheme, high-order byte is stored on the starting address (A) and low-order byte is stored on the
next address (A + 1).
To allow machines with different byte order conventions communicate with each other, the Internet protocols specify a
canonical byte order convention for data transmitted over the network. This is known as Network Byte Order.
By these definitions, a 32-bit data pattern, which is regarded as a 32-bit unsigned integer. The "high- Order" byte is the one
for the largest powers of 2: 231, ..., 224. The "low-order" byte is the one for the smallest powers of 2: 27, ..., 20.

Example
0x12674592 in 32-bit representation can be stored as −

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4.List out the different types of computer.
Classes by purpose
• Microcomputers (personal computers)
• Minicomputers (mid-range computers)
• Mainframe computers.
• Supercomputers.
• Servers.
• Workstations.

5.Differentiate multiprocessors and multicomputers.

Multiprocessor
• It consists of multiple processors within a single computer.

• It is a singly shared memory that is attached to the elements being processed.

• It is necessary for the processing elements to communicate with each other.

• It is a dynamic network.

• Example of multiprocessor is a sequent symmetry S-81.

Multicomputer
• It is an interlinked multiple autonomous computer.

• The memory attached to the processing elements are distributed in multiples.

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 • It is not required for elements being processed to communicate.

• It is a type of static network.

• Example of a multicomputer is a message passing multicomputer.

6.Define LOAD and STORE operations.

Load and store instructions involve actions affecting both the processor and the memory. While executing, both load
and stores must first wait for their addresses to be computed by an ALU or address unit. Then, loads can access the data
cache to fetch the requested memory data which is then made available in a register. The load is then completed usually by
writing the fetched data into the specified architectural register.
Stores have a different execution pattern. After receiving their generated addresses, stores have to wait for their operands to
be available. Unlike other instructions, a store is considered to be finished when operands become available. Now let us
consider a ROB is in use. When the ROB indicates that the store comes next in sequential execution, the memory address
and data to be stored are forwarded to the cache, and a cache store operation is initiated.
A processor that supports weak memory consistency allows the reordering of memory accesses. This is beneficial for at least
three methods −

• It allows load/store bypassing.

• It creates speculative loads or stores achievable
• It enables cache misses to be secret

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7.Define bus structure.
BUS structure : A group of lines that serves as a connecting path for several devices is called bus.In addition to
the lines that carry the data, the bus must have lines for address and control purposes.
In computer architecture, a bus is a subsystem that transfers data between computer components inside
a computer or between computers

A computer bus structure is provided which permits replacement of removable modules during operation of a
computer wherein means are provided to precharge signal output lines to within a predetermined range prior to the
usage of the signal output lines to carry signals, and further, wherein means are provided to minimize arcing to pins
designed to carry the power and signals of a connector. In a specific embodiment, pin length, i.e., separation between
male and female components of the connector, are subdivided into long pin length and short pin length. Ground
connections and power connections for each voltage level are assigned to the long pin lengths. Signal connections
and a second power connection for each voltage level is assigned to the short pin lengths.

8.Define word and word length.

The most common processors are/were 8 bit, 16 bit, 32 bit or 64 bit. These are the WORD lengths of the
processor. Actually half of a WORD is a BYTE, whatever the numerical length is. Ready for this, half of a BYTE is a
NIBBLE. A byte may have more than or fewer than 8 bits (although this is relatively rare). ... The term 'word' is used to
describe the number of bits processed at a time by a program or operating system. So, in a 16-bit CPU, the word length
is 16 bits. In a 32-bit CPU, the word length is 32 bits.
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The hardware registers in a computer machine are word sized. ... In this context, a word is the unit that a machine uses
when working with memory. For example, on a 32 bit machine, the word is 32 bits long and on a 64 bit is 64 bits long.
The word size determines the address space.

9.Define flags and different types of flags.

A flag is one or more data bits used to store binary values as specific program structure indicators. A
flag is a component of a programming language's data structure.

A computer interprets a flag value in relative terms or based on the data structure presented during
processing, and uses the flag to mark a specific data structure. Thus, the flag value directly impacts the
processing outcome.
But only five flags are implemented in 8085. And they are:

• Carry flag (Cy),

• Auxiliary carry flag (AC),

• Sign flag (S),

• Parity flag (P), and

• Zero flag (Z).

10.List out the features of 8086 microprocessor.

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 SALIENT FEATURES OF 8086 MICROPROCESSOR
• Single +5V power supply.
• Clock speed range of 5-10MHz.
• capable of executing about 0.33 MIPS (Millions instructions per second)
• It is 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and 16-bit external data bus resulting in
faster processing.

11.List out the addressing modes supported by 8086 microprocessor.

8086 Addressing Modes
• Immediate addressing mode. ...
• Register addressing mode. ...
• Direct addressing mode. ...
• Register indirect addressing mode. ...
• Based addressing mode. ...
• Indexed addressing mode. ...
• Based-index addressing mode. ...
• Based indexed with displacement mode.

12.List out the types of instructions supported by 8086 microprocessor.

8086 Instruction Sets
• Data Transfer Instructions.
• Arithmetic Instructions.
• Bit Manipulation Instructions.
• String Instructions.
• Program Execution Transfer Instructions (Branch & Loop Instructions)
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 • Processor Control Instructions.
• Iteration Control Instructions.
• Interrupt Instructions.

13.Define ARM processor.

An ARM processor is one of a family of CPUs based on the RISC (reduced instruction set computer) architecture developed by
Advanced RISC Machines (ARM). ... ARM processors are extensively used in consumer electronic devices such as smartphones, tablets,
multimedia players and other mobile devices, such as wearables.

14.Differentiate 8085 and 8086 microprocessor.

Serial
No. 8085 microprocessor 8086 microprocessor

1 The data bus is of 8 bits. The data bus is of 16 bits.

2 The address bus is of 16 bits. The address bus is of 20 bits.

The memory capacity is 64 KB.Also 8085 Can Perform The memory capacity is 1 MB.Also 8086
Operation Upto 2^8 ie. 256 numbers. A number greater Can Perform Operation upto 2^16 ie.
3 than this is to taken multiple times in 8 bit data bus. 65,536 numbers.

The input/output port addresses are of 8

4 The input/output port addresses are of 8 bits. bits.

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Serial
No. 8085 microprocessor 8086 microprocessor

The operating frequency is 5 MHz,

5 The operating frequency is 3.2 MHz. 8MHZ,10MHZ.

8086 MP has Two Modes Of Operation.

1. Minimum Mode = SingLe CPU
PROCESSOR
2. Maximum Mode = Multiple CPU
5 8085 MP has Single Mode Of Operation. PROCESSOR.

It have multiplication and division

6 It not have multiplication and division instructions. instructions.

It supports pipe-lining as it has two

independent units Execution Unit (EU)
7 It does not support pipe-lining. and Bus Interface Unit (BIU).

8 It does not support instruction queue. It supports instruction queue.

9 Memory space is not segmented. Memory space is segmented.

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12 Marks
1.Explain about the functional units of computer along with neat diagram.

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1. Input Unit: Its aim is to supply data (Alphanumeric, image , audio, video, etc.) to the computer for processing. The Input
devices are keyboard, mouse, scanner, mic, camera, etc
2. Central Processing Unit (CPU): It is the brain of the computer and consists of three components Arithmetic Logic
Unit(ALU): As the name implies it performs all calculations and comparison operations. Control Unit(CU): It controls overall
functions of a computer Registers: It stores the intermediate results temporarily.
3. Storage Unit(Memory Unit): A computer has huge storage capacity. It is used to store data and instructions before starts
the processing. Secondly it stores the intermediate results and thirdly it stores information(processed data), that is the final
results before send to the output unit(Visual Display Unit, Printer, etc)
Two Types of storage unit
(a) Primary Storage alias Main Memory: It is further be classified into Two- Random Access Memory(RAM) and Read Only
Memory(ROM). The one and only memory that the CPU can directly access is the main memory at a very high speed. It is
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expensive hence storage capacity is less. RAM is volatile (when the power is switched off the content will be erased) in
nature but ROM is non volatile(lt is permanent)
(b) Secondary Storage alias Auxiliary Memory: Because of limited storage capacity of primary memory its need arises.
When a user saves a file, it will be stored in this memory hence it is permanent in nature and its capacity is huge. eg: Hard
Disc Drive(HDD), Compact Disc(CD), DVD, Pen Drive, Blu Ray Disc etc.
4. Output Unit: After processing the data we will get information as result, that will be given to the end user through the
output unit in a human readable form. Normally monitor and printer are used.

2.Explain about the different types of instruction formats.

1. Zero Address Instructions –

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A stack-based computer does not use the address field in the instruction. To evaluate an expression first it is
converted to reverse Polish Notation i.e. Postfix Notation.
Expression: X = (A+B)*(C+D)
Postfixed : X = AB+CD+*
TOP means top of stack
M[X] is any memory location

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 PUSH A TOP = A

PUSH B TOP = B

ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

MUL TOP = (C+D)*(A+B)

POP X M[X] = TOP

s temporary location

LOAD A AC = M[A]

ADD B AC = AC + M[B]

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 STORE T M[T] = AC

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STORE X M[X] = AC

Here destination address can also contain operand.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]

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 MOV R2, C R2 = C

ADD R2, D R2 = R2 + D

MUL R1, R2 R1 = R1 * R2

MOV X, R1 M[X] = R1

[] is any memory location

ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]

MUL X, R1, R2 M[X] = R1 * R2

3.Explain about the operational concepts of CPU.

4.Describe about the execution of straight line instructions and branch instructions.

Instruction execution and straight line sequencing

• Instruction execution needs the following steps, which are
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 • PC (program counter) register of the processor gives the address of the instruction which needs
to be fetched from the memory.
• If the instruction is fetched then, the instruction opcode is decoded. On decoding, the processor
identifies the number of operands. If there is any operand to be fetched from the memory, then
that operand address is calculated.
• Operands are fetched from the memory. If there is more than one operand, then the operand
fetching process may be repeated (i.e. address calculation and fetching operands).
• After this, the data operation is performed on the operands, and a result is generated.
• If the result has to be stored in a register, the instructions end here.
• If the destination is memory, then first the destination address has to be calculated. Then the
result is then stored in the memory. If there are multiple results which need to be stored inside
the memory, then this process may repeat (i.e. destination address calculation and store result).
• Now the current instructions have been executed. Side by side, the PC is incremented to
calculate the address of the next instruction.
• The above instruction cycle then repeats for further instructions.

5..Define addressing modes and Explain about different types of addressing modes.

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 Addressing Modes

Addressing Modes

Different ways in which the location of the operand is specified in an instruction is

referred as addressing modes
The purpose of using addressing mode is:
To give the programming versatility to the user.
To reduce the number of bits in addressing field of instruction.
Types of Addressing Modes
• Immediate Addressing
• Direct Addressing
• Indirect Addressing
• Register Addressing
• Register Indirect Addressing
• Relative Addressing
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• Indexed Addressing
• Auto Increment
• Auto Decrement

Immediate Addressing
• Operand is given explicitly in the instruction
• e.g. ADD 5
– Add 5 to contents of accumulator
– 5 is operand
• No memory reference to fetch data
• Fast
• Limited range
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• MOV AL,25H ; Immediate addressing AL=25
• MOV AX,2345H ; AX=2345 AX=> AH=23 AL=45
Direct Addressing
• Address field contains address of operand
• Effective address (EA) = address field (A)
• e.g. ADD A
– Add contents of cell A to accumulator
– Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective address
• Limited address space
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• MOV AL,DATA1 ; Direct Addressing AL=23
• MOV AX,DATA2 ; AX=1234
• MOV DATA3,AL ; DATA3=23
• MOV DATA4,AX ; DATA4=1234

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 Indirect Addressing

• Memory cell pointed to by address field contains the address of

(pointer to) the operand
Two references to memory are required to fetch the operand.
• Effective Address = [A]
– Look in A, find address (A) and look there for operand •
e.g. ADD (A)
– Add contents of cell pointed to by contents of A to the
accumulator

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 Register Direct Addressing

In this addressing mode,

• The operand is contained in a register set.
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• The address field of the instruction refers to a CPU register that
contains the operand.
• No memory access
• Very fast execution
• Very limited address space
• Limited number of registers
• Very small address field needed
– Shorter instructions
– Faster instruction fetch
Register Direct Addressing

Eg:
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ADD R will increment the value stored in
the accumulator by the content of register R.
AC ← AC + [R]
• This addressing mode is similar to direct addressing
mode.
• The only difference is address field of the instruction
refers to a CPU register instead of main memory.

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 Register Indirect Addressing

• The address field of the instruction refers to a CPU

register that contains the effective address of the
operand.
• Only one reference to memory is required to fetch the
operand Eg:
ADD R will increment the value stored in the
accumulator by the content of memory location
specified in register R.
AC ← AC + [[R]]

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 Indexed Addressing

In this addressing mode,

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• Effective address of the operand is obtained by adding
the content of index register with the address part of
the instruction.

Effective Address
= Content of Index Register +
Address part of the instruction

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31
 Relative Addressing

A version of displacement addressing

In this addressing mode,
• Effective address of the operand is obtained by adding the
content of program counter with the address part of the
instruction.
Effective Address
= Content of Program Counter + Address part of
the instruction

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Auto increment mode
A special case of Register Indirect Addressing Mode where
Effective Address of the Operand
= Content of Register

In this addressing mode,

• After accessing the operand, the content of the register is
automatically incremented by step size ‘d’.
• Step size ‘d’ depends on the size of operand accessed.
• Only one reference to memory is required to fetch the operand.

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35
 Auto decrement mode

• A special case of Register Indirect Addressing Mode where

Effective Address of the Operand
= Content of Register – Step Size

In this addressing mode

• First, the content of the register is decremented by step size ‘d’.
• Step size ‘d’ depends on the size of operand accessed.
• After decrementing, the operand is read.
• Only one reference to memory is required to fetch the operand.

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5.Explain in detail about the architechture of 8086 microprocessor a,ong with neat diagram.
6.Explain in detail about the pin diagram of 8086 microprocessor along with neat diagram.
7.Explain in detail about the ARM Processor .

The ARM Architecture

ARM Ltd

The first ARM processor was developed in

the year 1978 by Cambridge University, and
the first ARM RISC processor was produced
by the Acorn Group of Computers in the year
1985. An ARM processor is one of a family
of CPUs based on the RISC (reduced
instruction set computer) architecture
developed by Advanced RISC Machines
(ARM).
ARM makes 32-bit and 64-bit RISC multi-
core processors.
RISC processors are designed to perform a
smaller number of types of computer
instructions so that they can operate at a
higher speed, performing more millions of
instructions per second (MIPS). By stripping
out unneeded instructions and optimizing
pathways, RISC processors provide
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 outstanding performance at a fraction of the
power demand of CISC (complex instruction
set computing) devices.
ARM Ltd

ARM processors are extensively used in

consumer electronic devices such as
smartphones, tablets, multimedia players and
other mobile devices, such as wearables.
The ARM processor’s smaller size, reduced
complexity and lower power consumption
makes them suitable for increasingly
miniaturized devices.
ARM processor features include:
❖ Load/store architecture.
❖ An orthogonal instruction set.
❖ Mostly single-cycle execution.
❖ Enhanced power-saving design.
❖ 64 and 32-bit execution states for scalable
high performance.
❖ Hardware virtualization support.
RISC

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 • RISC is an abbreviation of Reduced
Instruction Set Computer.
• RISC processor has ‘instruction sets’ that are
simple and have simple ‘addressing modes’.
• A RISC style instruction engages “one word”
in memory.
• Execution of the RISC instructions are faster
and take one clock cycle per instruction.
• RISC architecture emphasizes on using the
registers rather than memory.
• The RISC instructions operate on the
operands present in processor’s registers.
• RISC is a type of microprocessor architecture
that utilizes a small, highly-optimized set of
instructions, rather than a more specialized
set of instructions often found in other types
of architectures.
ARM Processor Architecture

• The ARM architecture processor is an

advanced reduced instruction set computing
[RISC] machine and it’s a 32bit reduced

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 instruction set computer (RISC)
microcontroller.
• It was introduced by the Acron computer
organization in 1987.
• This ARM is a family of microcontroller
developed by makers like ST
Microelectronics, Motorola, and so on.
• The ARM architecture comes with totally
different versions like ARMv1, ARMv2, etc.,
and, each one has its own advantage and
disadvantages.
• The ARM cortex is a complicated
microcontroller within the ARM family that
has ARMv7 design.
• There are 3 subfamilies within the ARM
cortex family :
– ARM Cortex Ax-
series – ARM-
Cortex Rx-series
– ARM-Cortex Mx-
series
ARM Architecture

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The ARM Architecture covers the below
mentioned components.
• Arithmetic Logic Unit
• Booth multiplier
• Barrel shifter
• Control unit
• Register file
The ARM processor conjointly has other
components like the Program status register,

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which contains the processor flags (Z, S, V and
C).
The modes bits conjointly exist within the
program standing register, in addition to the
interrupt and quick interrupt disable bits.
Some registers are used like the instruction,
memory data read and write registers and
memory address register.

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